diff options
Diffstat (limited to 'arch/mips/sni')
| -rw-r--r-- | arch/mips/sni/Makefile | 7 | ||||
| -rw-r--r-- | arch/mips/sni/int-handler.S | 106 | ||||
| -rw-r--r-- | arch/mips/sni/irq.c | 194 | ||||
| -rw-r--r-- | arch/mips/sni/pcimt_scache.c | 37 | ||||
| -rw-r--r-- | arch/mips/sni/reset.c | 51 | ||||
| -rw-r--r-- | arch/mips/sni/setup.c | 203 |
6 files changed, 598 insertions, 0 deletions
diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile new file mode 100644 index 000000000000..1e5676e4be86 --- /dev/null +++ b/arch/mips/sni/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the SNI specific part of the kernel +# + +obj-y += int-handler.o irq.o pcimt_scache.o reset.o setup.o + +EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/sni/int-handler.S b/arch/mips/sni/int-handler.S new file mode 100644 index 000000000000..2cdc09f55f18 --- /dev/null +++ b/arch/mips/sni/int-handler.S @@ -0,0 +1,106 @@ +/* + * SNI RM200 PCI specific interrupt handler code. + * + * Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000, 01 by Ralf Baechle + */ +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/regdef.h> +#include <asm/sni.h> +#include <asm/stackframe.h> + +/* + * The PCI ASIC has the nasty property that it may delay writes if it is busy. + * As a consequence from writes that have not graduated when we exit from the + * interrupt handler we might catch a spurious interrupt. To avoid this we + * force the PCI ASIC to graduate all writes by executing a read from the + * PCI bus. + */ + .set noreorder + .set noat + .align 5 + NESTED(sni_rm200_pci_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + /* Blinken light ... */ + lb t0, led_cache + addiu t0, 1 + sb t0, led_cache + sb t0, PCIMT_CSLED # write only register + .data +led_cache: .byte 0 + .text + + mfc0 t0, CP0_STATUS + mfc0 t1, CP0_CAUSE + and t0, t1 + + andi t1, t0, 0x0800 # hardware interrupt 1 + bnez t1, _hwint1 + andi t1, t0, 0x4000 # hardware interrupt 4 + bnez t1, _hwint4 + andi t1, t0, 0x2000 # hardware interrupt 3 + bnez t1, _hwint3 + andi t1, t0, 0x1000 # hardware interrupt 2 + bnez t1, _hwint2 + andi t1, t0, 0x8000 # hardware interrupt 5 + bnez t1, _hwint5 + andi t1, t0, 0x0400 # hardware interrupt 0 + bnez t1, _hwint0 + nop + + j restore_all # spurious interrupt + nop + + ############################################################################## + +/* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug + button interrupts. */ +_hwint0: jal pciasic_hwint0 + move a0, sp + j ret_from_irq + nop + +/* + * hwint 1 deals with EISA and SCSI interrupts + */ +_hwint1: jal pciasic_hwint1 + move a0, sp + j ret_from_irq + nop + + +/* + * This interrupt was used for the com1 console on the first prototypes; + * it's unsed otherwise + */ +_hwint2: jal pciasic_hwint2 + move a0, sp + j ret_from_irq + nop + +/* + * hwint 3 are the PCI interrupts A - D + */ +_hwint3: jal pciasic_hwint3 + move a0, sp + j ret_from_irq + nop + +/* + * hwint 4 is used for only the onboard PCnet 32. + */ +_hwint4: jal pciasic_hwint4 + move a0, sp + j ret_from_irq + nop + +/* hwint5 is the r4k count / compare interrupt */ +_hwint5: jal pciasic_hwint5 + move a0, sp + j ret_from_irq + nop + + END(sni_rm200_pci_handle_int) diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c new file mode 100644 index 000000000000..62c760f14674 --- /dev/null +++ b/arch/mips/sni/irq.c @@ -0,0 +1,194 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 Linus Torvalds + * Copyright (C) 1994 - 2000 Ralf Baechle + */ +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> + +#include <asm/i8259.h> +#include <asm/io.h> +#include <asm/sni.h> + +DEFINE_SPINLOCK(pciasic_lock); + +extern asmlinkage void sni_rm200_pci_handle_int(void); + +static void enable_pciasic_irq(unsigned int irq) +{ + unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); + unsigned long flags; + + spin_lock_irqsave(&pciasic_lock, flags); + *(volatile u8 *) PCIMT_IRQSEL |= mask; + spin_unlock_irqrestore(&pciasic_lock, flags); +} + +static unsigned int startup_pciasic_irq(unsigned int irq) +{ + enable_pciasic_irq(irq); + return 0; /* never anything pending */ +} + +#define shutdown_pciasic_irq disable_pciasic_irq + +void disable_pciasic_irq(unsigned int irq) +{ + unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2)); + unsigned long flags; + + spin_lock_irqsave(&pciasic_lock, flags); + *(volatile u8 *) PCIMT_IRQSEL &= mask; + spin_unlock_irqrestore(&pciasic_lock, flags); +} + +#define mask_and_ack_pciasic_irq disable_pciasic_irq + +static void end_pciasic_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_pciasic_irq(irq); +} + +static struct hw_interrupt_type pciasic_irq_type = { + "ASIC-PCI", + startup_pciasic_irq, + shutdown_pciasic_irq, + enable_pciasic_irq, + disable_pciasic_irq, + mask_and_ack_pciasic_irq, + end_pciasic_irq, + NULL +}; + +/* + * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug + * button interrupts. Later ... + */ +void pciasic_hwint0(struct pt_regs *regs) +{ + panic("Received int0 but no handler yet ..."); +} + +/* This interrupt was used for the com1 console on the first prototypes. */ +void pciasic_hwint2(struct pt_regs *regs) +{ + /* I think this shouldn't happen on production machines. */ + panic("hwint2 and no handler yet"); +} + +/* hwint5 is the r4k count / compare interrupt */ +void pciasic_hwint5(struct pt_regs *regs) +{ + panic("hwint5 and no handler yet"); +} + +static unsigned int ls1bit8(unsigned int x) +{ + int b = 7, s; + + s = 4; if ((x & 0x0f) == 0) s = 0; b -= s; x <<= s; + s = 2; if ((x & 0x30) == 0) s = 0; b -= s; x <<= s; + s = 1; if ((x & 0x40) == 0) s = 0; b -= s; + + return b; +} + +/* + * hwint 1 deals with EISA and SCSI interrupts, + * + * The EISA_INT bit in CSITPEND is high active, all others are low active. + */ +void pciasic_hwint1(struct pt_regs *regs) +{ + u8 pend = *(volatile char *)PCIMT_CSITPEND; + unsigned long flags; + + if (pend & IT_EISA) { + int irq; + /* + * Note: ASIC PCI's builtin interrupt achknowledge feature is + * broken. Using it may result in loss of some or all i8259 + * interupts, so don't use PCIMT_INT_ACKNOWLEDGE ... + */ + irq = i8259_irq(); + if (unlikely(irq < 0)) + return; + + do_IRQ(irq, regs); + } + + if (!(pend & IT_SCSI)) { + flags = read_c0_status(); + clear_c0_status(ST0_IM); + do_IRQ(PCIMT_IRQ_SCSI, regs); + write_c0_status(flags); + } +} + +/* + * hwint 3 should deal with the PCI A - D interrupts, + */ +void pciasic_hwint3(struct pt_regs *regs) +{ + u8 pend = *(volatile char *)PCIMT_CSITPEND; + int irq; + + pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD); + clear_c0_status(IE_IRQ3); + irq = PCIMT_IRQ_INT2 + ls1bit8(pend); + do_IRQ(irq, regs); + set_c0_status(IE_IRQ3); +} + +/* + * hwint 4 is used for only the onboard PCnet 32. + */ +void pciasic_hwint4(struct pt_regs *regs) +{ + clear_c0_status(IE_IRQ4); + do_IRQ(PCIMT_IRQ_ETHERNET, regs); + set_c0_status(IE_IRQ4); +} + +void __init init_pciasic(void) +{ + unsigned long flags; + + spin_lock_irqsave(&pciasic_lock, flags); + * (volatile u8 *) PCIMT_IRQSEL = + IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD; + spin_unlock_irqrestore(&pciasic_lock, flags); +} + +/* + * On systems with i8259-style interrupt controllers we assume for + * driver compatibility reasons interrupts 0 - 15 to be the i8295 + * interrupts even if the hardware uses a different interrupt numbering. + */ +void __init arch_init_irq(void) +{ + int i; + + set_except_vector(0, sni_rm200_pci_handle_int); + + init_i8259_irqs(); /* Integrated i8259 */ + init_pciasic(); + + /* Actually we've got more interrupts to handle ... */ + for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &pciasic_irq_type; + } + + change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); +} diff --git a/arch/mips/sni/pcimt_scache.c b/arch/mips/sni/pcimt_scache.c new file mode 100644 index 000000000000..a59d457fa8b1 --- /dev/null +++ b/arch/mips/sni/pcimt_scache.c @@ -0,0 +1,37 @@ +/* + * arch/mips/sni/pcimt_scache.c + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 1997, 1998 by Ralf Baechle + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <asm/bcache.h> +#include <asm/sni.h> + +#define cacheconf (*(volatile unsigned int *)PCIMT_CACHECONF) +#define invspace (*(volatile unsigned int *)PCIMT_INVSPACE) + +void __init sni_pcimt_sc_init(void) +{ + unsigned int scsiz, sc_size; + + scsiz = cacheconf & 7; + if (scsiz == 0) { + printk("Second level cache is deactived.\n"); + return; + } + if (scsiz >= 6) { + printk("Invalid second level cache size configured, " + "deactivating second level cache.\n"); + cacheconf = 0; + return; + } + + sc_size = 128 << scsiz; + printk("%dkb second level cache detected, deactivating.\n", sc_size); + cacheconf = 0; +} diff --git a/arch/mips/sni/reset.c b/arch/mips/sni/reset.c new file mode 100644 index 000000000000..be85bec002e1 --- /dev/null +++ b/arch/mips/sni/reset.c @@ -0,0 +1,51 @@ +/* + * linux/arch/mips/sni/process.c + * + * Reset a SNI machine. + */ +#include <asm/io.h> +#include <asm/reboot.h> +#include <asm/system.h> +#include <asm/sni.h> + +/* + * This routine reboots the machine by asking the keyboard + * controller to pulse the reset-line low. We try that for a while, + * and if it doesn't work, we do some other stupid things. + */ +static inline void +kb_wait(void) +{ + int i; + + for (i=0; i<0x10000; i++) + if ((inb_p(0x64) & 0x02) == 0) + break; +} + +/* XXX This ends up at the ARC firmware prompt ... */ +void sni_machine_restart(char *command) +{ + int i, j; + + /* This does a normal via the keyboard controller like a PC. + We can do that easier ... */ + local_irq_disable(); + for (;;) { + for (i=0; i<100; i++) { + kb_wait(); + for(j = 0; j < 100000 ; j++) + /* nothing */; + outb_p(0xfe,0x64); /* pulse reset low */ + } + } +} + +void sni_machine_halt(void) +{ +} + +void sni_machine_power_off(void) +{ + *(volatile unsigned char *)PCIMT_CSWCSM = 0xfd; +} diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c new file mode 100644 index 000000000000..8f67cee4317b --- /dev/null +++ b/arch/mips/sni/setup.c @@ -0,0 +1,203 @@ +/* + * Setup pointers to hardware-dependent routines. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 97, 98, 2000, 03, 04 Ralf Baechle (ralf@linux-mips.org) + */ +#include <linux/config.h> +#include <linux/eisa.h> +#include <linux/hdreg.h> +#include <linux/ioport.h> +#include <linux/sched.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/mc146818rtc.h> +#include <linux/pci.h> +#include <linux/console.h> +#include <linux/fb.h> +#include <linux/tty.h> + +#include <asm/arc/types.h> +#include <asm/sgialib.h> +#include <asm/bcache.h> +#include <asm/bootinfo.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/mc146818-time.h> +#include <asm/processor.h> +#include <asm/ptrace.h> +#include <asm/reboot.h> +#include <asm/sni.h> +#include <asm/time.h> +#include <asm/traps.h> + +extern void sni_machine_restart(char *command); +extern void sni_machine_halt(void); +extern void sni_machine_power_off(void); + +static void __init sni_rm200_pci_timer_setup(struct irqaction *irq) +{ + /* set the clock to 100 Hz */ + outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */ + outb_p(LATCH & 0xff , 0x40); /* LSB */ + outb(LATCH >> 8 , 0x40); /* MSB */ + setup_irq(0, irq); +} + +/* + * A bit more gossip about the iron we're running on ... + */ +static inline void sni_pcimt_detect(void) +{ + char boardtype[80]; + unsigned char csmsr; + char *p = boardtype; + unsigned int asic; + + csmsr = *(volatile unsigned char *)PCIMT_CSMSR; + + p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300"); + if ((csmsr & 0x80) == 0) + p += sprintf(p, ", board revision %s", + (csmsr & 0x20) ? "D" : "C"); + asic = csmsr & 0x80; + asic = (csmsr & 0x08) ? asic : !asic; + p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1"); + printk("%s.\n", boardtype); +} + +static void __init sni_display_setup(void) +{ +#ifdef CONFIG_VT +#if defined(CONFIG_VGA_CONSOLE) + struct screen_info *si = &screen_info; + DISPLAY_STATUS *di; + + di = ArcGetDisplayStatus(1); + + if (di) { + si->orig_x = di->CursorXPosition; + si->orig_y = di->CursorYPosition; + si->orig_video_cols = di->CursorMaxXPosition; + si->orig_video_lines = di->CursorMaxYPosition; + si->orig_video_isVGA = VIDEO_TYPE_VGAC; + si->orig_video_points = 16; + } +#endif +#endif +} + +static struct resource sni_io_resource = { + "PCIMT IO MEM", 0x00001000UL, 0x03bfffffUL, IORESOURCE_IO, +}; + +static struct resource pcimt_io_resources[] = { + { "dma1", 0x00, 0x1f, IORESOURCE_BUSY }, + { "timer", 0x40, 0x5f, IORESOURCE_BUSY }, + { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY }, + { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY }, + { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, + { "PCI config data", 0xcfc, 0xcff, IORESOURCE_BUSY } +}; + +static struct resource sni_mem_resource = { + "PCIMT PCI MEM", 0x10000000UL, 0xffffffffUL, IORESOURCE_MEM +}; + +/* + * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used + * for other purposes. Be paranoid and allocate all of the before the PCI + * code gets a chance to to map anything else there ... + * + * This leaves the following areas available: + * + * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory + * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory + * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory + * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory + * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory + */ +static struct resource pcimt_mem_resources[] = { + { "Video RAM area", 0x100a0000, 0x100bffff, IORESOURCE_BUSY }, + { "ISA Reserved", 0x100c0000, 0x100fffff, IORESOURCE_BUSY }, + { "PCI IO", 0x14000000, 0x17bfffff, IORESOURCE_BUSY }, + { "Cache Replacement Area", 0x17c00000, 0x17ffffff, IORESOURCE_BUSY}, + { "PCI INT Acknowledge", 0x1a000000, 0x1a000003, IORESOURCE_BUSY }, + { "Boot PROM", 0x1fc00000, 0x1fc7ffff, IORESOURCE_BUSY}, + { "Diag PROM", 0x1fc80000, 0x1fcfffff, IORESOURCE_BUSY}, + { "X-Bus", 0x1fd00000, 0x1fdfffff, IORESOURCE_BUSY}, + { "BIOS map", 0x1fe00000, 0x1fefffff, IORESOURCE_BUSY}, + { "NVRAM / EEPROM", 0x1ff00000, 0x1ff7ffff, IORESOURCE_BUSY}, + { "ASIC PCI", 0x1fff0000, 0x1fffefff, IORESOURCE_BUSY}, + { "MP Agent", 0x1ffff000, 0x1fffffff, IORESOURCE_BUSY}, + { "Main Memory", 0x20000000, 0x9fffffff, IORESOURCE_BUSY} +}; + +static void __init sni_resource_init(void) +{ + int i; + + /* request I/O space for devices used on all i[345]86 PCs */ + for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++) + request_resource(&ioport_resource, pcimt_io_resources + i); + + /* request mem space for pcimt-specific devices */ + for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++) + request_resource(&sni_mem_resource, pcimt_mem_resources + i); + + ioport_resource.end = sni_io_resource.end; +} + +extern struct pci_ops sni_pci_ops; + +static struct pci_controller sni_controller = { + .pci_ops = &sni_pci_ops, + .mem_resource = &sni_mem_resource, + .mem_offset = 0x10000000UL, + .io_resource = &sni_io_resource, + .io_offset = 0x00000000UL +}; + +static inline void sni_pcimt_time_init(void) +{ + rtc_get_time = mc146818_get_cmos_time; + rtc_set_time = mc146818_set_rtc_mmss; +} + +static int __init sni_rm200_pci_setup(void) +{ + sni_pcimt_detect(); + sni_pcimt_sc_init(); + sni_pcimt_time_init(); + + set_io_port_base(SNI_PORT_BASE); + ioport_resource.end = sni_io_resource.end; + + /* + * Setup (E)ISA I/O memory access stuff + */ + isa_slot_offset = 0xb0000000; +#ifdef CONFIG_EISA + EISA_bus = 1; +#endif + + sni_resource_init(); + board_timer_setup = sni_rm200_pci_timer_setup; + + _machine_restart = sni_machine_restart; + _machine_halt = sni_machine_halt; + _machine_power_off = sni_machine_power_off; + + sni_display_setup(); + +#ifdef CONFIG_PCI + register_pci_controller(&sni_controller); +#endif + + return 0; +} + +early_initcall(sni_rm200_pci_setup); |