diff options
Diffstat (limited to 'arch/mips')
49 files changed, 561 insertions, 451 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2f2ce0c28bc0..b22c043b6ef8 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -22,6 +22,7 @@ config MACH_ALCHEMY config BASLER_EXCITE bool "Basler eXcite smart camera" select CEVT_R4K + select CSRC_R4K select DMA_COHERENT select HW_HAS_PCI select IRQ_CPU @@ -49,6 +50,7 @@ config BASLER_EXCITE_PROTOTYPE config BCM47XX bool "BCM47XX based boards" select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU @@ -57,6 +59,8 @@ config BCM47XX select SYS_SUPPORTS_LITTLE_ENDIAN select SSB select SSB_DRIVER_MIPS + select SSB_DRIVER_EXTIF + select SSB_PCICORE_HOSTMODE if PCI select GENERIC_GPIO select SYS_HAS_EARLY_PRINTK select CFE @@ -66,6 +70,7 @@ config BCM47XX config MIPS_COBALT bool "Cobalt Server" select CEVT_R4K + select CSRC_R4K select CEVT_GT641XX select DMA_NONCOHERENT select HW_HAS_PCI @@ -85,6 +90,7 @@ config MACH_DECSTATION bool "DECstations" select BOOT_ELF32 select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select NO_IOPORT select IRQ_CPU @@ -117,6 +123,7 @@ config MACH_JAZZ select ARC32 select ARCH_MAY_HAVE_PC_FDC select CEVT_R4K + select CSRC_R4K select GENERIC_ISA_DMA select IRQ_CPU select I8253 @@ -137,6 +144,7 @@ config MACH_JAZZ config LASAT bool "LASAT Networks platforms" select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select SYS_HAS_EARLY_PRINTK select HW_HAS_PCI @@ -154,6 +162,7 @@ config LEMOTE_FULONG bool "Lemote Fulong mini-PC" select ARCH_SPARSEMEM_ENABLE select CEVT_R4K + select CSRC_R4K select SYS_HAS_CPU_LOONGSON2 select DMA_NONCOHERENT select BOOT_ELF32 @@ -179,6 +188,7 @@ config MIPS_ATLAS bool "MIPS Atlas board" select BOOT_ELF32 select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select SYS_HAS_EARLY_PRINTK select IRQ_CPU @@ -210,6 +220,7 @@ config MIPS_MALTA select ARCH_MAY_HAVE_PC_FDC select BOOT_ELF32 select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select GENERIC_ISA_DMA select IRQ_CPU @@ -241,6 +252,7 @@ config MIPS_MALTA config MIPS_SEAD bool "MIPS SEAD board" select CEVT_R4K + select CSRC_R4K select IRQ_CPU select DMA_NONCOHERENT select SYS_HAS_EARLY_PRINTK @@ -260,6 +272,7 @@ config MIPS_SEAD config MIPS_SIM bool 'MIPS simulator (MIPSsim)' select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select SYS_HAS_EARLY_PRINTK select IRQ_CPU @@ -278,6 +291,7 @@ config MIPS_SIM config MARKEINS bool "NEC EMMA2RH Mark-eins" select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU @@ -293,6 +307,7 @@ config MARKEINS config MACH_VR41XX bool "NEC VR4100 series based machines" select CEVT_R4K + select CSRC_R4K select SYS_HAS_CPU_VR41XX select GENERIC_HARDIRQS_NO__DO_IRQ @@ -330,6 +345,7 @@ config PMC_MSP config PMC_YOSEMITE bool "PMC-Sierra Yosemite eval board" select CEVT_R4K + select CSRC_R4K select DMA_COHERENT select HW_HAS_PCI select IRQ_CPU @@ -351,6 +367,7 @@ config PMC_YOSEMITE config QEMU bool "Qemu" select CEVT_R4K + select CSRC_R4K select DMA_COHERENT select GENERIC_ISA_DMA select HAVE_STD_PC_SERIAL_PORT @@ -382,9 +399,11 @@ config SGI_IP22 select ARC32 select BOOT_ELF32 select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select HW_HAS_EISA select I8253 + select I8259 select IP22_CPU_SCACHE select IRQ_CPU select GENERIC_ISA_DMA_SUPPORT_BROKEN @@ -427,6 +446,7 @@ config SGI_IP32 select ARC32 select BOOT_ELF32 select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU @@ -498,6 +518,7 @@ config SIBYTE_SWARM select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_KGDB select SYS_SUPPORTS_LITTLE_ENDIAN + select ZONE_DMA32 if 64BIT config SIBYTE_LITTLESUR bool "Sibyte BCM91250C2-LittleSur" @@ -548,6 +569,7 @@ config SIBYTE_BIGSUR select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN + select ZONE_DMA32 if 64BIT config SNI_RM bool "SNI RM200/300/400" @@ -556,6 +578,7 @@ config SNI_RM select ARCH_MAY_HAVE_PC_FDC select BOOT_ELF32 select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select GENERIC_ISA_DMA select HW_HAS_EISA @@ -599,6 +622,7 @@ config TOSHIBA_JMR3927 config TOSHIBA_RBTX4927 bool "Toshiba RBTX49[23]7 board" select CEVT_R4K + select CSRC_R4K select CEVT_TXX9 select DMA_NONCOHERENT select HAS_TXX9_SERIAL @@ -621,6 +645,7 @@ config TOSHIBA_RBTX4927 config TOSHIBA_RBTX4938 bool "Toshiba RBTX4938 board" select CEVT_R4K + select CSRC_R4K select CEVT_TXX9 select DMA_NONCOHERENT select HAS_TXX9_SERIAL @@ -642,6 +667,7 @@ config TOSHIBA_RBTX4938 config WR_PPMC bool "Wind River PPMC board" select CEVT_R4K + select CSRC_R4K select IRQ_CPU select BOOT_ELF32 select DMA_NONCOHERENT @@ -690,6 +716,10 @@ config ARCH_HAS_ILOG2_U64 bool default n +config ARCH_SUPPORTS_OPROFILE + bool + default y if !MIPS_MT_SMTC + config GENERIC_FIND_NEXT_BIT bool default y @@ -752,6 +782,9 @@ config CEVT_TXX9 config CSRC_BCM1480 bool +config CSRC_R4K + bool + config CSRC_SB1250 bool @@ -961,8 +994,6 @@ config BOOT_ELF64 menu "CPU selection" -source "kernel/time/Kconfig" - choice prompt "CPU type" default CPU_R4X00 @@ -1640,6 +1671,9 @@ config ARCH_DISCONTIGMEM_ENABLE or have huge holes in the physical address space for other reasons. See <file:Documentation/vm/numa> for more. +config ARCH_POPULATES_NODE_MAP + def_bool y + config ARCH_SPARSEMEM_ENABLE bool select SPARSEMEM_STATIC @@ -1734,6 +1768,8 @@ config NR_CPUS performance should round up your number of processors to the next power of two. +source "kernel/time/Kconfig" + # # Timer Interrupt Frequency Configuration # @@ -1945,6 +1981,9 @@ config I8253 config PCSPEAKER bool +config ZONE_DMA32 + bool + source "drivers/pcmcia/Kconfig" source "drivers/pci/hotplug/Kconfig" diff --git a/arch/mips/au1000/Kconfig b/arch/mips/au1000/Kconfig index b36cec58a9a8..1fe97cccead1 100644 --- a/arch/mips/au1000/Kconfig +++ b/arch/mips/au1000/Kconfig @@ -7,7 +7,6 @@ config MIPS_MTX1 bool "4G Systems MTX-1 board" select DMA_NONCOHERENT select HW_HAS_PCI - select RESOURCES_64BIT if PCI select SOC_AU1500 select SYS_SUPPORTS_LITTLE_ENDIAN @@ -22,7 +21,6 @@ config MIPS_DB1000 select SOC_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI - select RESOURCES_64BIT if PCI select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_DB1100 @@ -44,7 +42,6 @@ config MIPS_DB1500 select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_DISABLE_OBSOLETE_IDE - select RESOURCES_64BIT if PCI select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN @@ -54,7 +51,6 @@ config MIPS_DB1550 select HW_HAS_PCI select DMA_NONCOHERENT select MIPS_DISABLE_OBSOLETE_IDE - select RESOURCES_64BIT if PCI select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_MIRAGE @@ -68,7 +64,6 @@ config MIPS_PB1000 select SOC_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI - select RESOURCES_64BIT if PCI select SWAP_IO_SPACE select SYS_SUPPORTS_LITTLE_ENDIAN @@ -77,7 +72,6 @@ config MIPS_PB1100 select SOC_AU1100 select DMA_NONCOHERENT select HW_HAS_PCI - select RESOURCES_64BIT if PCI select SWAP_IO_SPACE select SYS_SUPPORTS_LITTLE_ENDIAN @@ -86,7 +80,6 @@ config MIPS_PB1200 select SOC_AU1200 select DMA_NONCOHERENT select MIPS_DISABLE_OBSOLETE_IDE - select RESOURCES_64BIT if PCI select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_PB1500 @@ -94,7 +87,6 @@ config MIPS_PB1500 select SOC_AU1500 select DMA_NONCOHERENT select HW_HAS_PCI - select RESOURCES_64BIT if PCI select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_PB1550 @@ -103,7 +95,6 @@ config MIPS_PB1550 select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_DISABLE_OBSOLETE_IDE - select RESOURCES_64BIT if PCI select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_XXS1500 @@ -138,6 +129,7 @@ config SOC_AU1X00 bool select 64BIT_PHYS_ADDR select CEVT_R4K + select CSRC_R4K select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c index 9d6ad43fded6..edf91f41a786 100644 --- a/arch/mips/au1000/common/dbdma.c +++ b/arch/mips/au1000/common/dbdma.c @@ -859,7 +859,7 @@ dbdma_interrupt(int irq, void *dev_id) intstat = dbdma_gptr->ddma_intstat; au_sync(); - chan_index = ffs(intstat); + chan_index = __ffs(intstat); ctp = chan_tab_ptr[chan_index]; cp = ctp->chan_ptr; diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index ddfb7f0a17a6..3c7714f057ac 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c @@ -462,9 +462,9 @@ static void intc0_req0_irqdispatch(void) return; } #endif - bit = ffs(intc0_req0); + bit = __ffs(intc0_req0); intc0_req0 &= ~(1 << bit); - do_IRQ(MIPS_CPU_IRQ_BASE + bit); + do_IRQ(AU1000_INTC0_INT_BASE + bit); } @@ -478,9 +478,9 @@ static void intc0_req1_irqdispatch(void) if (!intc0_req1) return; - bit = ffs(intc0_req1); + bit = __ffs(intc0_req1); intc0_req1 &= ~(1 << bit); - do_IRQ(bit); + do_IRQ(AU1000_INTC0_INT_BASE + bit); } @@ -498,9 +498,9 @@ static void intc1_req0_irqdispatch(void) if (!intc1_req0) return; - bit = ffs(intc1_req0); + bit = __ffs(intc1_req0); intc1_req0 &= ~(1 << bit); - do_IRQ(MIPS_CPU_IRQ_BASE + 32 + bit); + do_IRQ(AU1000_INTC1_INT_BASE + bit); } @@ -514,9 +514,9 @@ static void intc1_req1_irqdispatch(void) if (!intc1_req1) return; - bit = ffs(intc1_req1); + bit = __ffs(intc1_req1); intc1_req1 &= ~(1 << bit); - do_IRQ(MIPS_CPU_IRQ_BASE + 32 + bit); + do_IRQ(AU1000_INTC1_INT_BASE + bit); } asmlinkage void plat_irq_dispatch(void) diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c index 9be99a68932a..ce771487567d 100644 --- a/arch/mips/au1000/common/pci.c +++ b/arch/mips/au1000/common/pci.c @@ -1,8 +1,8 @@ /* * BRIEF MODULE DESCRIPTION - * Alchemy/AMD Au1x00 pci support. + * Alchemy/AMD Au1x00 PCI support. * - * Copyright 2001,2002,2003 MontaVista Software Inc. + * Copyright 2001-2003, 2007 MontaVista Software Inc. * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * @@ -39,15 +39,15 @@ /* TBD */ static struct resource pci_io_resource = { - .start = (resource_size_t)PCI_IO_START, - .end = (resource_size_t)PCI_IO_END, + .start = PCI_IO_START, + .end = PCI_IO_END, .name = "PCI IO space", .flags = IORESOURCE_IO }; static struct resource pci_mem_resource = { - .start = (resource_size_t)PCI_MEM_START, - .end = (resource_size_t)PCI_MEM_END, + .start = PCI_MEM_START, + .end = PCI_MEM_END, .name = "PCI memory space", .flags = IORESOURCE_MEM }; @@ -66,6 +66,8 @@ static unsigned long virt_io_addr; static int __init au1x_pci_setup(void) { + extern void au1x_pci_cfg_init(void); + #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); @@ -94,6 +96,8 @@ static int __init au1x_pci_setup(void) set_io_port_base(virt_io_addr); #endif + au1x_pci_cfg_init(); + register_pci_controller(&au1x_controller); return 0; } diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index a90d425d4651..d885e3848ec6 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -137,12 +137,11 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) #ifdef CONFIG_PCI { - u32 start, end; + u32 start = (u32)Au1500_PCI_MEM_START; + u32 end = (u32)Au1500_PCI_MEM_END; - start = (u32)Au1500_PCI_MEM_START; - end = (u32)Au1500_PCI_MEM_END; - /* check for pci memory window */ - if ((phys_addr >= start) && ((phys_addr + size) < end)) + /* Check for PCI memory window */ + if (phys_addr >= start && (phys_addr + size - 1) <= end) return (phys_t) ((phys_addr - start) + Au1500_PCI_MEM_START); } diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c index c096be4ed4e7..8fcd0df86f93 100644 --- a/arch/mips/au1000/pb1200/irqmap.c +++ b/arch/mips/au1000/pb1200/irqmap.c @@ -74,7 +74,7 @@ irqreturn_t pb1200_cascade_handler( int irq, void *dev_id) bcsr->int_status = bisr; for( ; bisr; bisr &= (bisr-1) ) { - extirq_nr = PB1200_INT_BEGIN + ffs(bisr); + extirq_nr = PB1200_INT_BEGIN + __ffs(bisr); /* Ack and dispatch IRQ */ do_IRQ(extirq_nr); } diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c index db330e811025..d1ba701c9dd1 100644 --- a/arch/mips/cobalt/console.c +++ b/arch/mips/cobalt/console.c @@ -4,10 +4,15 @@ #include <linux/io.h> #include <linux/serial_reg.h> +#include <cobalt.h> + #define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000)) void prom_putchar(char c) { + if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) + return; + while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE)) ; diff --git a/arch/mips/cobalt/time.c b/arch/mips/cobalt/time.c index fa819fccd5db..4a570e7145fe 100644 --- a/arch/mips/cobalt/time.c +++ b/arch/mips/cobalt/time.c @@ -27,9 +27,28 @@ void __init plat_time_init(void) { + u32 start, end; + int i = HZ / 10; + setup_pit_timer(); gt641xx_set_base_clock(GT641XX_BASE_CLOCK); - mips_timer_state = gt641xx_timer0_state; + /* + * MIPS counter frequency is measured during a 100msec interval + * using GT64111 timer0. + */ + while (!gt641xx_timer0_state()) + ; + + start = read_c0_count(); + + while (i--) + while (!gt641xx_timer0_state()) + ; + + end = read_c0_count(); + + mips_hpt_frequency = (end - start) * 10; + printk(KERN_INFO "MIPS counter frequency %dHz\n", mips_hpt_frequency); } diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index 80b0c99c2cfb..3c70c9d16d01 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -76,9 +76,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_CEVT_BCM1480=y +CONFIG_CSRC_BCM1480=y CONFIG_DMA_COHERENT=y CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set @@ -91,6 +95,11 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_CPU_LOONGSON2 is not set # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index fbd2d802fdfd..4b7e43c9f69a 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -49,10 +49,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_CEVT_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y @@ -76,6 +79,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_CPU_LOONGSON2 is not set # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y @@ -253,6 +260,7 @@ CONFIG_HW_HAS_PCI=y CONFIG_PCI=y # CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_MMU=y +CONFIG_I8253=y # # PCCARD (PCMCIA/CardBus) support diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index b551535b7e48..ffa08362de17 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o +obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ @@ -43,6 +44,7 @@ obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SMP_UP) += smp-up.o obj-$(CONFIG_MIPS_MT) += mips-mt.o obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index bab935a3d74b..24a2d907aa0d 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -219,7 +219,7 @@ static int c0_compare_int_usable(void) return 1; } -void __cpuinit mips_clockevent_init(void) +int __cpuinit mips_clockevent_init(void) { uint64_t mips_freq = mips_hpt_frequency; unsigned int cpu = smp_processor_id(); @@ -227,7 +227,7 @@ void __cpuinit mips_clockevent_init(void) unsigned int irq; if (!cpu_has_counter || !mips_hpt_frequency) - return; + return -ENXIO; #ifdef CONFIG_MIPS_MT_SMTC setup_smtc_dummy_clockevent_device(); @@ -237,11 +237,11 @@ void __cpuinit mips_clockevent_init(void) * device. */ if (cpu) - return; + return 0; #endif if (!c0_compare_int_usable()) - return; + return -ENXIO; /* * With vectored interrupts things are getting platform specific. @@ -276,8 +276,8 @@ void __cpuinit mips_clockevent_init(void) clockevents_register_device(cd); - if (!cp0_timer_irq_installed) - return; + if (cp0_timer_irq_installed) + return 0; cp0_timer_irq_installed = 1; @@ -287,4 +287,6 @@ void __cpuinit mips_clockevent_init(void) #else setup_irq(irq, &c0_compare_irqaction); #endif + + return 0; } diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c new file mode 100644 index 000000000000..0e2b5cd81f67 --- /dev/null +++ b/arch/mips/kernel/csrc-r4k.c @@ -0,0 +1,33 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 by Ralf Baechle + */ +#include <linux/clocksource.h> +#include <linux/init.h> + +#include <asm/time.h> + +static cycle_t c0_hpt_read(void) +{ + return read_c0_count(); +} + +static struct clocksource clocksource_mips = { + .name = "MIPS", + .read = c0_hpt_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +void __init init_mips_clocksource(void) +{ + /* Calclate a somewhat reasonable rating value */ + clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; + + clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); + + clocksource_register(&clocksource_mips); +} diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index 236768731063..50be56c9e9ef 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -136,7 +136,8 @@ EXPORT(_stext) * kernel load address. This is needed because this platform does * not have a ELF loader yet. */ - __INIT +FEXPORT(__kernel_entry) + j kernel_entry #endif __INIT_REFOK diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 471013577108..197d7977de35 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -238,7 +238,7 @@ static int i8259A_shutdown(struct sys_device *dev) } static struct sysdev_class i8259_sysdev_class = { - set_kset_name("i8259"), + .name = "i8259", .resume = i8259A_resume, .shutdown = i8259A_shutdown, }; diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 11cb264f59ce..2c09a442e5e5 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -77,9 +77,8 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) unsigned long status; /* New thread loses kernel privileges. */ - status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK); + status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK); #ifdef CONFIG_64BIT - status &= ~ST0_FR; status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR; #endif status |= KU_USER; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index a06a27d6cfcd..f8a535afce39 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -342,6 +342,34 @@ static void __init bootmem_init(void) */ bootmap_size = init_bootmem_node(NODE_DATA(0), mapstart, min_low_pfn, max_low_pfn); + + + for (i = 0; i < boot_mem_map.nr_map; i++) { + unsigned long start, end; + + start = PFN_UP(boot_mem_map.map[i].addr); + end = PFN_DOWN(boot_mem_map.map[i].addr + + boot_mem_map.map[i].size); + + if (start <= min_low_pfn) + start = min_low_pfn; + if (start >= end) + continue; + +#ifndef CONFIG_HIGHMEM + if (end > max_low_pfn) + end = max_low_pfn; + + /* + * ... finally, is the area going away? + */ + if (end <= start) + continue; +#endif + + add_active_range(0, start, end); + } + /* * Register fully available low RAM pages with the bootmem allocator. */ diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c new file mode 100644 index 000000000000..ead6c30eeb14 --- /dev/null +++ b/arch/mips/kernel/smp-up.c @@ -0,0 +1,67 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006, 07 by Ralf Baechle (ralf@linux-mips.org) + * + * Symmetric Uniprocessor (TM) Support + */ +#include <linux/kernel.h> +#include <linux/sched.h> + +/* + * Send inter-processor interrupt + */ +void up_send_ipi_single(int cpu, unsigned int action) +{ + panic(KERN_ERR "%s called", __func__); +} + +static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + panic(KERN_ERR "%s called", __func__); +} + +/* + * After we've done initial boot, this function is called to allow the + * board code to clean up state, if needed + */ +void __cpuinit up_init_secondary(void) +{ +} + +void __cpuinit up_smp_finish(void) +{ +} + +/* Hook for after all CPUs are online */ +void up_cpus_done(void) +{ +} + +/* + * Firmware CPU startup hook + */ +void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle) +{ +} + +void __init up_smp_setup(void) +{ +} + +void __init up_prepare_cpus(unsigned int max_cpus) +{ +} + +struct plat_smp_ops up_smp_ops = { + .send_ipi_single = up_send_ipi_single, + .send_ipi_mask = up_send_ipi_mask, + .init_secondary = up_init_secondary, + .smp_finish = up_smp_finish, + .cpus_done = up_cpus_done, + .boot_secondary = up_boot_secondary, + .smp_setup = up_smp_setup, + .prepare_cpus = up_prepare_cpus, +}; diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 3284b9b4ecac..2995be1ab3ca 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -50,14 +50,6 @@ int update_persistent_clock(struct timespec now) return rtc_mips_set_mmss(now.tv_sec); } -/* - * High precision timer functions for a R4k-compatible timer. - */ -static cycle_t c0_hpt_read(void) -{ - return read_c0_count(); -} - int (*mips_timer_state)(void); int null_perf_irq(void) @@ -84,55 +76,6 @@ EXPORT_SYMBOL(perf_irq); unsigned int mips_hpt_frequency; -static struct clocksource clocksource_mips = { - .name = "MIPS", - .read = c0_hpt_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static unsigned int __init calibrate_hpt(void) -{ - cycle_t frequency, hpt_start, hpt_end, hpt_count, hz; - - const int loops = HZ / 10; - int log_2_loops = 0; - int i; - - /* - * We want to calibrate for 0.1s, but to avoid a 64-bit - * division we round the number of loops up to the nearest - * power of 2. - */ - while (loops > 1 << log_2_loops) - log_2_loops++; - i = 1 << log_2_loops; - - /* - * Wait for a rising edge of the timer interrupt. - */ - while (mips_timer_state()); - while (!mips_timer_state()); - - /* - * Now see how many high precision timer ticks happen - * during the calculated number of periods between timer - * interrupts. - */ - hpt_start = clocksource_mips.read(); - do { - while (mips_timer_state()); - while (!mips_timer_state()); - } while (--i); - hpt_end = clocksource_mips.read(); - - hpt_count = (hpt_end - hpt_start) & clocksource_mips.mask; - hz = HZ; - frequency = hpt_count * hz; - - return frequency >> log_2_loops; -} - void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock) { u64 temp; @@ -166,20 +109,6 @@ void __cpuinit clockevent_set_clock(struct clock_event_device *cd, cd->mult = (u32) temp; } -static void __init init_mips_clocksource(void) -{ - /* Calclate a somewhat reasonable rating value */ - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; - - clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); - - clocksource_register(&clocksource_mips); -} - -void __init __weak plat_time_init(void) -{ -} - /* * This function exists in order to cause an error due to a duplicate * definition if platform code should have its own implementation. The hook @@ -194,21 +123,42 @@ void __init plat_timer_setup(void) BUG(); } +static __init int cpu_has_mfc0_count_bug(void) +{ + switch (current_cpu_type()) { + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + /* + * V3.0 is documented as suffering from the mfc0 from count bug. + * Afaik this is the last version of the R4000. Later versions + * were marketed as R4400. + */ + return 1; + + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + /* + * The published errata for the R4400 upto 3.0 say the CPU + * has the mfc0 from count bug. + */ + if ((current_cpu_data.processor_id & 0xff) <= 0x30) + return 1; + + /* + * we assume newer revisions are ok + */ + return 0; + } + + return 0; +} + void __init time_init(void) { plat_time_init(); - if (cpu_has_counter && (mips_hpt_frequency || mips_timer_state)) { - /* We know counter frequency. Or we can get it. */ - if (!mips_hpt_frequency) - mips_hpt_frequency = calibrate_hpt(); - - /* Report the high precision timer rate for a reference. */ - printk("Using %u.%03u MHz high precision timer.\n", - ((mips_hpt_frequency + 500) / 1000) / 1000, - ((mips_hpt_frequency + 500) / 1000) % 1000); + if (mips_clockevent_init() || !cpu_has_mfc0_count_bug()) init_mips_clocksource(); - } - - mips_clockevent_init(); } diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 23e73d0650a3..fcae66752972 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1317,12 +1317,12 @@ void __init per_cpu_trap_init(void) #endif if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) status_set |= ST0_XX; + if (cpu_has_dsp) + status_set |= ST0_MX; + change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, status_set); - if (cpu_has_dsp) - set_c0_status(ST0_MX); - #ifdef CONFIG_CPU_MIPSR2 if (cpu_has_mips_r2) { unsigned int enable = 0x0000000f; diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 38bd33fa2a23..c06eb812a95e 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -470,7 +470,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location, */ if (v != l->value) { printk(KERN_DEBUG "VPE loader: " - "apply_r_mips_lo16/hi16: " + "apply_r_mips_lo16/hi16: \t" "inconsistent value information\n"); return -ENOEXEC; } @@ -629,7 +629,7 @@ static void simplify_symbols(Elf_Shdr * sechdrs, break; case SHN_MIPS_SCOMMON: - printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON" + printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON " "symbol <%s> st_shndx %d\n", strtab + sym[i].st_name, sym[i].st_shndx); // .sbss section diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile index 5332449ec040..460626b6d62f 100644 --- a/arch/mips/lasat/image/Makefile +++ b/arch/mips/lasat/image/Makefile @@ -12,11 +12,11 @@ endif MKLASATIMG = mklasatimg MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200 -KERNEL_IMAGE = $(TOPDIR)/vmlinux +KERNEL_IMAGE = vmlinux KERNEL_START = $(shell $(NM) $(KERNEL_IMAGE) | grep " _text" | cut -f1 -d\ ) KERNEL_ENTRY = $(shell $(NM) $(KERNEL_IMAGE) | grep kernel_entry | cut -f1 -d\ ) -LDSCRIPT= -L$(obj) -Tromscript.normal +LDSCRIPT= -L$(srctree)/$(src) -Tromscript.normal HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \ -D_kernel_entry=0x$(KERNEL_ENTRY) \ @@ -24,7 +24,7 @@ HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \ -D TIMESTAMP=$(shell date +%s) $(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE) - $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $< + $(CC) -fno-pic $(HEAD_DEFINES) $(LINUXINCLUDE) -c -o $@ $< OBJECTS = head.o kImage.o diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c index 946aee331788..cb1b6822711a 100644 --- a/arch/mips/math-emu/ieee754.c +++ b/arch/mips/math-emu/ieee754.c @@ -108,6 +108,7 @@ int ieee754si_xcpt(int r, const char *op, ...) ax.rv.si = r; va_start(ax.ap, op); ieee754_xcpt(&ax); + va_end(ax.ap); return ax.rv.si; } @@ -122,5 +123,6 @@ s64 ieee754di_xcpt(s64 r, const char *op, ...) ax.rv.di = r; va_start(ax.ap, op); ieee754_xcpt(&ax); + va_end(ax.ap); return ax.rv.di; } diff --git a/arch/mips/math-emu/ieee754dp.c b/arch/mips/math-emu/ieee754dp.c index 3e214aac4b12..6d2d89f32472 100644 --- a/arch/mips/math-emu/ieee754dp.c +++ b/arch/mips/math-emu/ieee754dp.c @@ -57,6 +57,7 @@ ieee754dp ieee754dp_xcpt(ieee754dp r, const char *op, ...) ax.rv.dp = r; va_start(ax.ap, op); ieee754_xcpt(&ax); + va_end(ax.ap); return ax.rv.dp; } @@ -83,6 +84,7 @@ ieee754dp ieee754dp_nanxcpt(ieee754dp r, const char *op, ...) ax.rv.dp = r; va_start(ax.ap, op); ieee754_xcpt(&ax); + va_end(ax.ap); return ax.rv.dp; } diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c index adda851cd04f..463534045ab6 100644 --- a/arch/mips/math-emu/ieee754sp.c +++ b/arch/mips/math-emu/ieee754sp.c @@ -58,6 +58,7 @@ ieee754sp ieee754sp_xcpt(ieee754sp r, const char *op, ...) ax.rv.sp = r; va_start(ax.ap, op); ieee754_xcpt(&ax); + va_end(ax.ap); return ax.rv.sp; } @@ -84,6 +85,7 @@ ieee754sp ieee754sp_nanxcpt(ieee754sp r, const char *op, ...) ax.rv.sp = r; va_start(ax.ap, op); ieee754_xcpt(&ax); + va_end(ax.ap); return ax.rv.sp; } diff --git a/arch/mips/mips-boards/generic/display.c b/arch/mips/mips-boards/generic/display.c index 5d600054090a..2a0057cfc30d 100644 --- a/arch/mips/mips-boards/generic/display.c +++ b/arch/mips/mips-boards/generic/display.c @@ -37,9 +37,9 @@ void mips_display_message(const char *str) for (i = 0; i <= 14; i=i+2) { if (*str) - writel(*str++, display + i); + __raw_writel(*str++, display + i); else - writel(' ', display + i); + __raw_writel(' ', display + i); } } diff --git a/arch/mips/mips-boards/generic/reset.c b/arch/mips/mips-boards/generic/reset.c index 7a1bb51f81ee..583d468d98a9 100644 --- a/arch/mips/mips-boards/generic/reset.c +++ b/arch/mips/mips-boards/generic/reset.c @@ -39,16 +39,18 @@ static void atlas_machine_power_off(void); static void mips_machine_restart(char *command) { - unsigned int __iomem *softres_reg = ioremap(SOFTRES_REG, sizeof(unsigned int)); + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); - writew(GORESET, softres_reg); + __raw_writel(GORESET, softres_reg); } static void mips_machine_halt(void) { - unsigned int __iomem *softres_reg = ioremap(SOFTRES_REG, sizeof(unsigned int)); + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); - writew(GORESET, softres_reg); + __raw_writel(GORESET, softres_reg); } #if defined(CONFIG_MIPS_ATLAS) diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index 9a2636e56243..bc43a5c2224d 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -149,7 +149,7 @@ void __init plat_mem_setup(void) /* Check PCI clock */ { unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); - int jmpr = (readw(jmpr_p) >> 2) & 0x07; + int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; static const int pciclocks[] __initdata = { 33, 20, 25, 30, 12, 16, 37, 10 }; diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c index bfaafa38846f..e39bbe989da3 100644 --- a/arch/mips/mipssim/sim_time.c +++ b/arch/mips/mipssim/sim_time.c @@ -101,9 +101,7 @@ unsigned __init get_c0_compare_int(void) void __init plat_time_init(void) { - unsigned int est_freq, flags; - - local_irq_save(flags); + unsigned int est_freq; /* Set Data mode - binary. */ CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); @@ -114,6 +112,4 @@ void __init plat_time_init(void) (est_freq % 1000000) * 100 / 1000000); cpu_khz = est_freq / 1000; - - local_irq_restore(flags); } diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 33519ce49540..810535dd091b 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -40,16 +40,38 @@ static inline int cpu_is_noncoherent_r10000(struct device *dev) current_cpu_type() == CPU_R12000); } +static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp) +{ + /* ignore region specifiers */ + gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); + +#ifdef CONFIG_ZONE_DMA + if (dev == NULL) + gfp |= __GFP_DMA; + else if (dev->coherent_dma_mask < DMA_BIT_MASK(24)) + gfp |= __GFP_DMA; + else +#endif +#ifdef CONFIG_ZONE_DMA32 + if (dev->coherent_dma_mask < DMA_BIT_MASK(32)) + gfp |= __GFP_DMA32; + else +#endif + ; + + /* Don't invoke OOM killer */ + gfp |= __GFP_NORETRY; + + return gfp; +} + void *dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t * dma_handle, gfp_t gfp) { void *ret; - /* ignore region specifiers */ - gfp &= ~(__GFP_DMA | __GFP_HIGHMEM); + gfp = massage_gfp_flags(dev, gfp); - if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff)) - gfp |= GFP_DMA; ret = (void *) __get_free_pages(gfp, get_order(size)); if (ret != NULL) { @@ -67,11 +89,8 @@ void *dma_alloc_coherent(struct device *dev, size_t size, { void *ret; - /* ignore region specifiers */ - gfp &= ~(__GFP_DMA | __GFP_HIGHMEM); + gfp = massage_gfp_flags(dev, gfp); - if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff)) - gfp |= GFP_DMA; ret = (void *) __get_free_pages(gfp, get_order(size)); if (ret) { @@ -343,7 +362,7 @@ int dma_supported(struct device *dev, u64 mask) * so we can't guarantee allocations that must be * within a tighter range than GFP_DMA.. */ - if (mask < 0x00ffffff) + if (mask < DMA_BIT_MASK(24)) return 0; return 1; diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index ec3b9e9f30f4..480dec04f552 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -347,11 +347,8 @@ static int __init page_is_ram(unsigned long pagenr) void __init paging_init(void) { - unsigned long zones_size[MAX_NR_ZONES] = { 0, }; -#ifndef CONFIG_FLATMEM - unsigned long zholes_size[MAX_NR_ZONES] = { 0, }; - unsigned long i, j, pfn; -#endif + unsigned long max_zone_pfns[MAX_NR_ZONES]; + unsigned long lastpfn; pagetable_init(); @@ -361,35 +358,27 @@ void __init paging_init(void) kmap_coherent_init(); #ifdef CONFIG_ZONE_DMA - if (min_low_pfn < MAX_DMA_PFN && MAX_DMA_PFN <= max_low_pfn) { - zones_size[ZONE_DMA] = MAX_DMA_PFN - min_low_pfn; - zones_size[ZONE_NORMAL] = max_low_pfn - MAX_DMA_PFN; - } else if (max_low_pfn < MAX_DMA_PFN) - zones_size[ZONE_DMA] = max_low_pfn - min_low_pfn; - else + max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN; #endif - zones_size[ZONE_NORMAL] = max_low_pfn - min_low_pfn; - +#ifdef CONFIG_ZONE_DMA32 + max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN; +#endif + max_zone_pfns[ZONE_NORMAL] = max_low_pfn; + lastpfn = max_low_pfn; #ifdef CONFIG_HIGHMEM - zones_size[ZONE_HIGHMEM] = highend_pfn - highstart_pfn; + max_zone_pfns[ZONE_HIGHMEM] = highend_pfn; + lastpfn = highend_pfn; - if (cpu_has_dc_aliases && zones_size[ZONE_HIGHMEM]) { + if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) { printk(KERN_WARNING "This processor doesn't support highmem." - " %ldk highmem ignored\n", zones_size[ZONE_HIGHMEM]); - zones_size[ZONE_HIGHMEM] = 0; + " %ldk highmem ignored\n", + (highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10)); + max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn; + lastpfn = max_low_pfn; } #endif -#ifdef CONFIG_FLATMEM - free_area_init(zones_size); -#else - pfn = min_low_pfn; - for (i = 0; i < MAX_NR_ZONES; i++) - for (j = 0; j < zones_size[i]; j++, pfn++) - if (!page_is_ram(pfn)) - zholes_size[i]++; - free_area_init_node(0, NODE_DATA(0), zones_size, 0, zholes_size); -#endif + free_area_init_nodes(max_zone_pfns); } static struct kcore_list kcore_mem, kcore_vmalloc; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 423bc2c473df..bdfa07aecd97 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -6,6 +6,7 @@ * Copyright (C) 2004, 05, 06 by Ralf Baechle * Copyright (C) 2005 by MIPS Technologies, Inc. */ +#include <linux/cpumask.h> #include <linux/oprofile.h> #include <linux/interrupt.h> #include <linux/smp.h> @@ -33,11 +34,45 @@ #ifdef CONFIG_MIPS_MT_SMP #define WHAT (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id())) #define vpe_id() smp_processor_id() + +/* + * The number of bits to shift to convert between counters per core and + * counters per VPE. There is no reasonable interface atm to obtain the + * number of VPEs used by Linux and in the 34K this number is fixed to two + * anyways so we hardcore a few things here for the moment. The way it's + * done here will ensure that oprofile VSMP kernel will run right on a lesser + * core like a 24K also or with maxcpus=1. + */ +static inline unsigned int vpe_shift(void) +{ + if (num_possible_cpus() > 1) + return 1; + + return 0; +} + #else + #define WHAT 0 #define vpe_id() 0 + +static inline unsigned int vpe_shift(void) +{ + return 0; +} + #endif +static inline unsigned int counters_total_to_per_cpu(unsigned int counters) +{ + return counters >> vpe_shift(); +} + +static inline unsigned int counters_per_cpu_to_total(unsigned int counters) +{ + return counters << vpe_shift(); +} + #define __define_perf_accessors(r, n, np) \ \ static inline unsigned int r_c0_ ## r ## n(void) \ @@ -269,9 +304,7 @@ static int __init mipsxx_init(void) reset_counters(counters); -#ifdef CONFIG_MIPS_MT_SMP - counters >>= 1; -#endif + counters = counters_total_to_per_cpu(counters); op_model_mipsxx_ops.num_counters = counters; switch (current_cpu_type()) { @@ -330,9 +363,8 @@ static int __init mipsxx_init(void) static void mipsxx_exit(void) { int counters = op_model_mipsxx_ops.num_counters; -#ifdef CONFIG_MIPS_MT_SMP - counters <<= 1; -#endif + + counters = counters_per_cpu_to_total(counters); reset_counters(counters); perf_irq = null_perf_irq; diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index f7df1142912b..9553b14002dd 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -177,7 +177,7 @@ static char irq_tab_raq2[] __initdata = { int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - if (cobalt_board_id < COBALT_BRD_ID_QUBE2) + if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) return irq_tab_qube1[slot]; if (cobalt_board_id == COBALT_BRD_ID_RAQ2) diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c index 6b29904acf45..1314bd58f036 100644 --- a/arch/mips/pci/ops-au1000.c +++ b/arch/mips/pci/ops-au1000.c @@ -1,8 +1,8 @@ /* * BRIEF MODULE DESCRIPTION - * Alchemy/AMD Au1x00 pci support. + * Alchemy/AMD Au1x00 PCI support. * - * Copyright 2001,2002,2003 MontaVista Software Inc. + * Copyright 2001-2003, 2007 MontaVista Software Inc. * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * @@ -69,10 +69,27 @@ void mod_wired_entry(int entry, unsigned long entrylo0, write_c0_pagemask(old_pagemask); } -struct vm_struct *pci_cfg_vm; +static struct vm_struct *pci_cfg_vm; static int pci_cfg_wired_entry; -static int first_cfg = 1; -unsigned long last_entryLo0, last_entryLo1; +static unsigned long last_entryLo0, last_entryLo1; + +/* + * We can't ioremap the entire pci config space because it's too large. + * Nor can we call ioremap dynamically because some device drivers use + * the PCI config routines from within interrupt handlers and that + * becomes a problem in get_vm_area(). We use one wired TLB to handle + * all config accesses for all busses. + */ +void __init au1x_pci_cfg_init(void) +{ + /* Reserve a wired entry for PCI config accesses */ + pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); + if (!pci_cfg_vm) + panic(KERN_ERR "PCI unable to get vm area\n"); + pci_cfg_wired_entry = read_c0_wired(); + add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); + last_entryLo0 = last_entryLo1 = 0xffffffff; +} static int config_access(unsigned char access_type, struct pci_bus *bus, unsigned int dev_fn, unsigned char where, @@ -97,27 +114,6 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, Au1500_PCI_STATCMD); au_sync_udelay(1); - /* - * We can't ioremap the entire pci config space because it's - * too large. Nor can we call ioremap dynamically because some - * device drivers use the pci config routines from within - * interrupt handlers and that becomes a problem in get_vm_area(). - * We use one wired tlb to handle all config accesses for all - * busses. To improve performance, if the current device - * is the same as the last device accessed, we don't touch the - * tlb. - */ - if (first_cfg) { - /* reserve a wired entry for pci config accesses */ - first_cfg = 0; - pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); - if (!pci_cfg_vm) - panic(KERN_ERR "PCI unable to get vm area\n"); - pci_cfg_wired_entry = read_c0_wired(); - add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); - last_entryLo0 = last_entryLo1 = 0xffffffff; - } - /* Allow board vendors to implement their own off-chip idsel. * If it doesn't succeed, may as well bail out at this point. */ @@ -144,9 +140,12 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, /* page boundary */ cfg_base = cfg_base & PAGE_MASK; + /* + * To improve performance, if the current device is the same as + * the last device accessed, we don't touch the TLB. + */ entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; - if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) { mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1, (unsigned long)pci_cfg_vm->addr, PM_4K); diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c index fe5451449304..e95881897ec9 100644 --- a/arch/mips/pci/ops-mace.c +++ b/arch/mips/pci/ops-mace.c @@ -42,6 +42,10 @@ static int mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 *val) { + u32 control = mace->pci.control; + + /* disable master aborts interrupts during config read */ + mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT; mace->pci.config_addr = mkaddr(bus, devfn, reg); switch (size) { case 1: @@ -54,6 +58,9 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, *val = mace->pci.config_data.l; break; } + /* ack possible master abort */ + mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT; + mace->pci.control = control; DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val); diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index 5443ea3596f8..47f316c86ab1 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -76,8 +76,10 @@ static inline void WRITECFG32(u32 addr, u32 data) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - This is b0rked. - return dev->irq; + if (pin == 0) + return -1; + + return K_BCM1480_INT_PCI_INTA - 1 + pin; } /* Do platform specific device initialization at pci_enable_device() time */ diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c index 618ea7dbc474..532b561b4442 100644 --- a/arch/mips/pci/pci-ip32.c +++ b/arch/mips/pci/pci-ip32.c @@ -119,6 +119,7 @@ static struct pci_controller mace_pci_controller = { .iommu = 0, .mem_offset = MACE_PCI_MEM_OFFSET, .io_offset = 0, + .io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO), }; static int __init mace_init(void) @@ -135,7 +136,8 @@ static int __init mace_init(void) BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0, "MACE PCI error", NULL)); - iomem_resource = mace_pci_mem_resource; + /* extend memory resources */ + iomem_resource.end = mace_pci_mem_resource.end; ioport_resource = mace_pci_io_resource; register_pci_controller(&mace_pci_controller); diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 589b745d822a..6e6981fd7934 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -242,6 +242,8 @@ static void pcibios_fixup_device_resources(struct pci_dev *dev, for (i = 0; i < PCI_NUM_RESOURCES; i++) { if (!dev->resource[i].start) continue; + if (dev->resource[i].flags & IORESOURCE_PCI_FIXED) + continue; if (dev->resource[i].flags & IORESOURCE_IO) offset = hose->io_offset; else if (dev->resource[i].flags & IORESOURCE_MEM) diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c index e818fd0f1584..6d494e0de3d9 100644 --- a/arch/mips/philips/pnx8550/common/time.c +++ b/arch/mips/philips/pnx8550/common/time.c @@ -22,7 +22,6 @@ #include <linux/kernel_stat.h> #include <linux/spinlock.h> #include <linux/interrupt.h> -#include <linux/module.h> #include <asm/bootinfo.h> #include <asm/cpu.h> @@ -41,11 +40,60 @@ static cycle_t hpt_read(void) return read_c0_count2(); } +static struct clocksource pnx_clocksource = { + .name = "pnx8xxx", + .rating = 200, + .read = hpt_read, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + static void timer_ack(void) { write_c0_compare(cpj); } +static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *c = dev_id; + + /* clear MATCH, signal the event */ + c->event_handler(c); + + return IRQ_HANDLED; +} + +static struct irqaction pnx8xxx_timer_irq = { + .handler = pnx8xxx_timer_interrupt, + .flags = IRQF_DISABLED | IRQF_PERCPU, + .name = "pnx8xxx_timer", +}; + +static irqreturn_t monotonic_interrupt(int irq, void *dev_id) +{ + /* Timer 2 clear interrupt */ + write_c0_compare2(-1); + return IRQ_HANDLED; +} + +static struct irqaction monotonic_irqaction = { + .handler = monotonic_interrupt, + .flags = IRQF_DISABLED, + .name = "Monotonic timer", +}; + +static int pnx8xxx_set_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + write_c0_compare(delta); + return 0; +} + +static struct clock_event_device pnx8xxx_clockevent = { + .name = "pnx8xxx_clockevent", + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = pnx8xxx_set_next_event, +}; + /* * plat_time_init() - it does the following things: * @@ -58,11 +106,34 @@ static void timer_ack(void) __init void plat_time_init(void) { + unsigned int configPR; unsigned int n; unsigned int m; unsigned int p; unsigned int pow2p; + clockevents_register_device(&pnx8xxx_clockevent); + clocksource_register(&pnx_clocksource); + + setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq); + setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); + + /* Timer 1 start */ + configPR = read_c0_config7(); + configPR &= ~0x00000008; + write_c0_config7(configPR); + + /* Timer 2 start */ + configPR = read_c0_config7(); + configPR &= ~0x00000010; + write_c0_config7(configPR); + + /* Timer 3 stop */ + configPR = read_c0_config7(); + configPR |= 0x00000020; + write_c0_config7(configPR); + + /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */ /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */ @@ -87,42 +158,6 @@ __init void plat_time_init(void) write_c0_count2(0); write_c0_compare2(0xffffffff); - clocksource_mips.read = hpt_read; - mips_timer_ack = timer_ack; -} - -static irqreturn_t monotonic_interrupt(int irq, void *dev_id) -{ - /* Timer 2 clear interrupt */ - write_c0_compare2(-1); - return IRQ_HANDLED; } -static struct irqaction monotonic_irqaction = { - .handler = monotonic_interrupt, - .flags = IRQF_DISABLED, - .name = "Monotonic timer", -}; -void __init plat_timer_setup(struct irqaction *irq) -{ - int configPR; - - setup_irq(PNX8550_INT_TIMER1, irq); - setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); - - /* Timer 1 start */ - configPR = read_c0_config7(); - configPR &= ~0x00000008; - write_c0_config7(configPR); - - /* Timer 2 start */ - configPR = read_c0_config7(); - configPR &= ~0x00000010; - write_c0_config7(configPR); - - /* Timer 3 stop */ - configPR = read_c0_config7(); - configPR |= 0x00000020; - write_c0_config7(configPR); -} diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig index 6b293ce0935f..90261b83db04 100644 --- a/arch/mips/pmc-sierra/Kconfig +++ b/arch/mips/pmc-sierra/Kconfig @@ -5,12 +5,14 @@ choice config PMC_MSP4200_EVAL bool "PMC-Sierra MSP4200 Eval Board" select CEVT_R4K + select CSRC_R4K select IRQ_MSP_SLP select HW_HAS_PCI config PMC_MSP4200_GW bool "PMC-Sierra MSP4200 VoIP Gateway" select CEVT_R4K + select CSRC_R4K select IRQ_MSP_SLP select HW_HAS_PCI diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c index 11f984767880..7df36dbe65c7 100644 --- a/arch/mips/qemu/q-irq.c +++ b/arch/mips/qemu/q-irq.c @@ -33,5 +33,5 @@ void __init arch_init_irq(void) mips_cpu_irq_init(); init_i8259_irqs(); - set_c0_status(0x8400); + set_c0_status(0x400); } diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c index 26854fb11e7c..1617241d2737 100644 --- a/arch/mips/sgi-ip22/ip22-eisa.c +++ b/arch/mips/sgi-ip22/ip22-eisa.c @@ -36,6 +36,7 @@ #include <asm/sgi/ioc.h> #include <asm/sgi/mc.h> #include <asm/sgi/ip22.h> +#include <asm/i8259.h> /* I2 has four EISA slots. */ #define IP22_EISA_MAX_SLOTS 4 @@ -93,126 +94,11 @@ static irqreturn_t ip22_eisa_intr(int irq, void *dev_id) return IRQ_NONE; } -static void enable_eisa1_irq(unsigned int irq) -{ - u8 mask; - - mask = inb(EISA_INT1_MASK); - mask &= ~((u8) (1 << irq)); - outb(mask, EISA_INT1_MASK); -} - -static unsigned int startup_eisa1_irq(unsigned int irq) -{ - u8 edge; - - /* Only use edge interrupts for EISA */ - - edge = inb(EISA_INT1_EDGE_LEVEL); - edge &= ~((u8) (1 << irq)); - outb(edge, EISA_INT1_EDGE_LEVEL); - - enable_eisa1_irq(irq); - return 0; -} - -static void disable_eisa1_irq(unsigned int irq) -{ - u8 mask; - - mask = inb(EISA_INT1_MASK); - mask |= ((u8) (1 << irq)); - outb(mask, EISA_INT1_MASK); -} - -static void mask_and_ack_eisa1_irq(unsigned int irq) -{ - disable_eisa1_irq(irq); - - outb(0x20, EISA_INT1_CTRL); -} - -static void end_eisa1_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - enable_eisa1_irq(irq); -} - -static struct irq_chip ip22_eisa1_irq_type = { - .name = "IP22 EISA", - .startup = startup_eisa1_irq, - .ack = mask_and_ack_eisa1_irq, - .mask = disable_eisa1_irq, - .mask_ack = mask_and_ack_eisa1_irq, - .unmask = enable_eisa1_irq, - .end = end_eisa1_irq, -}; - -static void enable_eisa2_irq(unsigned int irq) -{ - u8 mask; - - mask = inb(EISA_INT2_MASK); - mask &= ~((u8) (1 << (irq - 8))); - outb(mask, EISA_INT2_MASK); -} - -static unsigned int startup_eisa2_irq(unsigned int irq) -{ - u8 edge; - - /* Only use edge interrupts for EISA */ - - edge = inb(EISA_INT2_EDGE_LEVEL); - edge &= ~((u8) (1 << (irq - 8))); - outb(edge, EISA_INT2_EDGE_LEVEL); - - enable_eisa2_irq(irq); - return 0; -} - -static void disable_eisa2_irq(unsigned int irq) -{ - u8 mask; - - mask = inb(EISA_INT2_MASK); - mask |= ((u8) (1 << (irq - 8))); - outb(mask, EISA_INT2_MASK); -} - -static void mask_and_ack_eisa2_irq(unsigned int irq) -{ - disable_eisa2_irq(irq); - - outb(0x20, EISA_INT2_CTRL); -} - -static void end_eisa2_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - enable_eisa2_irq(irq); -} - -static struct irq_chip ip22_eisa2_irq_type = { - .name = "IP22 EISA", - .startup = startup_eisa2_irq, - .ack = mask_and_ack_eisa2_irq, - .mask = disable_eisa2_irq, - .mask_ack = mask_and_ack_eisa2_irq, - .unmask = enable_eisa2_irq, - .end = end_eisa2_irq, -}; - static struct irqaction eisa_action = { .handler = ip22_eisa_intr, .name = "EISA", }; -static struct irqaction cascade_action = { - .handler = no_action, - .name = "EISA cascade", -}; - int __init ip22_eisa_init(void) { int i, c; @@ -248,29 +134,13 @@ int __init ip22_eisa_init(void) outb(1, EISA_EXT_NMI_RESET_CTRL); udelay(50); /* Wait long enough for the dust to settle */ outb(0, EISA_EXT_NMI_RESET_CTRL); - outb(0x11, EISA_INT1_CTRL); - outb(0x11, EISA_INT2_CTRL); - outb(0, EISA_INT1_MASK); - outb(8, EISA_INT2_MASK); - outb(4, EISA_INT1_MASK); - outb(2, EISA_INT2_MASK); - outb(1, EISA_INT1_MASK); - outb(1, EISA_INT2_MASK); - outb(0xfb, EISA_INT1_MASK); - outb(0xff, EISA_INT2_MASK); outb(0, EISA_DMA2_WRITE_SINGLE); - for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) { - if (i < (SGINT_EISA + 8)) - set_irq_chip(i, &ip22_eisa1_irq_type); - else - set_irq_chip(i, &ip22_eisa2_irq_type); - } + init_i8259_irqs(); /* Cannot use request_irq because of kmalloc not being ready at such * an early stage. Yes, I've been bitten... */ setup_irq(SGI_EISA_IRQ, &eisa_action); - setup_irq(SGINT_EISA + 2, &cascade_action); EISA_bus = 1; return 0; diff --git a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c index e19d60d5fcc1..0177566475d4 100644 --- a/arch/mips/sgi-ip22/ip22-nvram.c +++ b/arch/mips/sgi-ip22/ip22-nvram.c @@ -32,19 +32,19 @@ for (x=0; x<100000; x++) __asm__ __volatile__(""); }) #define eeprom_cs_on(ptr) ({ \ - *ptr &= ~EEPROM_DATO; \ - *ptr &= ~EEPROM_ECLK; \ - *ptr &= ~EEPROM_EPROT; \ - delay(); \ - *ptr |= EEPROM_CSEL; \ - *ptr |= EEPROM_ECLK; }) + __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \ + __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ + __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \ + delay(); \ + __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \ + __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) #define eeprom_cs_off(ptr) ({ \ - *ptr &= ~EEPROM_ECLK; \ - *ptr &= ~EEPROM_CSEL; \ - *ptr |= EEPROM_EPROT; \ - *ptr |= EEPROM_ECLK; }) + __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ + __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \ + __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \ + __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) #define BITS_IN_COMMAND 11 /* @@ -60,15 +60,17 @@ static inline void eeprom_cmd(unsigned int *ctrl, unsigned cmd, unsigned reg) ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND)); for (i = 0; i < BITS_IN_COMMAND; i++) { if (ser_cmd & (1<<15)) /* if high order bit set */ - writel(readl(ctrl) | EEPROM_DATO, ctrl); + __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); else - writel(readl(ctrl) & ~EEPROM_DATO, ctrl); - writel(readl(ctrl) & ~EEPROM_ECLK, ctrl); - writel(readl(ctrl) | EEPROM_ECLK, ctrl); + __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); + __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); + delay(); + __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); + delay(); ser_cmd <<= 1; } /* see data sheet timing diagram */ - writel(readl(ctrl) & ~EEPROM_DATO, ctrl); + __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); } unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg) @@ -76,18 +78,18 @@ unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg) unsigned short res = 0; int i; - writel(readl(ctrl) & ~EEPROM_EPROT, ctrl); + __raw_writel(__raw_readl(ctrl) & ~EEPROM_EPROT, ctrl); eeprom_cs_on(ctrl); eeprom_cmd(ctrl, EEPROM_READ, reg); /* clock the data ouf of serial mem */ for (i = 0; i < 16; i++) { - writel(readl(ctrl) & ~EEPROM_ECLK, ctrl); + __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); delay(); - writel(readl(ctrl) | EEPROM_ECLK, ctrl); + __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); delay(); res <<= 1; - if (readl(ctrl) & EEPROM_DATI) + if (__raw_readl(ctrl) & EEPROM_DATI) res |= 1; } diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index 174f09e42f6b..5f389ee26fca 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -31,25 +31,6 @@ unsigned long sgi_gfxaddr; EXPORT_SYMBOL_GPL(sgi_gfxaddr); -/* - * Stop-A is originally a Sun thing that isn't standard on IP22 so to avoid - * accidents it's disabled by default on IP22. - * - * FIXME: provide a mechanism to change the value of stop_a_enabled. - */ -int stop_a_enabled; - -void ip22_do_break(void) -{ - if (!stop_a_enabled) - return; - - printk("\n"); - ArcEnterInteractiveMode(); -} - -EXPORT_SYMBOL(ip22_do_break); - extern void ip22_be_init(void) __init; void __init plat_mem_setup(void) diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index aab17ddd2f30..b0ea0e43ba48 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -209,18 +209,18 @@ static unsigned long macepci_mask; static void enable_macepci_irq(unsigned int irq) { - macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); + macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); mace->pci.control = macepci_mask; - crime_mask |= 1 << (irq - 1); + crime_mask |= 1 << (irq - CRIME_IRQ_BASE); crime->imask = crime_mask; } static void disable_macepci_irq(unsigned int irq) { - crime_mask &= ~(1 << (irq - 1)); + crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE)); crime->imask = crime_mask; flush_crime_bus(); - macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9); + macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); mace->pci.control = macepci_mask; flush_mace_bus(); } @@ -299,7 +299,7 @@ static void enable_maceisa_irq(unsigned int irq) pr_debug("crime_int %08x enabled\n", crime_int); crime_mask |= crime_int; crime->imask = crime_mask; - maceisa_mask |= 1 << (irq - 33); + maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ); mace->perif.ctrl.imask = maceisa_mask; } @@ -307,7 +307,7 @@ static void disable_maceisa_irq(unsigned int irq) { unsigned int crime_int = 0; - maceisa_mask &= ~(1 << (irq - 33)); + maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); if (!(maceisa_mask & MACEISA_AUDIO_INT)) crime_int |= MACE_AUDIO_INT; if (!(maceisa_mask & MACEISA_MISC_INT)) @@ -331,7 +331,7 @@ static void mask_and_ack_maceisa_irq(unsigned int irq) case MACEISA_SERIAL2_TDMAPR_IRQ: /* edge triggered */ mace_int = mace->perif.ctrl.istat; - mace_int &= ~(1 << (irq - 33)); + mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); mace->perif.ctrl.istat = mace_int; break; } @@ -359,13 +359,17 @@ static struct irq_chip ip32_maceisa_interrupt = { static void enable_mace_irq(unsigned int irq) { - crime_mask |= 1 << (irq - 1); + unsigned int bit = irq - CRIME_IRQ_BASE; + + crime_mask |= (1 << bit); crime->imask = crime_mask; } static void disable_mace_irq(unsigned int irq) { - crime_mask &= ~(1 << (irq - 1)); + unsigned int bit = irq - CRIME_IRQ_BASE; + + crime_mask &= ~(1 << bit); crime->imask = crime_mask; flush_crime_bus(); } @@ -422,7 +426,6 @@ static void ip32_irq0(void) crime_int = crime->istat & crime_mask; irq = MACE_VID_IN1_IRQ + __ffs(crime_int); - crime_int = 1 << irq; if (crime_int & CRIME_MACEISA_INT_MASK) { unsigned long mace_int = mace->perif.ctrl.istat; @@ -489,7 +492,7 @@ void __init arch_init_irq(void) mace->perif.ctrl.imask = 0; mips_cpu_irq_init(); - for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) { + for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { switch (irq) { case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: set_irq_chip(irq, &ip32_mace_interrupt); diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c index 77febd68fcd4..89a71f49b692 100644 --- a/arch/mips/sgi-ip32/ip32-platform.c +++ b/arch/mips/sgi-ip32/ip32-platform.c @@ -13,21 +13,22 @@ #include <asm/ip32/mace.h> #include <asm/ip32/ip32_ints.h> -/* - * .iobase isn't a constant (in the sense of C) so we fill it in at runtime. - */ -#define MACE_PORT(int) \ +#define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1) +#define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2) + +#define MACE_PORT(offset,_irq) \ { \ - .irq = int, \ + .mapbase = MACE_BASE + offset, \ + .irq = _irq, \ .uartclk = 1843200, \ .iotype = UPIO_MEM, \ - .flags = UPF_SKIP_TEST, \ + .flags = UPF_SKIP_TEST|UPF_IOREMAP, \ .regshift = 8, \ } static struct plat_serial8250_port uart8250_data[] = { - MACE_PORT(MACEISA_SERIAL1_IRQ), - MACE_PORT(MACEISA_SERIAL2_IRQ), + MACE_PORT(MACEISA_SERIAL1_OFFS, MACEISA_SERIAL1_IRQ), + MACE_PORT(MACEISA_SERIAL2_OFFS, MACEISA_SERIAL2_IRQ), { }, }; @@ -41,9 +42,6 @@ static struct platform_device uart8250_device = { static int __init uart8250_init(void) { - uart8250_data[0].membase = (void __iomem *) &mace->isa.serial1; - uart8250_data[1].membase = (void __iomem *) &mace->isa.serial2; - return platform_device_register(&uart8250_device); } diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c index 4a8152375efe..632e5d201353 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c @@ -598,8 +598,8 @@ static int __init rbtx4938_ethaddr_init(void) printk(KERN_WARNING "seeprom: bad checksum.\n"); } for (i = 0; i < 2; i++) { - unsigned int slot = TX4938_PCIC_IDSEL_AD_TO_SLOT(31 - i); - unsigned int id = (1 << 8) | PCI_DEVFN(slot, 0); /* bus 1 */ + unsigned int id = + TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); struct platform_device *pdev; if (!(tx4938_ccfgptr->pcfg & (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig index eeb089f20c0d..559acc09c819 100644 --- a/arch/mips/vr41xx/Kconfig +++ b/arch/mips/vr41xx/Kconfig @@ -6,6 +6,7 @@ choice config CASIO_E55 bool "CASIO CASSIOPEIA E-10/15/55/65" select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select IRQ_CPU select ISA @@ -15,6 +16,7 @@ config CASIO_E55 config IBM_WORKPAD bool "IBM WorkPad z50" select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select IRQ_CPU select ISA @@ -24,6 +26,7 @@ config IBM_WORKPAD config NEC_CMBVR4133 bool "NEC CMB-VR4133" select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select IRQ_CPU select HW_HAS_PCI @@ -33,6 +36,7 @@ config NEC_CMBVR4133 config TANBAC_TB022X bool "TANBAC VR4131 multichip module and TANBAC VR4131DIMM" select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select IRQ_CPU select HW_HAS_PCI @@ -48,6 +52,7 @@ config TANBAC_TB022X config VICTOR_MPC30X bool "Victor MP-C303/304" select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select IRQ_CPU select HW_HAS_PCI @@ -58,6 +63,7 @@ config VICTOR_MPC30X config ZAO_CAPCELLA bool "ZAO Networks Capcella" select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select IRQ_CPU select HW_HAS_PCI |