diff options
Diffstat (limited to 'arch/powerpc/boot/dts/sbc8548.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/sbc8548.dts | 57 |
1 files changed, 54 insertions, 3 deletions
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index 22d967178fe9..333552b4e90d 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts @@ -44,6 +44,7 @@ timebase-frequency = <0>; // From uboot bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -161,7 +162,7 @@ interrupts = <0x12 0x2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8548-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes @@ -192,6 +193,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -262,15 +304,24 @@ fsl,has-rstcr; }; + crypto@30000 { + compatible = "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xfe>; + fsl,descriptor-types-mask = <0x12b0ebf>; + }; + mpic: pic@40000 { interrupt-controller; #address-cells = <0>; - #size-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; }; |