diff options
Diffstat (limited to 'arch/powerpc/platforms/52xx')
| -rw-r--r-- | arch/powerpc/platforms/52xx/Kconfig | 15 | ||||
| -rw-r--r-- | arch/powerpc/platforms/52xx/Makefile | 3 | ||||
| -rw-r--r-- | arch/powerpc/platforms/52xx/media5200.c | 273 | ||||
| -rw-r--r-- | arch/powerpc/platforms/52xx/mpc5200_simple.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/platforms/52xx/mpc52xx_common.c | 40 | ||||
| -rw-r--r-- | arch/powerpc/platforms/52xx/mpc52xx_gpio.c | 85 | ||||
| -rw-r--r-- | arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 396 | ||||
| -rw-r--r-- | arch/powerpc/platforms/52xx/mpc52xx_pic.c | 170 |
8 files changed, 785 insertions, 201 deletions
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig index 696a5ee4962d..8b8e9560a315 100644 --- a/arch/powerpc/platforms/52xx/Kconfig +++ b/arch/powerpc/platforms/52xx/Kconfig @@ -1,6 +1,6 @@ config PPC_MPC52xx bool "52xx-based boards" - depends on PPC_MULTIPLATFORM && PPC32 + depends on 6xx select PPC_CLOCK select PPC_PCI_CHOICE @@ -21,7 +21,13 @@ config PPC_MPC5200_SIMPLE and if there is a PCI bus node defined in the device tree. Boards that are compatible with this generic platform support - are: 'tqc,tqm5200', 'promess,motionpro', 'schindler,cm5200'. + are: + intercontrol,digsy-mtc + phytec,pcm030 + phytec,pcm032 + promess,motionpro + schindler,cm5200 + tqc,tqm5200 config PPC_EFIKA bool "bPlan Efika 5k2. MPC5200B based computer" @@ -35,6 +41,11 @@ config PPC_LITE5200 depends on PPC_MPC52xx select DEFAULT_UIMAGE +config PPC_MEDIA5200 + bool "Freescale Media5200 Eval Board" + depends on PPC_MPC52xx + select DEFAULT_UIMAGE + config PPC_MPC5200_BUGFIX bool "MPC5200 (L25R) bugfix support" depends on PPC_MPC52xx diff --git a/arch/powerpc/platforms/52xx/Makefile b/arch/powerpc/platforms/52xx/Makefile index b8a52062738a..bfd4f52cf3dd 100644 --- a/arch/powerpc/platforms/52xx/Makefile +++ b/arch/powerpc/platforms/52xx/Makefile @@ -1,12 +1,13 @@ # # Makefile for 52xx based boards # -obj-y += mpc52xx_pic.o mpc52xx_common.o +obj-y += mpc52xx_pic.o mpc52xx_common.o mpc52xx_gpt.o obj-$(CONFIG_PCI) += mpc52xx_pci.o obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o obj-$(CONFIG_PPC_EFIKA) += efika.o obj-$(CONFIG_PPC_LITE5200) += lite5200.o +obj-$(CONFIG_PPC_MEDIA5200) += media5200.o obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o ifeq ($(CONFIG_PPC_LITE5200),y) diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c new file mode 100644 index 000000000000..68e4f1696d14 --- /dev/null +++ b/arch/powerpc/platforms/52xx/media5200.c @@ -0,0 +1,273 @@ +/* + * Support for 'media5200-platform' compatible boards. + * + * Copyright (C) 2008 Secret Lab Technologies Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Description: + * This code implements support for the Freescape Media5200 platform + * (built around the MPC5200 SoC). + * + * Notable characteristic of the Media5200 is the presence of an FPGA + * that has all external IRQ lines routed through it. This file implements + * a cascaded interrupt controller driver which attaches itself to the + * Virtual IRQ subsystem after the primary mpc5200 interrupt controller + * is initialized. + * + */ + +#undef DEBUG + +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <asm/time.h> +#include <asm/prom.h> +#include <asm/machdep.h> +#include <asm/mpc52xx.h> + +static struct of_device_id mpc5200_gpio_ids[] __initdata = { + { .compatible = "fsl,mpc5200-gpio", }, + { .compatible = "mpc5200-gpio", }, + {} +}; + +/* FPGA register set */ +#define MEDIA5200_IRQ_ENABLE (0x40c) +#define MEDIA5200_IRQ_STATUS (0x410) +#define MEDIA5200_NUM_IRQS (6) +#define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS) + +struct media5200_irq { + void __iomem *regs; + spinlock_t lock; + struct irq_host *irqhost; +}; +struct media5200_irq media5200_irq; + +static void media5200_irq_unmask(unsigned int virq) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&media5200_irq.lock, flags); + val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); + val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq); + out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); + spin_unlock_irqrestore(&media5200_irq.lock, flags); +} + +static void media5200_irq_mask(unsigned int virq) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&media5200_irq.lock, flags); + val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); + val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq)); + out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); + spin_unlock_irqrestore(&media5200_irq.lock, flags); +} + +static struct irq_chip media5200_irq_chip = { + .typename = "Media5200 FPGA", + .unmask = media5200_irq_unmask, + .mask = media5200_irq_mask, + .mask_ack = media5200_irq_mask, +}; + +void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) +{ + int sub_virq, val; + u32 status, enable; + + /* Mask off the cascaded IRQ */ + spin_lock(&desc->lock); + desc->chip->mask(virq); + spin_unlock(&desc->lock); + + /* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs + * are pending. 'ffs()' is 1 based */ + status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); + enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS); + val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT); + if (val) { + sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1); + /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n", + * __func__, virq, status, enable, val - 1, sub_virq); + */ + generic_handle_irq(sub_virq); + } + + /* Processing done; can reenable the cascade now */ + spin_lock(&desc->lock); + desc->chip->ack(virq); + if (!(desc->status & IRQ_DISABLED)) + desc->chip->unmask(virq); + spin_unlock(&desc->lock); +} + +static int media5200_irq_map(struct irq_host *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct irq_desc *desc = get_irq_desc(virq); + + pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw); + set_irq_chip_data(virq, &media5200_irq); + set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq); + set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); + desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); + desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL; + + return 0; +} + +static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct, + u32 *intspec, unsigned int intsize, + irq_hw_number_t *out_hwirq, + unsigned int *out_flags) +{ + if (intsize != 2) + return -1; + + pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]); + *out_hwirq = intspec[1]; + *out_flags = IRQ_TYPE_NONE; + return 0; +} + +static struct irq_host_ops media5200_irq_ops = { + .map = media5200_irq_map, + .xlate = media5200_irq_xlate, +}; + +/* + * Setup Media5200 IRQ mapping + */ +static void __init media5200_init_irq(void) +{ + struct device_node *fpga_np; + int cascade_virq; + + /* First setup the regular MPC5200 interrupt controller */ + mpc52xx_init_irq(); + + /* Now find the FPGA IRQ */ + fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga"); + if (!fpga_np) + goto out; + pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name); + + media5200_irq.regs = of_iomap(fpga_np, 0); + if (!media5200_irq.regs) + goto out; + pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs); + + cascade_virq = irq_of_parse_and_map(fpga_np, 0); + if (!cascade_virq) + goto out; + pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq); + + /* Disable all FPGA IRQs */ + out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0); + + spin_lock_init(&media5200_irq.lock); + + media5200_irq.irqhost = irq_alloc_host(fpga_np, IRQ_HOST_MAP_LINEAR, + MEDIA5200_NUM_IRQS, + &media5200_irq_ops, -1); + if (!media5200_irq.irqhost) + goto out; + pr_debug("%s: allocated irqhost\n", __func__); + + media5200_irq.irqhost->host_data = &media5200_irq; + + set_irq_data(cascade_virq, &media5200_irq); + set_irq_chained_handler(cascade_virq, media5200_irq_cascade); + + return; + + out: + pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n"); +} + +/* + * Setup the architecture + */ +static void __init media5200_setup_arch(void) +{ + + struct device_node *np; + struct mpc52xx_gpio __iomem *gpio; + u32 port_config; + + if (ppc_md.progress) + ppc_md.progress("media5200_setup_arch()", 0); + + /* Map important registers from the internal memory map */ + mpc52xx_map_common_devices(); + + /* Some mpc5200 & mpc5200b related configuration */ + mpc5200_setup_xlb_arbiter(); + + mpc52xx_setup_pci(); + + np = of_find_matching_node(NULL, mpc5200_gpio_ids); + gpio = of_iomap(np, 0); + of_node_put(np); + if (!gpio) { + printk(KERN_ERR "%s() failed. expect abnormal behavior\n", + __func__); + return; + } + + /* Set port config */ + port_config = in_be32(&gpio->port_config); + + port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */ + port_config |= 0x01000000; + + out_be32(&gpio->port_config, port_config); + + /* Unmap zone */ + iounmap(gpio); + +} + +/* list of the supported boards */ +static char *board[] __initdata = { + "fsl,media5200", + NULL +}; + +/* + * Called very early, MMU is off, device-tree isn't unflattened + */ +static int __init media5200_probe(void) +{ + unsigned long node = of_get_flat_dt_root(); + int i = 0; + + while (board[i]) { + if (of_flat_dt_is_compatible(node, board[i])) + break; + i++; + } + + return (board[i] != NULL); +} + +define_machine(media5200_platform) { + .name = "media5200-platform", + .probe = media5200_probe, + .setup_arch = media5200_setup_arch, + .init = mpc52xx_declare_of_platform_devices, + .init_IRQ = media5200_init_irq, + .get_irq = mpc52xx_get_irq, + .restart = mpc52xx_restart, + .calibrate_decr = generic_calibrate_decr, +}; diff --git a/arch/powerpc/platforms/52xx/mpc5200_simple.c b/arch/powerpc/platforms/52xx/mpc5200_simple.c index a3bda0b9f1ff..c31e5b534f0a 100644 --- a/arch/powerpc/platforms/52xx/mpc5200_simple.c +++ b/arch/powerpc/platforms/52xx/mpc5200_simple.c @@ -50,8 +50,10 @@ static void __init mpc5200_simple_setup_arch(void) /* list of the supported boards */ static char *board[] __initdata = { - "promess,motionpro", + "intercontrol,digsy-mtc", "phytec,pcm030", + "phytec,pcm032", + "promess,motionpro", "schindler,cm5200", "tqc,tqm5200", NULL diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c index 98367a0255f3..8e3dd5a0f228 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_common.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c @@ -28,9 +28,10 @@ static struct of_device_id mpc52xx_xlb_ids[] __initdata = { static struct of_device_id mpc52xx_bus_ids[] __initdata = { { .compatible = "fsl,mpc5200-immr", }, { .compatible = "fsl,mpc5200b-immr", }, - { .compatible = "fsl,lpb", }, + { .compatible = "simple-bus", }, /* depreciated matches; shouldn't be used in new device trees */ + { .compatible = "fsl,lpb", }, { .type = "builtin", .compatible = "mpc5200", }, /* efika */ { .type = "soc", .compatible = "mpc5200", }, /* lite5200 */ {} @@ -205,6 +206,43 @@ int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv) EXPORT_SYMBOL(mpc52xx_set_psc_clkdiv); /** + * mpc52xx_get_xtal_freq - Get SYS_XTAL_IN frequency for a device + * + * @node: device node + * + * Returns the frequency of the external oscillator clock connected + * to the SYS_XTAL_IN pin, or 0 if it cannot be determined. + */ +unsigned int mpc52xx_get_xtal_freq(struct device_node *node) +{ + u32 val; + unsigned int freq; + + if (!mpc52xx_cdm) + return 0; + + freq = mpc52xx_find_ipb_freq(node); + if (!freq) + return 0; + + if (in_8(&mpc52xx_cdm->ipb_clk_sel) & 0x1) + freq *= 2; + + val = in_be32(&mpc52xx_cdm->rstcfg); + if (val & (1 << 5)) + freq *= 8; + else + freq *= 4; + if (val & (1 << 6)) + freq /= 12; + else + freq /= 16; + + return freq; +} +EXPORT_SYMBOL(mpc52xx_get_xtal_freq); + +/** * mpc52xx_restart: ppc_md->restart hook for mpc5200 using the watchdog timer */ void diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c index 07f89ae46d04..2b8d8ef32e4e 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c @@ -354,88 +354,6 @@ static struct of_platform_driver mpc52xx_simple_gpiochip_driver = { .remove = mpc52xx_gpiochip_remove, }; -/* - * GPIO LIB API implementation for gpt GPIOs. - * - * Each gpt only has a single GPIO. - */ -static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio) -{ - struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); - struct mpc52xx_gpt __iomem *regs = mm_gc->regs; - - return (in_be32(®s->status) & (1 << (31 - 23))) ? 1 : 0; -} - -static void -mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) -{ - struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); - struct mpc52xx_gpt __iomem *regs = mm_gc->regs; - - if (val) - out_be32(®s->mode, 0x34); - else - out_be32(®s->mode, 0x24); - - pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); -} - -static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) -{ - struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); - struct mpc52xx_gpt __iomem *regs = mm_gc->regs; - - out_be32(®s->mode, 0x04); - - return 0; -} - -static int -mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) -{ - mpc52xx_gpt_gpio_set(gc, gpio, val); - pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); - - return 0; -} - -static int __devinit mpc52xx_gpt_gpiochip_probe(struct of_device *ofdev, - const struct of_device_id *match) -{ - struct of_mm_gpio_chip *mmchip; - struct of_gpio_chip *chip; - - mmchip = kzalloc(sizeof(*mmchip), GFP_KERNEL); - if (!mmchip) - return -ENOMEM; - - chip = &mmchip->of_gc; - - chip->gpio_cells = 2; - chip->gc.ngpio = 1; - chip->gc.direction_input = mpc52xx_gpt_gpio_dir_in; - chip->gc.direction_output = mpc52xx_gpt_gpio_dir_out; - chip->gc.get = mpc52xx_gpt_gpio_get; - chip->gc.set = mpc52xx_gpt_gpio_set; - - return of_mm_gpiochip_add(ofdev->node, mmchip); -} - -static const struct of_device_id mpc52xx_gpt_gpiochip_match[] = { - { - .compatible = "fsl,mpc5200-gpt-gpio", - }, - {} -}; - -static struct of_platform_driver mpc52xx_gpt_gpiochip_driver = { - .name = "gpio_gpt", - .match_table = mpc52xx_gpt_gpiochip_match, - .probe = mpc52xx_gpt_gpiochip_probe, - .remove = mpc52xx_gpiochip_remove, -}; - static int __init mpc52xx_gpio_init(void) { if (of_register_platform_driver(&mpc52xx_wkup_gpiochip_driver)) @@ -444,9 +362,6 @@ static int __init mpc52xx_gpio_init(void) if (of_register_platform_driver(&mpc52xx_simple_gpiochip_driver)) printk(KERN_ERR "Unable to register simple GPIO driver\n"); - if (of_register_platform_driver(&mpc52xx_gpt_gpiochip_driver)) - printk(KERN_ERR "Unable to register gpt GPIO driver\n"); - return 0; } diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c new file mode 100644 index 000000000000..bfbcd418e690 --- /dev/null +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c @@ -0,0 +1,396 @@ +/* + * MPC5200 General Purpose Timer device driver + * + * Copyright (c) 2009 Secret Lab Technologies Ltd. + * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This file is a driver for the the General Purpose Timer (gpt) devices + * found on the MPC5200 SoC. Each timer has an IO pin which can be used + * for GPIO or can be used to raise interrupts. The timer function can + * be used independently from the IO pin, or it can be used to control + * output signals or measure input signals. + * + * This driver supports the GPIO and IRQ controller functions of the GPT + * device. Timer functions are not yet supported, nor is the watchdog + * timer. + * + * To use the GPIO function, the following two properties must be added + * to the device tree node for the gpt device (typically in the .dts file + * for the board): + * gpio-controller; + * #gpio-cells = < 2 >; + * This driver will register the GPIO pin if it finds the gpio-controller + * property in the device tree. + * + * To use the IRQ controller function, the following two properties must + * be added to the device tree node for the gpt device: + * interrupt-controller; + * #interrupt-cells = < 1 >; + * The IRQ controller binding only uses one cell to specify the interrupt, + * and the IRQ flags are encoded in the cell. A cell is not used to encode + * the IRQ number because the GPT only has a single IRQ source. For flags, + * a value of '1' means rising edge sensitive and '2' means falling edge. + * + * The GPIO and the IRQ controller functions can be used at the same time, + * but in this use case the IO line will only work as an input. Trying to + * use it as a GPIO output will not work. + * + * When using the GPIO line as an output, it can either be driven as normal + * IO, or it can be an Open Collector (OC) output. At the moment it is the + * responsibility of either the bootloader or the platform setup code to set + * the output mode. This driver does not change the output mode setting. + */ + +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/of_gpio.h> +#include <linux/kernel.h> +#include <asm/mpc52xx.h> + +MODULE_DESCRIPTION("Freescale MPC52xx gpt driver"); +MODULE_AUTHOR("Sascha Hauer, Grant Likely"); +MODULE_LICENSE("GPL"); + +/** + * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver + * @dev: pointer to device structure + * @regs: virtual address of GPT registers + * @lock: spinlock to coordinate between different functions. + * @of_gc: of_gpio_chip instance structure; used when GPIO is enabled + * @irqhost: Pointer to irq_host instance; used when IRQ mode is supported + */ +struct mpc52xx_gpt_priv { + struct device *dev; + struct mpc52xx_gpt __iomem *regs; + spinlock_t lock; + struct irq_host *irqhost; + +#if defined(CONFIG_GPIOLIB) + struct of_gpio_chip of_gc; +#endif +}; + +#define MPC52xx_GPT_MODE_MS_MASK (0x07) +#define MPC52xx_GPT_MODE_MS_IC (0x01) +#define MPC52xx_GPT_MODE_MS_OC (0x02) +#define MPC52xx_GPT_MODE_MS_PWM (0x03) +#define MPC52xx_GPT_MODE_MS_GPIO (0x04) + +#define MPC52xx_GPT_MODE_GPIO_MASK (0x30) +#define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20) +#define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30) + +#define MPC52xx_GPT_MODE_IRQ_EN (0x0100) + +#define MPC52xx_GPT_MODE_ICT_MASK (0x030000) +#define MPC52xx_GPT_MODE_ICT_RISING (0x010000) +#define MPC52xx_GPT_MODE_ICT_FALLING (0x020000) +#define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000) + +#define MPC52xx_GPT_STATUS_IRQMASK (0x000f) + +/* --------------------------------------------------------------------- + * Cascaded interrupt controller hooks + */ + +static void mpc52xx_gpt_irq_unmask(unsigned int virq) +{ + struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq); + unsigned long flags; + + spin_lock_irqsave(&gpt->lock, flags); + setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); + spin_unlock_irqrestore(&gpt->lock, flags); +} + +static void mpc52xx_gpt_irq_mask(unsigned int virq) +{ + struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq); + unsigned long flags; + + spin_lock_irqsave(&gpt->lock, flags); + clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); + spin_unlock_irqrestore(&gpt->lock, flags); +} + +static void mpc52xx_gpt_irq_ack(unsigned int virq) +{ + struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq); + + out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK); +} + +static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type) +{ + struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq); + unsigned long flags; + u32 reg; + + dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, virq, flow_type); + + spin_lock_irqsave(&gpt->lock, flags); + reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK; + if (flow_type & IRQF_TRIGGER_RISING) + reg |= MPC52xx_GPT_MODE_ICT_RISING; + if (flow_type & IRQF_TRIGGER_FALLING) + reg |= MPC52xx_GPT_MODE_ICT_FALLING; + out_be32(&gpt->regs->mode, reg); + spin_unlock_irqrestore(&gpt->lock, flags); + + return 0; +} + +static struct irq_chip mpc52xx_gpt_irq_chip = { + .typename = "MPC52xx GPT", + .unmask = mpc52xx_gpt_irq_unmask, + .mask = mpc52xx_gpt_irq_mask, + .ack = mpc52xx_gpt_irq_ack, + .set_type = mpc52xx_gpt_irq_set_type, +}; + +void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc) +{ + struct mpc52xx_gpt_priv *gpt = get_irq_data(virq); + int sub_virq; + u32 status; + + status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK; + if (status) { + sub_virq = irq_linear_revmap(gpt->irqhost, 0); + generic_handle_irq(sub_virq); + } +} + +static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct mpc52xx_gpt_priv *gpt = h->host_data; + + dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq); + set_irq_chip_data(virq, gpt); + set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq); + + return 0; +} + +static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct, + u32 *intspec, unsigned int intsize, + irq_hw_number_t *out_hwirq, + unsigned int *out_flags) +{ + struct mpc52xx_gpt_priv *gpt = h->host_data; + + dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]); + + if ((intsize < 1) || (intspec[0] < 1) || (intspec[0] > 3)) { + dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name); + return -EINVAL; + } + + *out_hwirq = 0; /* The GPT only has 1 IRQ line */ + *out_flags = intspec[0]; + + return 0; +} + +static struct irq_host_ops mpc52xx_gpt_irq_ops = { + .map = mpc52xx_gpt_irq_map, + .xlate = mpc52xx_gpt_irq_xlate, +}; + +static void +mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) +{ + int cascade_virq; + unsigned long flags; + + /* Only setup cascaded IRQ if device tree claims the GPT is + * an interrupt controller */ + if (!of_find_property(node, "interrupt-controller", NULL)) + return; + + cascade_virq = irq_of_parse_and_map(node, 0); + + gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1, + &mpc52xx_gpt_irq_ops, -1); + if (!gpt->irqhost) { + dev_err(gpt->dev, "irq_alloc_host() failed\n"); + return; + } + + gpt->irqhost->host_data = gpt; + + set_irq_data(cascade_virq, gpt); + set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); + + /* Set to Input Capture mode */ + spin_lock_irqsave(&gpt->lock, flags); + clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK, + MPC52xx_GPT_MODE_MS_IC); + spin_unlock_irqrestore(&gpt->lock, flags); + + dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq); +} + + +/* --------------------------------------------------------------------- + * GPIOLIB hooks + */ +#if defined(CONFIG_GPIOLIB) +static inline struct mpc52xx_gpt_priv *gc_to_mpc52xx_gpt(struct gpio_chip *gc) +{ + return container_of(to_of_gpio_chip(gc), struct mpc52xx_gpt_priv,of_gc); +} + +static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc); + + return (in_be32(&gpt->regs->status) >> 8) & 1; +} + +static void +mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v) +{ + struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc); + unsigned long flags; + u32 r; + + dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v); + r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW; + + spin_lock_irqsave(&gpt->lock, flags); + clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r); + spin_unlock_irqrestore(&gpt->lock, flags); +} + +static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) +{ + struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc); + unsigned long flags; + + dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio); + + spin_lock_irqsave(&gpt->lock, flags); + clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK); + spin_unlock_irqrestore(&gpt->lock, flags); + + return 0; +} + +static int +mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) +{ + mpc52xx_gpt_gpio_set(gc, gpio, val); + return 0; +} + +static void +mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) +{ + int rc; + + /* Only setup GPIO if the device tree claims the GPT is + * a GPIO controller */ + if (!of_find_property(node, "gpio-controller", NULL)) + return; + + gpt->of_gc.gc.label = kstrdup(node->full_name, GFP_KERNEL); + if (!gpt->of_gc.gc.label) { + dev_err(gpt->dev, "out of memory\n"); + return; + } + + gpt->of_gc.gpio_cells = 2; + gpt->of_gc.gc.ngpio = 1; + gpt->of_gc.gc.direction_input = mpc52xx_gpt_gpio_dir_in; + gpt->of_gc.gc.direction_output = mpc52xx_gpt_gpio_dir_out; + gpt->of_gc.gc.get = mpc52xx_gpt_gpio_get; + gpt->of_gc.gc.set = mpc52xx_gpt_gpio_set; + gpt->of_gc.gc.base = -1; + gpt->of_gc.xlate = of_gpio_simple_xlate; + node->data = &gpt->of_gc; + of_node_get(node); + + /* Setup external pin in GPIO mode */ + clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK, + MPC52xx_GPT_MODE_MS_GPIO); + + rc = gpiochip_add(&gpt->of_gc.gc); + if (rc) + dev_err(gpt->dev, "gpiochip_add() failed; rc=%i\n", rc); + + dev_dbg(gpt->dev, "%s() complete.\n", __func__); +} +#else /* defined(CONFIG_GPIOLIB) */ +static void +mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { } +#endif /* defined(CONFIG_GPIOLIB) */ + +/* --------------------------------------------------------------------- + * of_platform bus binding code + */ +static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev, + const struct of_device_id *match) +{ + struct mpc52xx_gpt_priv *gpt; + + gpt = kzalloc(sizeof *gpt, GFP_KERNEL); + if (!gpt) + return -ENOMEM; + + spin_lock_init(&gpt->lock); + gpt->dev = &ofdev->dev; + gpt->regs = of_iomap(ofdev->node, 0); + if (!gpt->regs) { + kfree(gpt); + return -ENOMEM; + } + + dev_set_drvdata(&ofdev->dev, gpt); + + mpc52xx_gpt_gpio_setup(gpt, ofdev->node); + mpc52xx_gpt_irq_setup(gpt, ofdev->node); + + return 0; +} + +static int mpc52xx_gpt_remove(struct of_device *ofdev) +{ + return -EBUSY; +} + +static const struct of_device_id mpc52xx_gpt_match[] = { + { .compatible = "fsl,mpc5200-gpt", }, + + /* Depreciated compatible values; don't use for new dts files */ + { .compatible = "fsl,mpc5200-gpt-gpio", }, + { .compatible = "mpc5200-gpt", }, + {} +}; + +static struct of_platform_driver mpc52xx_gpt_driver = { + .name = "mpc52xx-gpt", + .match_table = mpc52xx_gpt_match, + .probe = mpc52xx_gpt_probe, + .remove = mpc52xx_gpt_remove, +}; + +static int __init mpc52xx_gpt_init(void) +{ + if (of_register_platform_driver(&mpc52xx_gpt_driver)) + pr_err("error registering MPC52xx GPT driver\n"); + + return 0; +} + +/* Make sure GPIOs and IRQs get set up before anyone tries to use them */ +subsys_initcall(mpc52xx_gpt_init); diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c index 0a093f03c758..480f806fd0a9 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c @@ -163,8 +163,6 @@ static void mpc52xx_extirq_mask(unsigned int virq) irq = irq_map[virq].hwirq; l2irq = irq & MPC52xx_IRQ_L2_MASK; - pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); - io_be_clrbit(&intr->ctrl, 11 - l2irq); } @@ -176,8 +174,6 @@ static void mpc52xx_extirq_unmask(unsigned int virq) irq = irq_map[virq].hwirq; l2irq = irq & MPC52xx_IRQ_L2_MASK; - pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); - io_be_setbit(&intr->ctrl, 11 - l2irq); } @@ -189,17 +185,15 @@ static void mpc52xx_extirq_ack(unsigned int virq) irq = irq_map[virq].hwirq; l2irq = irq & MPC52xx_IRQ_L2_MASK; - pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); - io_be_setbit(&intr->ctrl, 27-l2irq); } static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type) { - struct irq_desc *desc = get_irq_desc(virq); u32 ctrl_reg, type; int irq; int l2irq; + void *handler = handle_level_irq; irq = irq_map[virq].hwirq; l2irq = irq & MPC52xx_IRQ_L2_MASK; @@ -207,32 +201,21 @@ static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type) pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type); switch (flow_type) { - case IRQF_TRIGGER_HIGH: - type = 0; - break; - case IRQF_TRIGGER_RISING: - type = 1; - break; - case IRQF_TRIGGER_FALLING: - type = 2; - break; - case IRQF_TRIGGER_LOW: - type = 3; - break; + case IRQF_TRIGGER_HIGH: type = 0; break; + case IRQF_TRIGGER_RISING: type = 1; handler = handle_edge_irq; break; + case IRQF_TRIGGER_FALLING: type = 2; handler = handle_edge_irq; break; + case IRQF_TRIGGER_LOW: type = 3; break; default: type = 0; } - desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); - desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; - if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) - desc->status |= IRQ_LEVEL; - ctrl_reg = in_be32(&intr->ctrl); ctrl_reg &= ~(0x3 << (22 - (l2irq * 2))); ctrl_reg |= (type << (22 - (l2irq * 2))); out_be32(&intr->ctrl, ctrl_reg); + __set_irq_handler_unlocked(virq, handler); + return 0; } @@ -247,6 +230,11 @@ static struct irq_chip mpc52xx_extirq_irqchip = { /* * Main interrupt irq_chip */ +static int mpc52xx_null_set_type(unsigned int virq, unsigned int flow_type) +{ + return 0; /* Do nothing so that the sense mask will get updated */ +} + static void mpc52xx_main_mask(unsigned int virq) { int irq; @@ -255,8 +243,6 @@ static void mpc52xx_main_mask(unsigned int virq) irq = irq_map[virq].hwirq; l2irq = irq & MPC52xx_IRQ_L2_MASK; - pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); - io_be_setbit(&intr->main_mask, 16 - l2irq); } @@ -268,8 +254,6 @@ static void mpc52xx_main_unmask(unsigned int virq) irq = irq_map[virq].hwirq; l2irq = irq & MPC52xx_IRQ_L2_MASK; - pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); - io_be_clrbit(&intr->main_mask, 16 - l2irq); } @@ -278,6 +262,7 @@ static struct irq_chip mpc52xx_main_irqchip = { .mask = mpc52xx_main_mask, .mask_ack = mpc52xx_main_mask, .unmask = mpc52xx_main_unmask, + .set_type = mpc52xx_null_set_type, }; /* @@ -291,8 +276,6 @@ static void mpc52xx_periph_mask(unsigned int virq) irq = irq_map[virq].hwirq; l2irq = irq & MPC52xx_IRQ_L2_MASK; - pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); - io_be_setbit(&intr->per_mask, 31 - l2irq); } @@ -304,8 +287,6 @@ static void mpc52xx_periph_unmask(unsigned int virq) irq = irq_map[virq].hwirq; l2irq = irq & MPC52xx_IRQ_L2_MASK; - pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); - io_be_clrbit(&intr->per_mask, 31 - l2irq); } @@ -314,6 +295,7 @@ static struct irq_chip mpc52xx_periph_irqchip = { .mask = mpc52xx_periph_mask, .mask_ack = mpc52xx_periph_mask, .unmask = mpc52xx_periph_unmask, + .set_type = mpc52xx_null_set_type, }; /* @@ -327,8 +309,6 @@ static void mpc52xx_sdma_mask(unsigned int virq) irq = irq_map[virq].hwirq; l2irq = irq & MPC52xx_IRQ_L2_MASK; - pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); - io_be_setbit(&sdma->IntMask, l2irq); } @@ -340,8 +320,6 @@ static void mpc52xx_sdma_unmask(unsigned int virq) irq = irq_map[virq].hwirq; l2irq = irq & MPC52xx_IRQ_L2_MASK; - pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); - io_be_clrbit(&sdma->IntMask, l2irq); } @@ -353,8 +331,6 @@ static void mpc52xx_sdma_ack(unsigned int virq) irq = irq_map[virq].hwirq; l2irq = irq & MPC52xx_IRQ_L2_MASK; - pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); - out_be32(&sdma->IntPend, 1 << l2irq); } @@ -363,9 +339,19 @@ static struct irq_chip mpc52xx_sdma_irqchip = { .mask = mpc52xx_sdma_mask, .unmask = mpc52xx_sdma_unmask, .ack = mpc52xx_sdma_ack, + .set_type = mpc52xx_null_set_type, }; /** + * mpc52xx_is_extirq - Returns true if hwirq number is for an external IRQ + */ +static int mpc52xx_is_extirq(int l1, int l2) +{ + return ((l1 == 0) && (l2 == 0)) || + ((l1 == 1) && (l2 >= 1) && (l2 <= 3)); +} + +/** * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property */ static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct, @@ -383,38 +369,23 @@ static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct, intrvect_l1 = (int)intspec[0]; intrvect_l2 = (int)intspec[1]; - intrvect_type = (int)intspec[2]; + intrvect_type = (int)intspec[2] & 0x3; intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK; intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK; - pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1, - intrvect_l2); - *out_hwirq = intrvect_linux; - *out_flags = mpc52xx_map_senses[intrvect_type]; + *out_flags = IRQ_TYPE_LEVEL_LOW; + if (mpc52xx_is_extirq(intrvect_l1, intrvect_l2)) + *out_flags = mpc52xx_map_senses[intrvect_type]; + pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1, + intrvect_l2); return 0; } /** - * mpc52xx_irqx_gettype - determine the IRQ sense type (level/edge) - * - * Only external IRQs need this. - */ -static int mpc52xx_irqx_gettype(int irq) -{ - int type; - u32 ctrl_reg; - - ctrl_reg = in_be32(&intr->ctrl); - type = (ctrl_reg >> (22 - irq * 2)) & 0x3; - - return mpc52xx_map_senses[type]; -} - -/** * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure */ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, @@ -422,68 +393,46 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, { int l1irq; int l2irq; - struct irq_chip *good_irqchip; - void *good_handle; + struct irq_chip *irqchip; + void *hndlr; int type; + u32 reg; l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET; l2irq = irq & MPC52xx_IRQ_L2_MASK; /* - * Most of ours IRQs will be level low - * Only external IRQs on some platform may be others + * External IRQs are handled differently by the hardware so they are + * handled by a dedicated irq_chip structure. */ - type = IRQ_TYPE_LEVEL_LOW; + if (mpc52xx_is_extirq(l1irq, l2irq)) { + reg = in_be32(&intr->ctrl); + type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3]; + if ((type == IRQ_TYPE_EDGE_FALLING) || + (type == IRQ_TYPE_EDGE_RISING)) + hndlr = handle_edge_irq; + else + hndlr = handle_level_irq; + + set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr); + pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n", + __func__, l2irq, virq, (int)irq, type); + return 0; + } + /* It is an internal SOC irq. Choose the correct irq_chip */ switch (l1irq) { - case MPC52xx_IRQ_L1_CRIT: - pr_debug("%s: Critical. l2=%x\n", __func__, l2irq); - - BUG_ON(l2irq != 0); - - type = mpc52xx_irqx_gettype(l2irq); - good_irqchip = &mpc52xx_extirq_irqchip; - break; - - case MPC52xx_IRQ_L1_MAIN: - pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq); - - if ((l2irq >= 1) && (l2irq <= 3)) { - type = mpc52xx_irqx_gettype(l2irq); - good_irqchip = &mpc52xx_extirq_irqchip; - } else { - good_irqchip = &mpc52xx_main_irqchip; - } - break; - - case MPC52xx_IRQ_L1_PERP: - pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq); - good_irqchip = &mpc52xx_periph_irqchip; - break; - - case MPC52xx_IRQ_L1_SDMA: - pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq); - good_irqchip = &mpc52xx_sdma_irqchip; - break; - + case MPC52xx_IRQ_L1_MAIN: irqchip = &mpc52xx_main_irqchip; break; + case MPC52xx_IRQ_L1_PERP: irqchip = &mpc52xx_periph_irqchip; break; + case MPC52xx_IRQ_L1_SDMA: irqchip = &mpc52xx_sdma_irqchip; break; default: - pr_err("%s: invalid virq requested (0x%x)\n", __func__, virq); + pr_err("%s: invalid irq: virq=%i, l1=%i, l2=%i\n", + __func__, virq, l1irq, l2irq); return -EINVAL; } - switch (type) { - case IRQ_TYPE_EDGE_FALLING: - case IRQ_TYPE_EDGE_RISING: - good_handle = handle_edge_irq; - break; - default: - good_handle = handle_level_irq; - } - - set_irq_chip_and_handler(virq, good_irqchip, good_handle); - - pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq, - (int)irq, type); + set_irq_chip_and_handler(virq, irqchip, handle_level_irq); + pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq); return 0; } @@ -522,6 +471,8 @@ void __init mpc52xx_init_irq(void) panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. " "Check node !"); + pr_debug("MPC5200 IRQ controller mapped to 0x%p\n", intr); + /* Disable all interrupt sources. */ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */ @@ -613,8 +564,5 @@ unsigned int mpc52xx_get_irq(void) } } - pr_debug("%s: irq=%x. virq=%d\n", __func__, irq, - irq_linear_revmap(mpc52xx_irqhost, irq)); - return irq_linear_revmap(mpc52xx_irqhost, irq); } |