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-rw-r--r--arch/ppc/syslib/Makefile2
-rw-r--r--arch/ppc/syslib/cpm2_common.c1
-rw-r--r--arch/ppc/syslib/ibm440gx_common.c15
-rw-r--r--arch/ppc/syslib/ibm44x_common.h4
-rw-r--r--arch/ppc/syslib/m8260_setup.c3
-rw-r--r--arch/ppc/syslib/m82xx_pci.c6
-rw-r--r--arch/ppc/syslib/m8xx_setup.c8
-rw-r--r--arch/ppc/syslib/mpc10x_common.c53
-rw-r--r--arch/ppc/syslib/mpc83xx_devices.c8
-rw-r--r--arch/ppc/syslib/ppc85xx_setup.c4
10 files changed, 76 insertions, 28 deletions
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index dec5bf4f6879..220a65ab0a51 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram.o
obj-$(CONFIG_PPC_OCP) += ocp.o
obj-$(CONFIG_IBM_OCP) += ibm_ocp.o
obj-$(CONFIG_44x) += ibm44x_common.o
+obj-$(CONFIG_440EP) += ibm440gx_common.o
obj-$(CONFIG_440GP) += ibm440gp_common.o
obj-$(CONFIG_440GX) += ibm440gx_common.o
obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
@@ -44,6 +45,7 @@ obj-$(CONFIG_PPC_CHRP) += open_pic.o indirect_pci.o i8259.o
obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
todc_time.o
+obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
diff --git a/arch/ppc/syslib/cpm2_common.c b/arch/ppc/syslib/cpm2_common.c
index 4c19a4ac7163..cbac44b1620c 100644
--- a/arch/ppc/syslib/cpm2_common.c
+++ b/arch/ppc/syslib/cpm2_common.c
@@ -27,7 +27,6 @@
#include <asm/mpc8260.h>
#include <asm/page.h>
#include <asm/pgtable.h>
-#include <asm/immap_cpm2.h>
#include <asm/cpm2.h>
#include <asm/rheap.h>
diff --git a/arch/ppc/syslib/ibm440gx_common.c b/arch/ppc/syslib/ibm440gx_common.c
index 4ad85e0e0234..d4776af6a3ca 100644
--- a/arch/ppc/syslib/ibm440gx_common.c
+++ b/arch/ppc/syslib/ibm440gx_common.c
@@ -34,6 +34,10 @@ void __init ibm440gx_get_clocks(struct ibm44x_clocks* p, unsigned int sys_clk,
u32 plld = CPR_READ(DCRN_CPR_PLLD);
u32 uart0 = SDR_READ(DCRN_SDR_UART0);
u32 uart1 = SDR_READ(DCRN_SDR_UART1);
+#ifdef CONFIG_440EP
+ u32 uart2 = SDR_READ(DCRN_SDR_UART2);
+ u32 uart3 = SDR_READ(DCRN_SDR_UART3);
+#endif
/* Dividers */
u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
@@ -96,6 +100,17 @@ bypass:
p->uart1 = ser_clk;
else
p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+#ifdef CONFIG_440EP
+ if (uart2 & 0x00800000)
+ p->uart2 = ser_clk;
+ else
+ p->uart2 = p->plb / __fix_zero(uart2 & 0xff, 256);
+
+ if (uart3 & 0x00800000)
+ p->uart3 = ser_clk;
+ else
+ p->uart3 = p->plb / __fix_zero(uart3 & 0xff, 256);
+#endif
}
/* Issue L2C diagnostic command */
diff --git a/arch/ppc/syslib/ibm44x_common.h b/arch/ppc/syslib/ibm44x_common.h
index b14eb603ce01..c16b6a5ac6ab 100644
--- a/arch/ppc/syslib/ibm44x_common.h
+++ b/arch/ppc/syslib/ibm44x_common.h
@@ -29,6 +29,10 @@ struct ibm44x_clocks {
unsigned int ebc; /* PerClk */
unsigned int uart0;
unsigned int uart1;
+#ifdef CONFIG_440EP
+ unsigned int uart2;
+ unsigned int uart3;
+#endif
};
/* common 44x platform init */
diff --git a/arch/ppc/syslib/m8260_setup.c b/arch/ppc/syslib/m8260_setup.c
index fda75d79050c..8f80a42dfdb7 100644
--- a/arch/ppc/syslib/m8260_setup.c
+++ b/arch/ppc/syslib/m8260_setup.c
@@ -24,7 +24,7 @@
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/mpc8260.h>
-#include <asm/immap_cpm2.h>
+#include <asm/cpm2.h>
#include <asm/machdep.h>
#include <asm/bootinfo.h>
#include <asm/time.h>
@@ -33,7 +33,6 @@
unsigned char __res[sizeof(bd_t)];
-extern void cpm2_reset(void);
extern void pq2_find_bridges(void);
extern void pq2pci_init_irq(void);
extern void idma_pci9_init(void);
diff --git a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c
index 5e7a7edcea74..9db58c587b46 100644
--- a/arch/ppc/syslib/m82xx_pci.c
+++ b/arch/ppc/syslib/m82xx_pci.c
@@ -238,9 +238,9 @@ pq2ads_setup_pci(struct pci_controller *hose)
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
* and local bus for PCI (SIUMCR [LBPC]).
*/
- immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
- ~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
- SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10;
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr &
+ ~(SIUMCR_L2CPC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
+ SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10);
#endif
/* Enable PCI */
immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c
index c1db2ab1d154..55a381af4e37 100644
--- a/arch/ppc/syslib/m8xx_setup.c
+++ b/arch/ppc/syslib/m8xx_setup.c
@@ -57,7 +57,7 @@ unsigned char __res[sizeof(bd_t)];
extern void m8xx_ide_init(void);
extern unsigned long find_available_memory(void);
-extern void m8xx_cpm_reset(uint cpm_page);
+extern void m8xx_cpm_reset();
extern void m8xx_wdt_handler_install(bd_t *bp);
extern void rpxfb_alloc_pages(void);
extern void cpm_interrupt_init(void);
@@ -70,13 +70,9 @@ board_init(void)
void __init
m8xx_setup_arch(void)
{
- int cpm_page;
-
- cpm_page = (int) alloc_bootmem_pages(PAGE_SIZE);
-
/* Reset the Communication Processor Module.
*/
- m8xx_cpm_reset(cpm_page);
+ m8xx_cpm_reset();
#ifdef CONFIG_FB_RPX
rpxfb_alloc_pages();
diff --git a/arch/ppc/syslib/mpc10x_common.c b/arch/ppc/syslib/mpc10x_common.c
index 8fc5f4154521..87065e2e4c5f 100644
--- a/arch/ppc/syslib/mpc10x_common.c
+++ b/arch/ppc/syslib/mpc10x_common.c
@@ -45,24 +45,29 @@
#define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS)
#define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS)
#define MPC10X_UART0_IRQ (EPIC_IRQ_BASE + 4 + NUM_8259_INTERRUPTS)
+#define MPC10X_UART1_IRQ (EPIC_IRQ_BASE + 5 + NUM_8259_INTERRUPTS)
#else
#define MPC10X_I2C_IRQ -1
#define MPC10X_DMA0_IRQ -1
#define MPC10X_DMA1_IRQ -1
#define MPC10X_UART0_IRQ -1
+#define MPC10X_UART1_IRQ -1
#endif
static struct fsl_i2c_platform_data mpc10x_i2c_pdata = {
.device_flags = 0,
};
-static struct plat_serial8250_port serial_platform_data[] = {
+static struct plat_serial8250_port serial_plat_uart0[] = {
[0] = {
.mapbase = 0x4500,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
},
- [1] = {
+ { },
+};
+static struct plat_serial8250_port serial_plat_uart1[] = {
+ [0] = {
.mapbase = 0x4600,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
@@ -133,11 +138,17 @@ struct platform_device ppc_sys_platform_devices[] = {
},
},
},
- [MPC10X_DUART] = {
+ [MPC10X_UART0] = {
.name = "serial8250",
.id = 0,
- .dev.platform_data = serial_platform_data,
+ .dev.platform_data = serial_plat_uart0,
},
+ [MPC10X_UART1] = {
+ .name = "serial8250",
+ .id = 1,
+ .dev.platform_data = serial_plat_uart1,
+ },
+
};
/* We use the PCI ID to match on */
@@ -147,10 +158,10 @@ struct ppc_sys_spec ppc_sys_specs[] = {
.ppc_sys_name = "8245",
.mask = 0xFFFFFFFF,
.value = MPC10X_BRIDGE_8245,
- .num_devices = 4,
+ .num_devices = 5,
.device_list = (enum ppc_sys_devices[])
{
- MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_DUART,
+ MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_UART0, MPC10X_UART1,
},
},
{
@@ -180,6 +191,25 @@ struct ppc_sys_spec ppc_sys_specs[] = {
},
};
+/*
+ * mach_mpc10x_fixup: This function enables DUART mode if it detects
+ * if it detects two UARTS in the platform device entries.
+ */
+static int __init mach_mpc10x_fixup(struct platform_device *pdev)
+{
+ if (strncmp (pdev->name, "serial8250", 10) == 0 && pdev->id == 1)
+ writeb(readb(serial_plat_uart1[0].membase + 0x11) | 0x1,
+ serial_plat_uart1[0].membase + 0x11);
+ return 0;
+}
+
+static int __init mach_mpc10x_init(void)
+{
+ ppc_sys_device_fixup = mach_mpc10x_fixup;
+ return 0;
+}
+postcore_initcall(mach_mpc10x_init);
+
/* Set resources to match bridge memory map */
void __init
mpc10x_bridge_set_resources(int map, struct pci_controller *hose)
@@ -219,6 +249,7 @@ mpc10x_bridge_set_resources(int map, struct pci_controller *hose)
ppc_md.progress("mpc10x:exit1", 0x100);
}
}
+
/*
* Do some initialization and put the EUMB registers at the specified address
* (also map the EPIC registers into virtual space--OpenPIC_Addr will be set).
@@ -411,11 +442,13 @@ mpc10x_bridge_init(struct pci_controller *hose,
ppc_sys_platform_devices[MPC10X_DMA1].resource[1].start = MPC10X_DMA1_IRQ;
ppc_sys_platform_devices[MPC10X_DMA1].resource[1].end = MPC10X_DMA1_IRQ;
- serial_platform_data[0].mapbase += phys_eumb_base;
- serial_platform_data[0].irq = MPC10X_UART0_IRQ;
+ serial_plat_uart0[0].mapbase += phys_eumb_base;
+ serial_plat_uart0[0].irq = MPC10X_UART0_IRQ;
+ serial_plat_uart0[0].membase = ioremap(serial_plat_uart0[0].mapbase, 0x100);
- serial_platform_data[1].mapbase += phys_eumb_base;
- serial_platform_data[1].irq = MPC10X_UART0_IRQ + 1;
+ serial_plat_uart1[0].mapbase += phys_eumb_base;
+ serial_plat_uart1[0].irq = MPC10X_UART1_IRQ;
+ serial_plat_uart1[0].membase = ioremap(serial_plat_uart1[0].mapbase, 0x100);
/*
* 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative
diff --git a/arch/ppc/syslib/mpc83xx_devices.c b/arch/ppc/syslib/mpc83xx_devices.c
index 75c8e9834ae7..5aaf0e58e1f9 100644
--- a/arch/ppc/syslib/mpc83xx_devices.c
+++ b/arch/ppc/syslib/mpc83xx_devices.c
@@ -191,8 +191,8 @@ struct platform_device ppc_sys_platform_devices[] = {
.num_resources = 2,
.resource = (struct resource[]) {
{
- .start = 0x22000,
- .end = 0x22fff,
+ .start = 0x23000,
+ .end = 0x23fff,
.flags = IORESOURCE_MEM,
},
{
@@ -208,8 +208,8 @@ struct platform_device ppc_sys_platform_devices[] = {
.num_resources = 2,
.resource = (struct resource[]) {
{
- .start = 0x23000,
- .end = 0x23fff,
+ .start = 0x22000,
+ .end = 0x22fff,
.flags = IORESOURCE_MEM,
},
{
diff --git a/arch/ppc/syslib/ppc85xx_setup.c b/arch/ppc/syslib/ppc85xx_setup.c
index ca95d79a704e..b7242f1bd931 100644
--- a/arch/ppc/syslib/ppc85xx_setup.c
+++ b/arch/ppc/syslib/ppc85xx_setup.c
@@ -233,14 +233,14 @@ mpc85xx_setup_pci2(struct pci_controller *hose)
pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
/* Enable, Mem R/W */
pci->powar1 = 0x80044000 |
- (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
+ (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1);
/* Setup outboud IO windows @ MPC85XX_PCI2_IO_BASE */
pci->potar2 = 0x00000000;
pci->potear2 = 0x00000000;
pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
/* Enable, IO R/W */
- pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
+ pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1);
/* Setup 2G inbound Memory Window @ 0 */
pci->pitar1 = 0x00000000;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-16 11:30:22 +0100