diff options
Diffstat (limited to 'drivers/clk/hisilicon')
| -rw-r--r-- | drivers/clk/hisilicon/clk-hi3660.c | 6 | ||||
| -rw-r--r-- | drivers/clk/hisilicon/clk-hisi-phase.c | 4 |
2 files changed, 7 insertions, 3 deletions
diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index f40419959656..794eeff0d5d2 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -163,8 +163,12 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = { "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 17, 0, }, { HI3660_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2", "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, }, + /* + * clk_gate_ufs_subsys is a system bus clock, mark it as critical + * clock and keep it on for system suspend and resume. + */ { HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus", - CLK_SET_RATE_PARENT, 0x50, 21, 0, }, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x50, 21, 0, }, { HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus", CLK_SET_RATE_PARENT, 0x50, 28, 0, }, { HI3660_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus", diff --git a/drivers/clk/hisilicon/clk-hisi-phase.c b/drivers/clk/hisilicon/clk-hisi-phase.c index 5fdc267bb2da..ba6afad66a2b 100644 --- a/drivers/clk/hisilicon/clk-hisi-phase.c +++ b/drivers/clk/hisilicon/clk-hisi-phase.c @@ -75,10 +75,10 @@ static int hisi_clk_set_phase(struct clk_hw *hw, int degrees) spin_lock_irqsave(phase->lock, flags); - val = clk_readl(phase->reg); + val = readl(phase->reg); val &= ~phase->mask; val |= regval << phase->shift; - clk_writel(val, phase->reg); + writel(val, phase->reg); spin_unlock_irqrestore(phase->lock, flags); |