diff options
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5433.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 44 |
1 files changed, 24 insertions, 20 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index f096bd7df40c..11343a597093 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -6,7 +6,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Common Clock Framework support for Exynos5443 SoC. + * Common Clock Framework support for Exynos5433 SoC. */ #include <linux/clk-provider.h> @@ -549,10 +549,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { 29, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400", ENABLE_ACLK_TOP, 26, - CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400", ENABLE_ACLK_TOP, 25, - CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266", ENABLE_ACLK_TOP, 24, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), @@ -616,7 +616,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { /* ENABLE_SCLK_TOP_MSCL */ GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg", - ENABLE_SCLK_TOP_MSCL, 0, 0, 0), + ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0), /* ENABLE_SCLK_TOP_CAM1 */ GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b", @@ -698,7 +698,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL */ -static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = { +static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = { PLL_35XX_RATE(2500000000U, 625, 6, 0), PLL_35XX_RATE(2400000000U, 500, 5, 0), PLL_35XX_RATE(2300000000U, 575, 6, 0), @@ -739,7 +739,9 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = PLL_35XX_RATE(350000000U, 350, 6, 2), PLL_35XX_RATE(333000000U, 222, 4, 2), PLL_35XX_RATE(300000000U, 500, 5, 3), + PLL_35XX_RATE(278000000U, 556, 6, 3), PLL_35XX_RATE(266000000U, 532, 6, 3), + PLL_35XX_RATE(250000000U, 500, 6, 3), PLL_35XX_RATE(200000000U, 400, 6, 3), PLL_35XX_RATE(166000000U, 332, 6, 3), PLL_35XX_RATE(160000000U, 320, 6, 3), @@ -749,7 +751,7 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = }; /* AUD_PLL */ -static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] __initconst = { +static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { PLL_36XX_RATE(400000000U, 200, 3, 2, 0), PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), PLL_36XX_RATE(384000000U, 128, 2, 2, 0), @@ -764,9 +766,9 @@ static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] __initcons static const struct samsung_pll_clock top_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", - ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates), + ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates), PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", - AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates), + AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates), }; static const struct samsung_cmu_info top_cmu_info __initconst = { @@ -820,7 +822,7 @@ PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; static const struct samsung_pll_clock cpif_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", - MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates), + MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates), }; static const struct samsung_mux_clock cpif_mux_clks[] __initconst = { @@ -1011,13 +1013,13 @@ static const unsigned long mif_clk_regs[] __initconst = { static const struct samsung_pll_clock mif_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", - MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates), + MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates), PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", - MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates), + MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates), PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", - BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates), + BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates), PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", - MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates), + MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates), }; /* list of all parent clock list */ @@ -1382,7 +1384,7 @@ static const struct samsung_gate_clock mif_gate_clks[] __initconst = { /* ENABLE_ACLK_MIF3 */ GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400", ENABLE_ACLK_MIF3, 4, - CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333", ENABLE_ACLK_MIF3, 1, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), @@ -2539,7 +2541,7 @@ PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", static const struct samsung_pll_clock disp_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", - DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates), + DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates), }; static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = { @@ -2559,8 +2561,10 @@ static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), /* PHY clocks from MIPI_DPHY0 */ - FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000), - FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000), + FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy", + NULL, 0, 188000000), + FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy", + NULL, 0, 100000000), /* PHY clocks from HDMI_PHY */ FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", NULL, 0, 300000000), @@ -3224,7 +3228,7 @@ PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", - G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates), + G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates), }; static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { @@ -3514,7 +3518,7 @@ PNAME(mout_apollo_p) = { "mout_apollo_pll", static const struct samsung_pll_clock apollo_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", - APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates), + APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates), }; static const struct samsung_mux_clock apollo_mux_clks[] __initconst = { @@ -3737,7 +3741,7 @@ PNAME(mout_atlas_p) = { "mout_atlas_pll", static const struct samsung_pll_clock atlas_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", - ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates), + ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates), }; static const struct samsung_mux_clock atlas_mux_clks[] __initconst = { |