diff options
Diffstat (limited to 'drivers/isdn/hisax/ipacx.c')
| -rw-r--r-- | drivers/isdn/hisax/ipacx.c | 675 |
1 files changed, 337 insertions, 338 deletions
diff --git a/drivers/isdn/hisax/ipacx.c b/drivers/isdn/hisax/ipacx.c index 690840444184..74feb5c83067 100644 --- a/drivers/isdn/hisax/ipacx.c +++ b/drivers/isdn/hisax/ipacx.c @@ -1,10 +1,10 @@ -/* +/* * * IPACX specific routines * * Author Joerg Petersohn * Derived from hisax_isac.c, isac.c, hscx.c and others - * + * * This software may be used and distributed according to the terms * of the GNU General Public License, incorporated herein by reference. * @@ -24,7 +24,7 @@ #define D_FIFO_SIZE 32 -// ipacx interrupt mask values +// ipacx interrupt mask values #define _MASK_IMASK 0x2E // global mask #define _MASKB_IMASK 0x0B #define _MASKD_IMASK 0x03 // all on @@ -55,33 +55,33 @@ static void clear_pending_ints(struct IsdnCardState *cs); //---------------------------------------------------------- // Issue Layer 1 command to chip //---------------------------------------------------------- -static void +static void ph_command(struct IsdnCardState *cs, unsigned int command) { - if (cs->debug &L1_DEB_ISAC) + if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ph_command (%#x) in (%#x)", command, cs->dc.isac.ph_state); -//################################### +//################################### // printk(KERN_INFO "ph_command (%#x)\n", command); -//################################### +//################################### cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E); } //---------------------------------------------------------- // Transceiver interrupt handler //---------------------------------------------------------- -static inline void +static inline void cic_int(struct IsdnCardState *cs) { u_char event; event = cs->readisac(cs, IPACX_CIR0) >> 4; - if (cs->debug &L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event); -//######################################### + if (cs->debug & L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event); +//######################################### // printk(KERN_INFO "cic_int(%x)\n", event); -//######################################### - cs->dc.isac.ph_state = event; - schedule_event(cs, D_L1STATECHANGE); +//######################################### + cs->dc.isac.ph_state = event; + schedule_event(cs, D_L1STATECHANGE); } //========================================================== @@ -99,99 +99,99 @@ dch_l2l1(struct PStack *st, int pr, void *arg) u_char cda1_cr; switch (pr) { - case (PH_DATA |REQUEST): - if (cs->debug &DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len); - if (cs->debug &DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0); - if (cs->tx_skb) { - skb_queue_tail(&cs->sq, skb); -#ifdef L2FRAME_DEBUG - if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0); -#endif - } else { - cs->tx_skb = skb; - cs->tx_cnt = 0; + case (PH_DATA | REQUEST): + if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len); + if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0); + if (cs->tx_skb) { + skb_queue_tail(&cs->sq, skb); #ifdef L2FRAME_DEBUG - if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0); + if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0); #endif - dch_fill_fifo(cs); - } - break; - - case (PH_PULL |INDICATION): - if (cs->tx_skb) { - if (cs->debug & L1_DEB_WARN) - debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); - skb_queue_tail(&cs->sq, skb); - break; - } - if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len); - if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0); + } else { cs->tx_skb = skb; cs->tx_cnt = 0; #ifdef L2FRAME_DEBUG - if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); + if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0); #endif dch_fill_fifo(cs); + } + break; + + case (PH_PULL | INDICATION): + if (cs->tx_skb) { + if (cs->debug & L1_DEB_WARN) + debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); + skb_queue_tail(&cs->sq, skb); break; - - case (PH_PULL | REQUEST): + } + if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len); + if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0); + cs->tx_skb = skb; + cs->tx_cnt = 0; #ifdef L2FRAME_DEBUG - if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL"); + if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); #endif - if (!cs->tx_skb) { - clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); - st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); - } else - set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); - break; - - case (HW_RESET | REQUEST): - case (HW_ENABLE | REQUEST): - if ((cs->dc.isac.ph_state == IPACX_IND_RES) || - (cs->dc.isac.ph_state == IPACX_IND_DR) || - (cs->dc.isac.ph_state == IPACX_IND_DC)) - ph_command(cs, IPACX_CMD_TIM); - else - ph_command(cs, IPACX_CMD_RES); - break; - - case (HW_INFO3 | REQUEST): - ph_command(cs, IPACX_CMD_AR8); - break; - - case (HW_TESTLOOP | REQUEST): - cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1 - cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1 - cda1_cr = cs->readisac(cs, IPACX_CDA1_CR); - (void) cs->readisac(cs, IPACX_CDA2_CR); - if ((long)arg &1) { // loop B1 - cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x0a); - } - else { // B1 off - cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x0a); - } - if ((long)arg &2) { // loop B2 - cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x14); - } - else { // B2 off - cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x14); - } - break; + dch_fill_fifo(cs); + break; - case (HW_DEACTIVATE | RESPONSE): - skb_queue_purge(&cs->rq); - skb_queue_purge(&cs->sq); - if (cs->tx_skb) { - dev_kfree_skb_any(cs->tx_skb); - cs->tx_skb = NULL; - } - if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) - del_timer(&cs->dbusytimer); - break; + case (PH_PULL | REQUEST): +#ifdef L2FRAME_DEBUG + if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL"); +#endif + if (!cs->tx_skb) { + clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); + st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); + } else + set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); + break; + + case (HW_RESET | REQUEST): + case (HW_ENABLE | REQUEST): + if ((cs->dc.isac.ph_state == IPACX_IND_RES) || + (cs->dc.isac.ph_state == IPACX_IND_DR) || + (cs->dc.isac.ph_state == IPACX_IND_DC)) + ph_command(cs, IPACX_CMD_TIM); + else + ph_command(cs, IPACX_CMD_RES); + break; + + case (HW_INFO3 | REQUEST): + ph_command(cs, IPACX_CMD_AR8); + break; + + case (HW_TESTLOOP | REQUEST): + cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1 + cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1 + cda1_cr = cs->readisac(cs, IPACX_CDA1_CR); + (void) cs->readisac(cs, IPACX_CDA2_CR); + if ((long)arg & 1) { // loop B1 + cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x0a); + } + else { // B1 off + cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x0a); + } + if ((long)arg & 2) { // loop B2 + cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x14); + } + else { // B2 off + cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x14); + } + break; + + case (HW_DEACTIVATE | RESPONSE): + skb_queue_purge(&cs->rq); + skb_queue_purge(&cs->sq); + if (cs->tx_skb) { + dev_kfree_skb_any(cs->tx_skb); + cs->tx_skb = NULL; + } + if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) + del_timer(&cs->dbusytimer); + break; - default: - if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr); - break; + default: + if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr); + break; } } @@ -206,11 +206,11 @@ dbusy_timer_handler(struct IsdnCardState *cs) if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { rbchd = cs->readisac(cs, IPACX_RBCHD); stard = cs->readisac(cs, IPACX_STARD); - if (cs->debug) - debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard); - if (!(stard &0x40)) { // D-Channel Busy + if (cs->debug) + debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard); + if (!(stard & 0x40)) { // D-Channel Busy set_bit(FLG_L1_DBUSY, &cs->HW_Flags); - for (st = cs->stlist; st; st = st->next) { + for (st = cs->stlist; st; st = st->next) { st->l1.l1l2(st, PH_PAUSE | INDICATION, NULL); // flow control on } } else { @@ -232,30 +232,30 @@ dbusy_timer_handler(struct IsdnCardState *cs) //---------------------------------------------------------- // Fill buffer from receive FIFO //---------------------------------------------------------- -static void +static void dch_empty_fifo(struct IsdnCardState *cs, int count) { u_char *ptr; - if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO)) + if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) debugl1(cs, "dch_empty_fifo()"); - // message too large, remove + // message too large, remove if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) { - if (cs->debug &L1_DEB_WARN) + if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_empty_fifo() incoming message too large"); - cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC + cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC cs->rcvidx = 0; return; } - + ptr = cs->rcvbuf + cs->rcvidx; cs->rcvidx += count; - + cs->readisacfifo(cs, ptr, count); cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC - - if (cs->debug &L1_DEB_ISAC_FIFO) { + + if (cs->debug & L1_DEB_ISAC_FIFO) { char *t = cs->dlog; t += sprintf(t, "dch_empty_fifo() cnt %d", count); @@ -267,15 +267,15 @@ dch_empty_fifo(struct IsdnCardState *cs, int count) //---------------------------------------------------------- // Fill transmit FIFO //---------------------------------------------------------- -static void +static void dch_fill_fifo(struct IsdnCardState *cs) { int count; u_char cmd, *ptr; - if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO)) + if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) debugl1(cs, "dch_fill_fifo()"); - + if (!cs->tx_skb) return; count = cs->tx_skb->len; if (count <= 0) return; @@ -286,14 +286,14 @@ dch_fill_fifo(struct IsdnCardState *cs) } else { cmd = 0x0A; // XTF | XME } - + ptr = cs->tx_skb->data; skb_pull(cs->tx_skb, count); cs->tx_cnt += count; cs->writeisacfifo(cs, ptr, count); cs->writeisac(cs, IPACX_CMDRD, cmd); - - // set timeout for transmission contol + + // set timeout for transmission contol if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { debugl1(cs, "dch_fill_fifo dbusytimer running"); del_timer(&cs->dbusytimer); @@ -301,8 +301,8 @@ dch_fill_fifo(struct IsdnCardState *cs) init_timer(&cs->dbusytimer); cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000); add_timer(&cs->dbusytimer); - - if (cs->debug &L1_DEB_ISAC_FIFO) { + + if (cs->debug & L1_DEB_ISAC_FIFO) { char *t = cs->dlog; t += sprintf(t, "dch_fill_fifo() cnt %d", count); @@ -314,7 +314,7 @@ dch_fill_fifo(struct IsdnCardState *cs) //---------------------------------------------------------- // D channel interrupt handler //---------------------------------------------------------- -static inline void +static inline void dch_int(struct IsdnCardState *cs) { struct sk_buff *skb; @@ -322,31 +322,31 @@ dch_int(struct IsdnCardState *cs) int count; istad = cs->readisac(cs, IPACX_ISTAD); -//############################################## +//############################################## // printk(KERN_WARNING "dch_int(istad=%02x)\n", istad); -//############################################## - - if (istad &0x80) { // RME - rstad = cs->readisac(cs, IPACX_RSTAD); - if ((rstad &0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB) - if (!(rstad &0x80)) - if (cs->debug &L1_DEB_WARN) - debugl1(cs, "dch_int(): invalid frame"); - if ((rstad &0x40)) - if (cs->debug &L1_DEB_WARN) - debugl1(cs, "dch_int(): RDO"); - if (!(rstad &0x20)) - if (cs->debug &L1_DEB_WARN) - debugl1(cs, "dch_int(): CRC error"); - cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC +//############################################## + + if (istad & 0x80) { // RME + rstad = cs->readisac(cs, IPACX_RSTAD); + if ((rstad & 0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB) + if (!(rstad & 0x80)) + if (cs->debug & L1_DEB_WARN) + debugl1(cs, "dch_int(): invalid frame"); + if ((rstad & 0x40)) + if (cs->debug & L1_DEB_WARN) + debugl1(cs, "dch_int(): RDO"); + if (!(rstad & 0x20)) + if (cs->debug & L1_DEB_WARN) + debugl1(cs, "dch_int(): CRC error"); + cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC } else { // received frame ok count = cs->readisac(cs, IPACX_RBCLD); - if (count) count--; // RSTAB is last byte - count &= D_FIFO_SIZE-1; + if (count) count--; // RSTAB is last byte + count &= D_FIFO_SIZE - 1; if (count == 0) count = D_FIFO_SIZE; dch_empty_fifo(cs, count); if ((count = cs->rcvidx) > 0) { - cs->rcvidx = 0; + cs->rcvidx = 0; if (!(skb = dev_alloc_skb(count))) printk(KERN_WARNING "HiSax dch_int(): receive out of memory\n"); else { @@ -354,57 +354,57 @@ dch_int(struct IsdnCardState *cs) skb_queue_tail(&cs->rq, skb); } } - } - cs->rcvidx = 0; + } + cs->rcvidx = 0; schedule_event(cs, D_RCVBUFREADY); } - if (istad &0x40) { // RPF + if (istad & 0x40) { // RPF dch_empty_fifo(cs, D_FIFO_SIZE); } - if (istad &0x20) { // RFO - if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): RFO"); - cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES + if (istad & 0x20) { // RFO + if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): RFO"); + cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES } - - if (istad &0x10) { // XPR + + if (istad & 0x10) { // XPR if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) del_timer(&cs->dbusytimer); if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) schedule_event(cs, D_CLEARBUSY); - if (cs->tx_skb) { - if (cs->tx_skb->len) { - dch_fill_fifo(cs); - goto afterXPR; - } - else { - dev_kfree_skb_irq(cs->tx_skb); - cs->tx_skb = NULL; - cs->tx_cnt = 0; - } - } - if ((cs->tx_skb = skb_dequeue(&cs->sq))) { - cs->tx_cnt = 0; - dch_fill_fifo(cs); - } - else { - schedule_event(cs, D_XMTBUFREADY); - } - } - afterXPR: - - if (istad &0x0C) { // XDU or XMR - if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): XDU"); - if (cs->tx_skb) { - skb_push(cs->tx_skb, cs->tx_cnt); // retransmit - cs->tx_cnt = 0; + if (cs->tx_skb) { + if (cs->tx_skb->len) { + dch_fill_fifo(cs); + goto afterXPR; + } + else { + dev_kfree_skb_irq(cs->tx_skb); + cs->tx_skb = NULL; + cs->tx_cnt = 0; + } + } + if ((cs->tx_skb = skb_dequeue(&cs->sq))) { + cs->tx_cnt = 0; + dch_fill_fifo(cs); + } + else { + schedule_event(cs, D_XMTBUFREADY); + } + } +afterXPR: + + if (istad & 0x0C) { // XDU or XMR + if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): XDU"); + if (cs->tx_skb) { + skb_push(cs->tx_skb, cs->tx_cnt); // retransmit + cs->tx_cnt = 0; dch_fill_fifo(cs); } else { printk(KERN_WARNING "HiSax: ISAC XDU no skb\n"); debugl1(cs, "ISAC XDU no skb"); } - } + } } //---------------------------------------------------------- @@ -423,15 +423,15 @@ dch_init(struct IsdnCardState *cs) printk(KERN_INFO "HiSax: IPACX ISDN driver v0.1.0\n"); cs->setstack_d = dch_setstack; - + cs->dbusytimer.function = (void *) dbusy_timer_handler; cs->dbusytimer.data = (long) cs; init_timer(&cs->dbusytimer); - cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD - cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter - cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go - cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel + cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD + cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter + cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go + cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel } @@ -450,55 +450,55 @@ bch_l2l1(struct PStack *st, int pr, void *arg) u_long flags; switch (pr) { - case (PH_DATA | REQUEST): - spin_lock_irqsave(&bcs->cs->lock, flags); - if (bcs->tx_skb) { - skb_queue_tail(&bcs->squeue, skb); - } else { - bcs->tx_skb = skb; - set_bit(BC_FLG_BUSY, &bcs->Flag); - bcs->hw.hscx.count = 0; - bch_fill_fifo(bcs); - } - spin_unlock_irqrestore(&bcs->cs->lock, flags); - break; - case (PH_PULL | INDICATION): - spin_lock_irqsave(&bcs->cs->lock, flags); - if (bcs->tx_skb) { - printk(KERN_WARNING "HiSax bch_l2l1(): this shouldn't happen\n"); - } else { - set_bit(BC_FLG_BUSY, &bcs->Flag); - bcs->tx_skb = skb; - bcs->hw.hscx.count = 0; - bch_fill_fifo(bcs); - } - spin_unlock_irqrestore(&bcs->cs->lock, flags); - break; - case (PH_PULL | REQUEST): - if (!bcs->tx_skb) { - clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); - st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); - } else - set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); - break; - case (PH_ACTIVATE | REQUEST): - spin_lock_irqsave(&bcs->cs->lock, flags); - set_bit(BC_FLG_ACTIV, &bcs->Flag); - bch_mode(bcs, st->l1.mode, st->l1.bc); - spin_unlock_irqrestore(&bcs->cs->lock, flags); - l1_msg_b(st, pr, arg); - break; - case (PH_DEACTIVATE | REQUEST): - l1_msg_b(st, pr, arg); - break; - case (PH_DEACTIVATE | CONFIRM): - spin_lock_irqsave(&bcs->cs->lock, flags); - clear_bit(BC_FLG_ACTIV, &bcs->Flag); - clear_bit(BC_FLG_BUSY, &bcs->Flag); - bch_mode(bcs, 0, st->l1.bc); - spin_unlock_irqrestore(&bcs->cs->lock, flags); - st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL); - break; + case (PH_DATA | REQUEST): + spin_lock_irqsave(&bcs->cs->lock, flags); + if (bcs->tx_skb) { + skb_queue_tail(&bcs->squeue, skb); + } else { + bcs->tx_skb = skb; + set_bit(BC_FLG_BUSY, &bcs->Flag); + bcs->hw.hscx.count = 0; + bch_fill_fifo(bcs); + } + spin_unlock_irqrestore(&bcs->cs->lock, flags); + break; + case (PH_PULL | INDICATION): + spin_lock_irqsave(&bcs->cs->lock, flags); + if (bcs->tx_skb) { + printk(KERN_WARNING "HiSax bch_l2l1(): this shouldn't happen\n"); + } else { + set_bit(BC_FLG_BUSY, &bcs->Flag); + bcs->tx_skb = skb; + bcs->hw.hscx.count = 0; + bch_fill_fifo(bcs); + } + spin_unlock_irqrestore(&bcs->cs->lock, flags); + break; + case (PH_PULL | REQUEST): + if (!bcs->tx_skb) { + clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); + st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); + } else + set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); + break; + case (PH_ACTIVATE | REQUEST): + spin_lock_irqsave(&bcs->cs->lock, flags); + set_bit(BC_FLG_ACTIV, &bcs->Flag); + bch_mode(bcs, st->l1.mode, st->l1.bc); + spin_unlock_irqrestore(&bcs->cs->lock, flags); + l1_msg_b(st, pr, arg); + break; + case (PH_DEACTIVATE | REQUEST): + l1_msg_b(st, pr, arg); + break; + case (PH_DEACTIVATE | CONFIRM): + spin_lock_irqsave(&bcs->cs->lock, flags); + clear_bit(BC_FLG_ACTIV, &bcs->Flag); + clear_bit(BC_FLG_BUSY, &bcs->Flag); + bch_mode(bcs, 0, st->l1.bc); + spin_unlock_irqrestore(&bcs->cs->lock, flags); + st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL); + break; } } @@ -513,28 +513,28 @@ bch_empty_fifo(struct BCState *bcs, int count) int cnt; cs = bcs->cs; - hscx = bcs->hw.hscx.hscx; - if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO)) + hscx = bcs->hw.hscx.hscx; + if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) debugl1(cs, "bch_empty_fifo()"); - // message too large, remove + // message too large, remove if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) { - if (cs->debug &L1_DEB_WARN) + if (cs->debug & L1_DEB_WARN) debugl1(cs, "bch_empty_fifo() incoming packet too large"); - cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC + cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC bcs->hw.hscx.rcvidx = 0; return; } - + ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; cnt = count; - while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB); + while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB); cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC - + ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; bcs->hw.hscx.rcvidx += count; - - if (cs->debug &L1_DEB_HSCX_FIFO) { + + if (cs->debug & L1_DEB_HSCX_FIFO) { char *t = bcs->blog; t += sprintf(t, "bch_empty_fifo() B-%d cnt %d", hscx, count); @@ -554,7 +554,7 @@ bch_fill_fifo(struct BCState *bcs) u_char *ptr, *p, hscx; cs = bcs->cs; - if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO)) + if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) debugl1(cs, "bch_fill_fifo()"); if (!bcs->tx_skb) return; @@ -567,17 +567,17 @@ bch_fill_fifo(struct BCState *bcs) count = B_FIFO_SIZE; } else { count = bcs->tx_skb->len; - } + } cnt = count; - + p = ptr = bcs->tx_skb->data; skb_pull(bcs->tx_skb, count); bcs->tx_cnt -= count; bcs->hw.hscx.count += count; - while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++); + while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++); cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a)); - - if (cs->debug &L1_DEB_HSCX_FIFO) { + + if (cs->debug & L1_DEB_HSCX_FIFO) { char *t = bcs->blog; t += sprintf(t, "chb_fill_fifo() B-%d cnt %d", hscx, count); @@ -600,31 +600,31 @@ bch_int(struct IsdnCardState *cs, u_char hscx) bcs = cs->bcs + hscx; istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB); -//############################################## +//############################################## // printk(KERN_WARNING "bch_int(istab=%02x)\n", istab); -//############################################## +//############################################## if (!test_bit(BC_FLG_INIT, &bcs->Flag)) return; - if (istab &0x80) { // RME + if (istab & 0x80) { // RME rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB); - if ((rstab &0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB) - if (!(rstab &0x80)) - if (cs->debug &L1_DEB_WARN) - debugl1(cs, "bch_int() B-%d: invalid frame", hscx); - if ((rstab &0x40) && (bcs->mode != L1_MODE_NULL)) - if (cs->debug &L1_DEB_WARN) - debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode); - if (!(rstab &0x20)) - if (cs->debug &L1_DEB_WARN) - debugl1(cs, "bch_int() B-%d: CRC error", hscx); - cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC - } - else { // received frame ok - count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) &(B_FIFO_SIZE-1); + if ((rstab & 0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB) + if (!(rstab & 0x80)) + if (cs->debug & L1_DEB_WARN) + debugl1(cs, "bch_int() B-%d: invalid frame", hscx); + if ((rstab & 0x40) && (bcs->mode != L1_MODE_NULL)) + if (cs->debug & L1_DEB_WARN) + debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode); + if (!(rstab & 0x20)) + if (cs->debug & L1_DEB_WARN) + debugl1(cs, "bch_int() B-%d: CRC error", hscx); + cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC + } + else { // received frame ok + count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) & (B_FIFO_SIZE - 1); if (count == 0) count = B_FIFO_SIZE; bch_empty_fifo(bcs, count); if ((count = bcs->hw.hscx.rcvidx - 1) > 0) { - if (cs->debug &L1_DEB_HSCX_FIFO) + if (cs->debug & L1_DEB_HSCX_FIFO) debugl1(cs, "bch_int Frame %d", count); if (!(skb = dev_alloc_skb(count))) printk(KERN_WARNING "HiSax bch_int(): receive frame out of memory\n"); @@ -637,8 +637,8 @@ bch_int(struct IsdnCardState *cs, u_char hscx) bcs->hw.hscx.rcvidx = 0; schedule_event(bcs, B_RCVBUFREADY); } - - if (istab &0x40) { // RPF + + if (istab & 0x40) { // RPF bch_empty_fifo(bcs, B_FIFO_SIZE); if (bcs->mode == L1_MODE_TRANS) { // queue every chunk @@ -653,21 +653,21 @@ bch_int(struct IsdnCardState *cs, u_char hscx) schedule_event(bcs, B_RCVBUFREADY); } } - - if (istab &0x20) { // RFO - if (cs->debug &L1_DEB_WARN) + + if (istab & 0x20) { // RFO + if (cs->debug & L1_DEB_WARN) debugl1(cs, "bch_int() B-%d: RFO error", hscx); cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES } - if (istab &0x10) { // XPR + if (istab & 0x10) { // XPR if (bcs->tx_skb) { if (bcs->tx_skb->len) { bch_fill_fifo(bcs); goto afterXPR; } else { - if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) && - (PACKET_NOACK != bcs->tx_skb->pkt_type)) { + if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) && + (PACKET_NOACK != bcs->tx_skb->pkt_type)) { u_long flags; spin_lock_irqsave(&bcs->aclock, flags); bcs->ackcnt += bcs->hw.hscx.count; @@ -678,7 +678,7 @@ bch_int(struct IsdnCardState *cs, u_char hscx) dev_kfree_skb_irq(bcs->tx_skb); bcs->hw.hscx.count = 0; bcs->tx_skb = NULL; - } + } if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) { bcs->hw.hscx.count = 0; set_bit(BC_FLG_BUSY, &bcs->Flag); @@ -688,22 +688,22 @@ bch_int(struct IsdnCardState *cs, u_char hscx) schedule_event(bcs, B_XMTBUFREADY); } } - afterXPR: +afterXPR: - if (istab &0x04) { // XDU - if (bcs->mode == L1_MODE_TRANS) { + if (istab & 0x04) { // XDU + if (bcs->mode == L1_MODE_TRANS) { bch_fill_fifo(bcs); - } - else { - if (bcs->tx_skb) { // restart transmitting the whole frame - skb_push(bcs->tx_skb, bcs->hw.hscx.count); - bcs->tx_cnt += bcs->hw.hscx.count; - bcs->hw.hscx.count = 0; - } - cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES - if (cs->debug &L1_DEB_WARN) - debugl1(cs, "bch_int() B-%d XDU error", hscx); - } + } + else { + if (bcs->tx_skb) { // restart transmitting the whole frame + skb_push(bcs->tx_skb, bcs->hw.hscx.count); + bcs->tx_cnt += bcs->hw.hscx.count; + bcs->hw.hscx.count = 0; + } + cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES + if (cs->debug & L1_DEB_WARN) + debugl1(cs, "bch_int() B-%d XDU error", hscx); + } } } @@ -715,43 +715,43 @@ bch_mode(struct BCState *bcs, int mode, int bc) struct IsdnCardState *cs = bcs->cs; int hscx = bcs->hw.hscx.hscx; - bc = bc ? 1 : 0; // in case bc is greater than 1 + bc = bc ? 1 : 0; // in case bc is greater than 1 if (cs->debug & L1_DEB_HSCX) debugl1(cs, "mode_bch() switch B-%d mode %d chan %d", hscx, mode, bc); bcs->mode = mode; bcs->channel = bc; - - // map controller to according timeslot - if (!hscx) - { - cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc); - cs->writeisac(cs, IPACX_BCHA_CR, 0x88); - } - else - { - cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc); - cs->writeisac(cs, IPACX_BCHB_CR, 0x88); - } + + // map controller to according timeslot + if (!hscx) + { + cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc); + cs->writeisac(cs, IPACX_BCHA_CR, 0x88); + } + else + { + cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc); + cs->writeisac(cs, IPACX_BCHB_CR, 0x88); + } switch (mode) { - case (L1_MODE_NULL): - cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off - cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj. - cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off - cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments - break; - case (L1_MODE_TRANS): - cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode - cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000 - cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments - cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); - break; - case (L1_MODE_HDLC): - cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0 - cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled - cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments - cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); - break; + case (L1_MODE_NULL): + cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off + cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj. + cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off + cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments + break; + case (L1_MODE_TRANS): + cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode + cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000 + cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments + cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); + break; + case (L1_MODE_HDLC): + cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0 + cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled + cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments + cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); + break; } } @@ -784,13 +784,13 @@ bch_open_state(struct IsdnCardState *cs, struct BCState *bcs) if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) { if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) { printk(KERN_WARNING - "HiSax open_bchstate(): No memory for hscx.rcvbuf\n"); + "HiSax open_bchstate(): No memory for hscx.rcvbuf\n"); clear_bit(BC_FLG_INIT, &bcs->Flag); return (1); } if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) { printk(KERN_WARNING - "HiSax open_bchstate: No memory for bcs->blog\n"); + "HiSax open_bchstate: No memory for bcs->blog\n"); clear_bit(BC_FLG_INIT, &bcs->Flag); kfree(bcs->hw.hscx.rcvbuf); bcs->hw.hscx.rcvbuf = NULL; @@ -842,21 +842,21 @@ bch_init(struct IsdnCardState *cs, int hscx) //---------------------------------------------------------- // Main interrupt handler //---------------------------------------------------------- -void +void interrupt_ipacx(struct IsdnCardState *cs) { u_char ista; - + while ((ista = cs->readisac(cs, IPACX_ISTA))) { -//################################################# +//################################################# // printk(KERN_WARNING "interrupt_ipacx(ista=%02x)\n", ista); -//################################################# - if (ista &0x80) bch_int(cs, 0); // B channel interrupts - if (ista &0x40) bch_int(cs, 1); - - if (ista &0x01) dch_int(cs); // D channel - if (ista &0x10) cic_int(cs); // Layer 1 state - } +//################################################# + if (ista & 0x80) bch_int(cs, 0); // B channel interrupts + if (ista & 0x40) bch_int(cs, 1); + + if (ista & 0x01) dch_int(cs); // D channel + if (ista & 0x10) cic_int(cs); // Layer 1 state + } } //---------------------------------------------------------- @@ -867,17 +867,17 @@ clear_pending_ints(struct IsdnCardState *cs) { int ista; - // all interrupts off - cs->writeisac(cs, IPACX_MASK, 0xff); + // all interrupts off + cs->writeisac(cs, IPACX_MASK, 0xff); cs->writeisac(cs, IPACX_MASKD, 0xff); cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff); cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff); - - ista = cs->readisac(cs, IPACX_ISTA); - if (ista &0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB); - if (ista &0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB); - if (ista &0x10) cs->readisac(cs, IPACX_CIR0); - if (ista &0x01) cs->readisac(cs, IPACX_ISTAD); + + ista = cs->readisac(cs, IPACX_ISTA); + if (ista & 0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB); + if (ista & 0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB); + if (ista & 0x10) cs->readisac(cs, IPACX_CIR0); + if (ista & 0x01) cs->readisac(cs, IPACX_ISTAD); } //---------------------------------------------------------- @@ -887,23 +887,23 @@ clear_pending_ints(struct IsdnCardState *cs) void init_ipacx(struct IsdnCardState *cs, int part) { - if (part &1) { // initialise chip -//################################################## + if (part & 1) { // initialise chip +//################################################## // printk(KERN_INFO "init_ipacx(%x)\n", part); -//################################################## +//################################################## clear_pending_ints(cs); bch_init(cs, 0); bch_init(cs, 1); dch_init(cs); } - if (part &2) { // reenable all interrupts and start chip + if (part & 2) { // reenable all interrupts and start chip cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK); cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK); cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK); cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register // reset HDLC Transmitters/receivers - cs->writeisac(cs, IPACX_CMDRD, 0x41); + cs->writeisac(cs, IPACX_CMDRD, 0x41); cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41); cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41); ph_command(cs, IPACX_CMD_RES); @@ -911,4 +911,3 @@ init_ipacx(struct IsdnCardState *cs, int part) } //----------------- end of file ----------------------- - |