diff options
Diffstat (limited to 'drivers/misc/mei/hw-me.c')
| -rw-r--r-- | drivers/misc/mei/hw-me.c | 170 |
1 files changed, 101 insertions, 69 deletions
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index f8fd503dfbd6..6fb75e62a764 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -25,6 +25,8 @@ #include "hw-me.h" #include "hw-me-regs.h" +#include "mei-trace.h" + /** * mei_me_reg_read - Reads 32bit data from the mei device * @@ -61,45 +63,79 @@ static inline void mei_me_reg_write(const struct mei_me_hw *hw, * * Return: ME_CB_RW register value (u32) */ -static u32 mei_me_mecbrw_read(const struct mei_device *dev) +static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) { return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); } + +/** + * mei_me_hcbww_write - write 32bit data to the host circular buffer + * + * @dev: the device structure + * @data: 32bit data to be written to the host circular buffer + */ +static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) +{ + mei_me_reg_write(to_me_hw(dev), H_CB_WW, data); +} + /** * mei_me_mecsr_read - Reads 32bit data from the ME CSR * - * @hw: the me hardware structure + * @dev: the device structure * * Return: ME_CSR_HA register value (u32) */ -static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw) +static inline u32 mei_me_mecsr_read(const struct mei_device *dev) { - return mei_me_reg_read(hw, ME_CSR_HA); + u32 reg; + + reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); + trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); + + return reg; } /** * mei_hcsr_read - Reads 32bit data from the host CSR * - * @hw: the me hardware structure + * @dev: the device structure * * Return: H_CSR register value (u32) */ -static inline u32 mei_hcsr_read(const struct mei_me_hw *hw) +static inline u32 mei_hcsr_read(const struct mei_device *dev) +{ + u32 reg; + + reg = mei_me_reg_read(to_me_hw(dev), H_CSR); + trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); + + return reg; +} + +/** + * mei_hcsr_write - writes H_CSR register to the mei device + * + * @dev: the device structure + * @reg: new register value + */ +static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) { - return mei_me_reg_read(hw, H_CSR); + trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); + mei_me_reg_write(to_me_hw(dev), H_CSR, reg); } /** * mei_hcsr_set - writes H_CSR register to the mei device, * and ignores the H_IS bit for it is write-one-to-zero. * - * @hw: the me hardware structure - * @hcsr: new register value + * @dev: the device structure + * @reg: new register value */ -static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr) +static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) { - hcsr &= ~H_IS; - mei_me_reg_write(hw, H_CSR, hcsr); + reg &= ~H_IS; + mei_hcsr_write(dev, reg); } /** @@ -141,7 +177,7 @@ static int mei_me_fw_status(struct mei_device *dev, static void mei_me_hw_config(struct mei_device *dev) { struct mei_me_hw *hw = to_me_hw(dev); - u32 hcsr = mei_hcsr_read(to_me_hw(dev)); + u32 hcsr = mei_hcsr_read(dev); /* Doesn't change in runtime */ dev->hbuf_depth = (hcsr & H_CBD) >> 24; @@ -170,11 +206,10 @@ static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) */ static void mei_me_intr_clear(struct mei_device *dev) { - struct mei_me_hw *hw = to_me_hw(dev); - u32 hcsr = mei_hcsr_read(hw); + u32 hcsr = mei_hcsr_read(dev); if ((hcsr & H_IS) == H_IS) - mei_me_reg_write(hw, H_CSR, hcsr); + mei_hcsr_write(dev, hcsr); } /** * mei_me_intr_enable - enables mei device interrupts @@ -183,11 +218,10 @@ static void mei_me_intr_clear(struct mei_device *dev) */ static void mei_me_intr_enable(struct mei_device *dev) { - struct mei_me_hw *hw = to_me_hw(dev); - u32 hcsr = mei_hcsr_read(hw); + u32 hcsr = mei_hcsr_read(dev); hcsr |= H_IE; - mei_hcsr_set(hw, hcsr); + mei_hcsr_set(dev, hcsr); } /** @@ -197,11 +231,10 @@ static void mei_me_intr_enable(struct mei_device *dev) */ static void mei_me_intr_disable(struct mei_device *dev) { - struct mei_me_hw *hw = to_me_hw(dev); - u32 hcsr = mei_hcsr_read(hw); + u32 hcsr = mei_hcsr_read(dev); hcsr &= ~H_IE; - mei_hcsr_set(hw, hcsr); + mei_hcsr_set(dev, hcsr); } /** @@ -211,12 +244,11 @@ static void mei_me_intr_disable(struct mei_device *dev) */ static void mei_me_hw_reset_release(struct mei_device *dev) { - struct mei_me_hw *hw = to_me_hw(dev); - u32 hcsr = mei_hcsr_read(hw); + u32 hcsr = mei_hcsr_read(dev); hcsr |= H_IG; hcsr &= ~H_RST; - mei_hcsr_set(hw, hcsr); + mei_hcsr_set(dev, hcsr); /* complete this write before we set host ready on another CPU */ mmiowb(); @@ -231,8 +263,7 @@ static void mei_me_hw_reset_release(struct mei_device *dev) */ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) { - struct mei_me_hw *hw = to_me_hw(dev); - u32 hcsr = mei_hcsr_read(hw); + u32 hcsr = mei_hcsr_read(dev); /* H_RST may be found lit before reset is started, * for example if preceding reset flow hasn't completed. @@ -242,8 +273,8 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) if ((hcsr & H_RST) == H_RST) { dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); hcsr &= ~H_RST; - mei_hcsr_set(hw, hcsr); - hcsr = mei_hcsr_read(hw); + mei_hcsr_set(dev, hcsr); + hcsr = mei_hcsr_read(dev); } hcsr |= H_RST | H_IG | H_IS; @@ -254,13 +285,13 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) hcsr &= ~H_IE; dev->recvd_hw_ready = false; - mei_me_reg_write(hw, H_CSR, hcsr); + mei_hcsr_write(dev, hcsr); /* * Host reads the H_CSR once to ensure that the * posted write to H_CSR completes. */ - hcsr = mei_hcsr_read(hw); + hcsr = mei_hcsr_read(dev); if ((hcsr & H_RST) == 0) dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); @@ -281,11 +312,10 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) */ static void mei_me_host_set_ready(struct mei_device *dev) { - struct mei_me_hw *hw = to_me_hw(dev); - u32 hcsr = mei_hcsr_read(hw); + u32 hcsr = mei_hcsr_read(dev); hcsr |= H_IE | H_IG | H_RDY; - mei_hcsr_set(hw, hcsr); + mei_hcsr_set(dev, hcsr); } /** @@ -296,8 +326,7 @@ static void mei_me_host_set_ready(struct mei_device *dev) */ static bool mei_me_host_is_ready(struct mei_device *dev) { - struct mei_me_hw *hw = to_me_hw(dev); - u32 hcsr = mei_hcsr_read(hw); + u32 hcsr = mei_hcsr_read(dev); return (hcsr & H_RDY) == H_RDY; } @@ -310,8 +339,7 @@ static bool mei_me_host_is_ready(struct mei_device *dev) */ static bool mei_me_hw_is_ready(struct mei_device *dev) { - struct mei_me_hw *hw = to_me_hw(dev); - u32 mecsr = mei_me_mecsr_read(hw); + u32 mecsr = mei_me_mecsr_read(dev); return (mecsr & ME_RDY_HRA) == ME_RDY_HRA; } @@ -368,11 +396,10 @@ static int mei_me_hw_start(struct mei_device *dev) */ static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) { - struct mei_me_hw *hw = to_me_hw(dev); u32 hcsr; char read_ptr, write_ptr; - hcsr = mei_hcsr_read(hw); + hcsr = mei_hcsr_read(dev); read_ptr = (char) ((hcsr & H_CBRP) >> 8); write_ptr = (char) ((hcsr & H_CBWP) >> 16); @@ -439,7 +466,6 @@ static int mei_me_write_message(struct mei_device *dev, struct mei_msg_hdr *header, unsigned char *buf) { - struct mei_me_hw *hw = to_me_hw(dev); unsigned long rem; unsigned long length = header->length; u32 *reg_buf = (u32 *)buf; @@ -457,21 +483,21 @@ static int mei_me_write_message(struct mei_device *dev, if (empty_slots < 0 || dw_cnt > empty_slots) return -EMSGSIZE; - mei_me_reg_write(hw, H_CB_WW, *((u32 *) header)); + mei_me_hcbww_write(dev, *((u32 *) header)); for (i = 0; i < length / 4; i++) - mei_me_reg_write(hw, H_CB_WW, reg_buf[i]); + mei_me_hcbww_write(dev, reg_buf[i]); rem = length & 0x3; if (rem > 0) { u32 reg = 0; memcpy(®, &buf[length - rem], rem); - mei_me_reg_write(hw, H_CB_WW, reg); + mei_me_hcbww_write(dev, reg); } - hcsr = mei_hcsr_read(hw) | H_IG; - mei_hcsr_set(hw, hcsr); + hcsr = mei_hcsr_read(dev) | H_IG; + mei_hcsr_set(dev, hcsr); if (!mei_me_hw_is_ready(dev)) return -EIO; @@ -487,12 +513,11 @@ static int mei_me_write_message(struct mei_device *dev, */ static int mei_me_count_full_read_slots(struct mei_device *dev) { - struct mei_me_hw *hw = to_me_hw(dev); u32 me_csr; char read_ptr, write_ptr; unsigned char buffer_depth, filled_slots; - me_csr = mei_me_mecsr_read(hw); + me_csr = mei_me_mecsr_read(dev); buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24); read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8); write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16); @@ -518,7 +543,6 @@ static int mei_me_count_full_read_slots(struct mei_device *dev) static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, unsigned long buffer_length) { - struct mei_me_hw *hw = to_me_hw(dev); u32 *reg_buf = (u32 *)buffer; u32 hcsr; @@ -531,49 +555,59 @@ static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, memcpy(reg_buf, ®, buffer_length); } - hcsr = mei_hcsr_read(hw) | H_IG; - mei_hcsr_set(hw, hcsr); + hcsr = mei_hcsr_read(dev) | H_IG; + mei_hcsr_set(dev, hcsr); return 0; } /** - * mei_me_pg_enter - write pg enter register + * mei_me_pg_set - write pg enter register * * @dev: the device structure */ -static void mei_me_pg_enter(struct mei_device *dev) +static void mei_me_pg_set(struct mei_device *dev) { struct mei_me_hw *hw = to_me_hw(dev); - u32 reg = mei_me_reg_read(hw, H_HPG_CSR); + u32 reg; + + reg = mei_me_reg_read(hw, H_HPG_CSR); + trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); reg |= H_HPG_CSR_PGI; + + trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); mei_me_reg_write(hw, H_HPG_CSR, reg); } /** - * mei_me_pg_exit - write pg exit register + * mei_me_pg_unset - write pg exit register * * @dev: the device structure */ -static void mei_me_pg_exit(struct mei_device *dev) +static void mei_me_pg_unset(struct mei_device *dev) { struct mei_me_hw *hw = to_me_hw(dev); - u32 reg = mei_me_reg_read(hw, H_HPG_CSR); + u32 reg; + + reg = mei_me_reg_read(hw, H_HPG_CSR); + trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n"); reg |= H_HPG_CSR_PGIHEXR; + + trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); mei_me_reg_write(hw, H_HPG_CSR, reg); } /** - * mei_me_pg_set_sync - perform pg entry procedure + * mei_me_pg_enter_sync - perform pg entry procedure * * @dev: the device structure * * Return: 0 on success an error code otherwise */ -int mei_me_pg_set_sync(struct mei_device *dev) +int mei_me_pg_enter_sync(struct mei_device *dev) { struct mei_me_hw *hw = to_me_hw(dev); unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); @@ -591,7 +625,7 @@ int mei_me_pg_set_sync(struct mei_device *dev) mutex_lock(&dev->device_lock); if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { - mei_me_pg_enter(dev); + mei_me_pg_set(dev); ret = 0; } else { ret = -ETIME; @@ -604,13 +638,13 @@ int mei_me_pg_set_sync(struct mei_device *dev) } /** - * mei_me_pg_unset_sync - perform pg exit procedure + * mei_me_pg_exit_sync - perform pg exit procedure * * @dev: the device structure * * Return: 0 on success an error code otherwise */ -int mei_me_pg_unset_sync(struct mei_device *dev) +int mei_me_pg_exit_sync(struct mei_device *dev) { struct mei_me_hw *hw = to_me_hw(dev); unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); @@ -621,7 +655,7 @@ int mei_me_pg_unset_sync(struct mei_device *dev) dev->pg_event = MEI_PG_EVENT_WAIT; - mei_me_pg_exit(dev); + mei_me_pg_unset(dev); mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, @@ -649,8 +683,7 @@ reply: */ static bool mei_me_pg_is_enabled(struct mei_device *dev) { - struct mei_me_hw *hw = to_me_hw(dev); - u32 reg = mei_me_reg_read(hw, ME_CSR_HA); + u32 reg = mei_me_mecsr_read(dev); if ((reg & ME_PGIC_HRA) == 0) goto notsupported; @@ -683,14 +716,13 @@ notsupported: irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id) { struct mei_device *dev = (struct mei_device *) dev_id; - struct mei_me_hw *hw = to_me_hw(dev); - u32 csr_reg = mei_hcsr_read(hw); + u32 hcsr = mei_hcsr_read(dev); - if ((csr_reg & H_IS) != H_IS) + if ((hcsr & H_IS) != H_IS) return IRQ_NONE; /* clear H_IS bit in H_CSR */ - mei_me_reg_write(hw, H_CSR, csr_reg); + mei_hcsr_write(dev, hcsr); return IRQ_WAKE_THREAD; } |