diff options
Diffstat (limited to 'drivers/net/ipa/gsi_reg.h')
| -rw-r--r-- | drivers/net/ipa/gsi_reg.h | 59 |
1 files changed, 17 insertions, 42 deletions
diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index acc9e744c67d..8e0e9350c383 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -258,6 +258,11 @@ GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \ (0x0001f080 + 0x4000 * (ee)) +#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ + GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) +#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ + (0x0001f088 + 0x4000 * (ee)) +/* The masks below are used for the TYPE_IRQ and TYPE_IRQ_MASK registers */ #define CH_CTRL_FMASK GENMASK(0, 0) #define EV_CTRL_FMASK GENMASK(1, 1) #define GLOB_EE_FMASK GENMASK(2, 2) @@ -265,18 +270,6 @@ #define INTER_EE_CH_CTRL_FMASK GENMASK(4, 4) #define INTER_EE_EV_CTRL_FMASK GENMASK(5, 5) #define GENERAL_FMASK GENMASK(6, 6) - -#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ - GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ - (0x0001f088 + 0x4000 * (ee)) -#define MSK_CH_CTRL_FMASK GENMASK(0, 0) -#define MSK_EV_CTRL_FMASK GENMASK(1, 1) -#define MSK_GLOB_EE_FMASK GENMASK(2, 2) -#define MSK_IEOB_FMASK GENMASK(3, 3) -#define MSK_INTER_EE_CH_CTRL_FMASK GENMASK(4, 4) -#define MSK_INTER_EE_EV_CTRL_FMASK GENMASK(5, 5) -#define MSK_GENERAL_FMASK GENMASK(6, 6) #define GSI_CNTXT_TYPE_IRQ_MSK_ALL GENMASK(6, 0) #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ @@ -328,57 +321,39 @@ GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \ (0x0001f100 + 0x4000 * (ee)) -#define ERROR_INT_FMASK GENMASK(0, 0) -#define GP_INT1_FMASK GENMASK(1, 1) -#define GP_INT2_FMASK GENMASK(2, 2) -#define GP_INT3_FMASK GENMASK(3, 3) - #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \ GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \ (0x0001f108 + 0x4000 * (ee)) -#define EN_ERROR_INT_FMASK GENMASK(0, 0) -#define EN_GP_INT1_FMASK GENMASK(1, 1) -#define EN_GP_INT2_FMASK GENMASK(2, 2) -#define EN_GP_INT3_FMASK GENMASK(3, 3) -#define GSI_CNTXT_GLOB_IRQ_ALL GENMASK(3, 0) - #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \ GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \ (0x0001f110 + 0x4000 * (ee)) -#define CLR_ERROR_INT_FMASK GENMASK(0, 0) -#define CLR_GP_INT1_FMASK GENMASK(1, 1) -#define CLR_GP_INT2_FMASK GENMASK(2, 2) -#define CLR_GP_INT3_FMASK GENMASK(3, 3) +/* The masks below are used for the general IRQ STTS, EN, and CLR registers */ +#define ERROR_INT_FMASK GENMASK(0, 0) +#define GP_INT1_FMASK GENMASK(1, 1) +#define GP_INT2_FMASK GENMASK(2, 2) +#define GP_INT3_FMASK GENMASK(3, 3) +#define GSI_CNTXT_GLOB_IRQ_ALL GENMASK(3, 0) #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \ (0x0001f118 + 0x4000 * (ee)) -#define BREAK_POINT_FMASK GENMASK(0, 0) -#define BUS_ERROR_FMASK GENMASK(1, 1) -#define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) -#define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) - #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \ (0x0001f120 + 0x4000 * (ee)) -#define EN_BREAK_POINT_FMASK GENMASK(0, 0) -#define EN_BUS_ERROR_FMASK GENMASK(1, 1) -#define EN_CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) -#define EN_MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) -#define GSI_CNTXT_GSI_IRQ_ALL GENMASK(3, 0) - #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \ (0x0001f128 + 0x4000 * (ee)) -#define CLR_BREAK_POINT_FMASK GENMASK(0, 0) -#define CLR_BUS_ERROR_FMASK GENMASK(1, 1) -#define CLR_CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) -#define CLR_MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) +/* The masks below are used for the general IRQ STTS, EN, and CLR registers */ +#define BREAK_POINT_FMASK GENMASK(0, 0) +#define BUS_ERROR_FMASK GENMASK(1, 1) +#define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) +#define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) +#define GSI_CNTXT_GSI_IRQ_ALL GENMASK(3, 0) #define GSI_CNTXT_INTSET_OFFSET \ GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP) |