diff options
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-spear13xx.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-spear13xx.c | 46 |
1 files changed, 20 insertions, 26 deletions
diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c index 800c34a60a33..ebbaa06fc8ab 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -66,32 +66,10 @@ struct pcie_app_reg { #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev) -static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) +static int spear13xx_pcie_start_link(struct dw_pcie *pci) { - struct dw_pcie *pci = spear13xx_pcie->pci; - struct pcie_port *pp = &pci->pp; + struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci); struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; - u32 val; - u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - - if (dw_pcie_link_up(pci)) { - dev_err(pci->dev, "link already up\n"); - return 0; - } - - dw_pcie_setup_rc(pp); - - /* - * this controller support only 128 bytes read size, however its - * default value in capability register is 512 bytes. So force - * it to 128 here. - */ - val = dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL); - val &= ~PCI_EXP_DEVCTL_READRQ; - dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL, val); - - dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, 0x104A); - dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, 0xCD80); /* enable ltssm */ writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID) @@ -99,7 +77,7 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) | ((u32)1 << REG_TRANSLATION_ENABLE), &app_reg->app_ctrl_0); - return dw_pcie_wait_for_link(pci); + return 0; } static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg) @@ -151,10 +129,25 @@ static int spear13xx_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci); + u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; spear13xx_pcie->app_base = pci->dbi_base + 0x2000; - spear13xx_pcie_establish_link(spear13xx_pcie); + dw_pcie_setup_rc(pp); + + /* + * this controller support only 128 bytes read size, however its + * default value in capability register is 512 bytes. So force + * it to 128 here. + */ + val = dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL); + val &= ~PCI_EXP_DEVCTL_READRQ; + dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL, val); + + dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, 0x104A); + dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, 0xCD80); + spear13xx_pcie_enable_interrupts(spear13xx_pcie); return 0; @@ -198,6 +191,7 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie, static const struct dw_pcie_ops dw_pcie_ops = { .link_up = spear13xx_pcie_link_up, + .start_link = spear13xx_pcie_start_link, }; static int spear13xx_pcie_probe(struct platform_device *pdev) |