diff options
Diffstat (limited to 'drivers/pci/host/pcie-designware.c')
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 12afce19890b..1f6bd6d42874 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -115,12 +115,12 @@ int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) return PCIBIOS_SUCCESSFUL; } -static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val) +static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) { if (pp->ops->readl_rc) - pp->ops->readl_rc(pp, pp->dbi_base + reg, val); - else - *val = readl(pp->dbi_base + reg); + return pp->ops->readl_rc(pp, pp->dbi_base + reg); + + return readl(pp->dbi_base + reg); } static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) @@ -169,7 +169,7 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, * Make sure ATU enable takes effect before any subsequent config * and I/O accesses. */ - dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val); + val = dw_pcie_readl_rc(pp, PCIE_ATU_CR2); } static struct irq_chip dw_msi_irq_chip = { @@ -720,7 +720,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) u32 val; /* set the number of lanes */ - dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); + val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL); val &= ~PORT_LINK_MODE_MASK; switch (pp->lanes) { case 1: @@ -742,7 +742,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); /* set link width speed control register */ - dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val); + val = dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL); val &= ~PORT_LOGIC_LINK_WIDTH_MASK; switch (pp->lanes) { case 1: @@ -765,19 +765,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); /* setup interrupt pins */ - dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); + val = dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE); val &= 0xffff00ff; val |= 0x00000100; dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); /* setup bus numbers */ - dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val); + val = dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS); val &= 0xff000000; val |= 0x00010100; dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); /* setup command register */ - dw_pcie_readl_rc(pp, PCI_COMMAND, &val); + val = dw_pcie_readl_rc(pp, PCI_COMMAND); val &= 0xffff0000; val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; |