diff options
Diffstat (limited to 'drivers/pinctrl/pinctrl-single.c')
| -rw-r--r-- | drivers/pinctrl/pinctrl-single.c | 217 |
1 files changed, 136 insertions, 81 deletions
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index bfdf720db270..a5a0392ab817 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -31,12 +31,10 @@ #include <linux/platform_data/pinctrl-single.h> #include "core.h" +#include "devicetree.h" #include "pinconf.h" #define DRIVER_NAME "pinctrl-single" -#define PCS_MUX_PINS_NAME "pinctrl-single,pins" -#define PCS_MUX_BITS_NAME "pinctrl-single,bits" -#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3) #define PCS_OFF_DISABLED ~0U /** @@ -142,20 +140,6 @@ struct pcs_data { }; /** - * struct pcs_name - register name for a pin - * @name: name of the pinctrl register - * - * REVISIT: We may want to make names optional in the pinctrl - * framework as some drivers may not care about pin names to - * avoid kernel bloat. The pin names can be deciphered by user - * space tools using debugfs based on the register address and - * SoC packaging information. - */ -struct pcs_name { - char name[PCS_REG_NAME_LEN]; -}; - -/** * struct pcs_soc_data - SoC specific settings * @flags: initial SoC specific PCS_FEAT_xxx values * @irq: optional interrupt for the controller @@ -177,8 +161,11 @@ struct pcs_soc_data { * @base: virtual address of the controller * @size: size of the ioremapped area * @dev: device entry + * @np: device tree node * @pctl: pin controller device * @flags: mask of PCS_FEAT_xxx values + * @missing_nr_pinctrl_cells: for legacy binding, may go away + * @socdata: soc specific data * @lock: spinlock for register access * @mutex: mutex protecting the lists * @width: bits per mux register @@ -186,8 +173,8 @@ struct pcs_soc_data { * @fshift: function register shift * @foff: value to turn mux off * @fmax: max number of functions in fmask - * @bits_per_pin:number of bits per pin - * @names: array of register names for pins + * @bits_per_mux: number of bits per mux + * @bits_per_pin: number of bits per pin * @pins: physical pins on the SoC * @pgtree: pingroup index radix tree * @ftree: function index radix tree @@ -208,11 +195,13 @@ struct pcs_device { void __iomem *base; unsigned size; struct device *dev; + struct device_node *np; struct pinctrl_dev *pctl; unsigned flags; #define PCS_QUIRK_SHARED_IRQ (1 << 2) #define PCS_FEAT_IRQ (1 << 1) #define PCS_FEAT_PINCONF (1 << 0) + struct property *missing_nr_pinctrl_cells; struct pcs_soc_data socdata; raw_spinlock_t lock; struct mutex mutex; @@ -223,7 +212,6 @@ struct pcs_device { unsigned fmax; bool bits_per_mux; unsigned bits_per_pin; - struct pcs_name *names; struct pcs_data pins; struct radix_tree_root pgtree; struct radix_tree_root ftree; @@ -354,13 +342,17 @@ static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, { struct pcs_device *pcs; unsigned val, mux_bytes; + unsigned long offset; + size_t pa; pcs = pinctrl_dev_get_drvdata(pctldev); mux_bytes = pcs->width / BITS_PER_BYTE; - val = pcs->read(pcs->base + pin * mux_bytes); + offset = pin * mux_bytes; + val = pcs->read(pcs->base + offset); + pa = pcs->res->start + offset; - seq_printf(s, "%08x %s " , val, DRIVER_NAME); + seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME); } static void pcs_dt_free_map(struct pinctrl_dev *pctldev, @@ -763,7 +755,6 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, { struct pcs_soc_data *pcs_soc = &pcs->socdata; struct pinctrl_pin_desc *pin; - struct pcs_name *pn; int i; i = pcs->pins.cur; @@ -786,10 +777,6 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, } pin = &pcs->pins.pa[i]; - pn = &pcs->names[i]; - sprintf(pn->name, "%lx.%u", - (unsigned long)pcs->res->start + offset, pin_pos); - pin->name = pn->name; pin->number = i; pcs->pins.cur++; @@ -827,12 +814,6 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) if (!pcs->pins.pa) return -ENOMEM; - pcs->names = devm_kzalloc(pcs->dev, - sizeof(struct pcs_name) * nr_pins, - GFP_KERNEL); - if (!pcs->names) - return -ENOMEM; - pcs->desc.pins = pcs->pins.pa; pcs->desc.npins = nr_pins; @@ -1146,21 +1127,17 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, unsigned *num_maps, const char **pgnames) { + const char *name = "pinctrl-single,pins"; struct pcs_func_vals *vals; - const __be32 *mux; - int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int rows, *pins, found = 0, res = -ENOMEM, i; struct pcs_function *function; - mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); - if ((!mux) || (size < sizeof(*mux) * 2)) { - dev_err(pcs->dev, "bad data for mux %s\n", - np->name); + rows = pinctrl_count_index_with_args(np, name); + if (rows <= 0) { + dev_err(pcs->dev, "Ivalid number of rows: %d\n", rows); return -EINVAL; } - size /= sizeof(*mux); /* Number of elements in array */ - rows = size / 2; - vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); if (!vals) return -ENOMEM; @@ -1169,14 +1146,28 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, if (!pins) goto free_vals; - while (index < size) { - unsigned offset, val; + for (i = 0; i < rows; i++) { + struct of_phandle_args pinctrl_spec; + unsigned int offset; int pin; - offset = be32_to_cpup(mux + index++); - val = be32_to_cpup(mux + index++); + res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec); + if (res) + return res; + + if (pinctrl_spec.args_count < 2) { + dev_err(pcs->dev, "invalid args_count for spec: %i\n", + pinctrl_spec.args_count); + break; + } + + /* Index plus one value cell */ + offset = pinctrl_spec.args[0]; vals[found].reg = pcs->base + offset; - vals[found].val = val; + vals[found].val = pinctrl_spec.args[1]; + + dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n", + pinctrl_spec.np->name, offset, pinctrl_spec.args[1]); pin = pcs_get_pin_by_offset(pcs, offset); if (pin < 0) { @@ -1190,8 +1181,10 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, pgnames[0] = np->name; function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); - if (!function) + if (!function) { + res = -ENOMEM; goto free_pins; + } res = pcs_add_pingroup(pcs, np, np->name, pins, found); if (res < 0) @@ -1226,36 +1219,24 @@ free_vals: return res; } -#define PARAMS_FOR_BITS_PER_MUX 3 - static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, struct device_node *np, struct pinctrl_map **map, unsigned *num_maps, const char **pgnames) { + const char *name = "pinctrl-single,bits"; struct pcs_func_vals *vals; - const __be32 *mux; - int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int rows, *pins, found = 0, res = -ENOMEM, i; int npins_in_row; struct pcs_function *function; - mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); - - if (!mux) { - dev_err(pcs->dev, "no valid property for %s\n", np->name); - return -EINVAL; - } - - if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) { - dev_err(pcs->dev, "bad data for %s\n", np->name); + rows = pinctrl_count_index_with_args(np, name); + if (rows <= 0) { + dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); return -EINVAL; } - /* Number of elements in array */ - size /= sizeof(*mux); - - rows = size / PARAMS_FOR_BITS_PER_MUX; npins_in_row = pcs->width / pcs->bits_per_pin; vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row, @@ -1268,15 +1249,30 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, if (!pins) goto free_vals; - while (index < size) { + for (i = 0; i < rows; i++) { + struct of_phandle_args pinctrl_spec; unsigned offset, val; unsigned mask, bit_pos, val_pos, mask_pos, submask; unsigned pin_num_from_lsb; int pin; - offset = be32_to_cpup(mux + index++); - val = be32_to_cpup(mux + index++); - mask = be32_to_cpup(mux + index++); + res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec); + if (res) + return res; + + if (pinctrl_spec.args_count < 3) { + dev_err(pcs->dev, "invalid args_count for spec: %i\n", + pinctrl_spec.args_count); + break; + } + + /* Index plus two value cells */ + offset = pinctrl_spec.args[0]; + val = pinctrl_spec.args[1]; + mask = pinctrl_spec.args[2]; + + dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n", + pinctrl_spec.np->name, offset, val, mask); /* Parse pins in each row from LSB */ while (mask) { @@ -1319,8 +1315,10 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, pgnames[0] = np->name; function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); - if (!function) + if (!function) { + res = -ENOMEM; goto free_pins; + } res = pcs_add_pingroup(pcs, np, np->name, pins, found); if (res < 0) @@ -1494,17 +1492,12 @@ static void pcs_free_resources(struct pcs_device *pcs) pinctrl_unregister(pcs->pctl); pcs_free_funcs(pcs); pcs_free_pingroups(pcs); +#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE) + if (pcs->missing_nr_pinctrl_cells) + of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); +#endif } -#define PCS_GET_PROP_U32(name, reg, err) \ - do { \ - ret = of_property_read_u32(np, name, reg); \ - if (ret) { \ - dev_err(pcs->dev, err); \ - return ret; \ - } \ - } while (0); - static const struct of_device_id pcs_of_match[]; static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) @@ -1820,6 +1813,55 @@ static int pinctrl_single_resume(struct platform_device *pdev) } #endif +/** + * pcs_quirk_missing_pinctrl_cells - handle legacy binding + * @pcs: pinctrl driver instance + * @np: device tree node + * @cells: number of cells + * + * Handle legacy binding with no #pinctrl-cells. This should be + * always two pinctrl-single,bit-per-mux and one for others. + * At some point we may want to consider removing this. + */ +static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs, + struct device_node *np, + int cells) +{ + struct property *p; + const char *name = "#pinctrl-cells"; + int error; + u32 val; + + error = of_property_read_u32(np, name, &val); + if (!error) + return 0; + + dev_warn(pcs->dev, "please update dts to use %s = <%i>\n", + name, cells); + + p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + + p->length = sizeof(__be32); + p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL); + if (!p->value) + return -ENOMEM; + *(__be32 *)p->value = cpu_to_be32(cells); + + p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL); + if (!p->name) + return -ENOMEM; + + pcs->missing_nr_pinctrl_cells = p; + +#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE) + error = of_add_property(np, pcs->missing_nr_pinctrl_cells); +#endif + + return error; +} + static int pcs_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -1840,6 +1882,7 @@ static int pcs_probe(struct platform_device *pdev) return -ENOMEM; } pcs->dev = &pdev->dev; + pcs->np = np; raw_spin_lock_init(&pcs->lock); mutex_init(&pcs->mutex); INIT_LIST_HEAD(&pcs->pingroups); @@ -1849,8 +1892,13 @@ static int pcs_probe(struct platform_device *pdev) pcs->flags = soc->flags; memcpy(&pcs->socdata, soc, sizeof(*soc)); - PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, - "register width not specified\n"); + ret = of_property_read_u32(np, "pinctrl-single,register-width", + &pcs->width); + if (ret) { + dev_err(pcs->dev, "register width not specified\n"); + + return ret; + } ret = of_property_read_u32(np, "pinctrl-single,function-mask", &pcs->fmask); @@ -1871,6 +1919,13 @@ static int pcs_probe(struct platform_device *pdev) pcs->bits_per_mux = of_property_read_bool(np, "pinctrl-single,bit-per-mux"); + ret = pcs_quirk_missing_pinctrl_cells(pcs, np, + pcs->bits_per_mux ? 2 : 1); + if (ret) { + dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n"); + + return ret; + } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { |