diff options
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a7778.c')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 125 |
1 files changed, 55 insertions, 70 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index 49fe52d35f30..24866a5958ae 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -22,28 +22,17 @@ #define PORT_GP_PUP_1(bank, pin, fn, sfx) \ PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) -#define PORT_GP_PUP_27(bank, fn, sfx) \ - PORT_GP_PUP_1(bank, 0, fn, sfx), PORT_GP_PUP_1(bank, 1, fn, sfx), \ - PORT_GP_PUP_1(bank, 2, fn, sfx), PORT_GP_PUP_1(bank, 3, fn, sfx), \ - PORT_GP_PUP_1(bank, 4, fn, sfx), PORT_GP_PUP_1(bank, 5, fn, sfx), \ - PORT_GP_PUP_1(bank, 6, fn, sfx), PORT_GP_PUP_1(bank, 7, fn, sfx), \ - PORT_GP_PUP_1(bank, 8, fn, sfx), PORT_GP_PUP_1(bank, 9, fn, sfx), \ - PORT_GP_PUP_1(bank, 10, fn, sfx), PORT_GP_PUP_1(bank, 11, fn, sfx), \ - PORT_GP_PUP_1(bank, 12, fn, sfx), PORT_GP_PUP_1(bank, 13, fn, sfx), \ - PORT_GP_PUP_1(bank, 14, fn, sfx), PORT_GP_PUP_1(bank, 15, fn, sfx), \ - PORT_GP_PUP_1(bank, 16, fn, sfx), PORT_GP_PUP_1(bank, 17, fn, sfx), \ - PORT_GP_PUP_1(bank, 18, fn, sfx), PORT_GP_PUP_1(bank, 19, fn, sfx), \ - PORT_GP_PUP_1(bank, 20, fn, sfx), PORT_GP_PUP_1(bank, 21, fn, sfx), \ - PORT_GP_PUP_1(bank, 22, fn, sfx), PORT_GP_PUP_1(bank, 23, fn, sfx), \ - PORT_GP_PUP_1(bank, 24, fn, sfx), PORT_GP_PUP_1(bank, 25, fn, sfx), \ - PORT_GP_PUP_1(bank, 26, fn, sfx) - -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_PUP_27(4, fn, sfx) + PORT_GP_CFG_27(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP(CLKOUT, "B25", fn), \ + PIN_NOGP(CS0, "A20", fn), \ + PIN_NOGP(CS1_A26, "C20", fn) enum { PINMUX_RESERVED = 0, @@ -1253,19 +1242,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C), }; -/* Pin numbers for pins without a corresponding GPIO port number are computed - * from the row and column numbers with a 1000 offset to avoid collisions with - * GPIO port numbers. +/* + * Pins not associated with a GPIO port. */ -#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* Pins not associated with a GPIO port */ - SH_PFC_PIN_NAMED(3, 20, C20), - SH_PFC_PIN_NAMED(1, 20, A20), - SH_PFC_PIN_NAMED(2, 25, B25), + PINMUX_NOGP_ALL(), }; /* - macro */ @@ -1400,7 +1387,7 @@ HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A, HSPI_RX1_A, HSPI_TX1_A); HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26), - PIN_NUMBER(1, 20), PIN_NUMBER(2, 25)); + PIN_CS0, PIN_CLKOUT); HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B, HSPI_RX1_B, HSPI_TX1_B); @@ -1426,7 +1413,7 @@ I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B); /* - I2C2 ------------------------------------------------------------------ */ -I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); +I2C_PFC_PIN(i2c2_a, PIN_CS1_A26, RCAR_GP_PIN(1, 3)); I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A); I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B); @@ -1516,7 +1503,7 @@ SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E); SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9)); SCIF_PFC_CLK(scif2_clk_a, SCK2_A); -SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20)); +SCIF_PFC_PIN(scif2_clk_b, PIN_CS1_A26); SCIF_PFC_CLK(scif2_clk_b, SCK2_B); SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12)); SCIF_PFC_CLK(scif2_clk_c, SCK2_C); @@ -1631,7 +1618,7 @@ SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10)); SSI_PFC_DATA(ssi0_data, SSI_SDATA0); SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21)); SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A); -SSI_PFC_PINS(ssi1_b_ctrl, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); +SSI_PFC_PINS(ssi1_b_ctrl, PIN_CS1_A26, RCAR_GP_PIN(1, 3)); SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B); SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9)); SSI_PFC_DATA(ssi1_data, SSI_SDATA1); @@ -2921,8 +2908,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -#define PIN_NONE U16_MAX - static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) { [ 0] = RCAR_GP_PIN(0, 6), /* A0 */ @@ -2969,28 +2954,28 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 7] = RCAR_GP_PIN(1, 10), /* DACK0 */ [ 8] = RCAR_GP_PIN(1, 12), /* IRQ0 */ [ 9] = RCAR_GP_PIN(1, 13), /* IRQ1 */ - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, } }, { PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) { [ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */ @@ -3112,21 +3097,21 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [14] = RCAR_GP_PIN(4, 20), /* ETH_MAGIC */ [15] = RCAR_GP_PIN(4, 25), /* AVS1 */ [16] = RCAR_GP_PIN(4, 26), /* AVS2 */ - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ }, }; 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