diff options
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-sh7786.c')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-sh7786.c | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c index cc2657c4f85c..4903bc95a835 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -627,7 +627,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) { + { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2, GROUP( PA7_FN, PA7_OUT, PA7_IN, 0, PA6_FN, PA6_OUT, PA6_IN, 0, PA5_FN, PA5_OUT, PA5_IN, 0, @@ -635,9 +635,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PA3_FN, PA3_OUT, PA3_IN, 0, PA2_FN, PA2_OUT, PA2_IN, 0, PA1_FN, PA1_OUT, PA1_IN, 0, - PA0_FN, PA0_OUT, PA0_IN, 0 } + PA0_FN, PA0_OUT, PA0_IN, 0 )) }, - { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) { + { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2, GROUP( PB7_FN, PB7_OUT, PB7_IN, 0, PB6_FN, PB6_OUT, PB6_IN, 0, PB5_FN, PB5_OUT, PB5_IN, 0, @@ -645,9 +645,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PB3_FN, PB3_OUT, PB3_IN, 0, PB2_FN, PB2_OUT, PB2_IN, 0, PB1_FN, PB1_OUT, PB1_IN, 0, - PB0_FN, PB0_OUT, PB0_IN, 0 } + PB0_FN, PB0_OUT, PB0_IN, 0 )) }, - { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) { + { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2, GROUP( PC7_FN, PC7_OUT, PC7_IN, 0, PC6_FN, PC6_OUT, PC6_IN, 0, PC5_FN, PC5_OUT, PC5_IN, 0, @@ -655,9 +655,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PC3_FN, PC3_OUT, PC3_IN, 0, PC2_FN, PC2_OUT, PC2_IN, 0, PC1_FN, PC1_OUT, PC1_IN, 0, - PC0_FN, PC0_OUT, PC0_IN, 0 } + PC0_FN, PC0_OUT, PC0_IN, 0 )) }, - { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) { + { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2, GROUP( PD7_FN, PD7_OUT, PD7_IN, 0, PD6_FN, PD6_OUT, PD6_IN, 0, PD5_FN, PD5_OUT, PD5_IN, 0, @@ -665,9 +665,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PD3_FN, PD3_OUT, PD3_IN, 0, PD2_FN, PD2_OUT, PD2_IN, 0, PD1_FN, PD1_OUT, PD1_IN, 0, - PD0_FN, PD0_OUT, PD0_IN, 0 } + PD0_FN, PD0_OUT, PD0_IN, 0 )) }, - { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) { + { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2, GROUP( PE7_FN, PE7_OUT, PE7_IN, 0, PE6_FN, PE6_OUT, PE6_IN, 0, 0, 0, 0, 0, @@ -675,9 +675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, - { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) { + { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2, GROUP( PF7_FN, PF7_OUT, PF7_IN, 0, PF6_FN, PF6_OUT, PF6_IN, 0, PF5_FN, PF5_OUT, PF5_IN, 0, @@ -685,9 +685,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PF3_FN, PF3_OUT, PF3_IN, 0, PF2_FN, PF2_OUT, PF2_IN, 0, PF1_FN, PF1_OUT, PF1_IN, 0, - PF0_FN, PF0_OUT, PF0_IN, 0 } + PF0_FN, PF0_OUT, PF0_IN, 0 )) }, - { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) { + { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2, GROUP( PG7_FN, PG7_OUT, PG7_IN, 0, PG6_FN, PG6_OUT, PG6_IN, 0, PG5_FN, PG5_OUT, PG5_IN, 0, @@ -695,9 +695,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, - { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) { + { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2, GROUP( PH7_FN, PH7_OUT, PH7_IN, 0, PH6_FN, PH6_OUT, PH6_IN, 0, PH5_FN, PH5_OUT, PH5_IN, 0, @@ -705,9 +705,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PH3_FN, PH3_OUT, PH3_IN, 0, PH2_FN, PH2_OUT, PH2_IN, 0, PH1_FN, PH1_OUT, PH1_IN, 0, - PH0_FN, PH0_OUT, PH0_IN, 0 } + PH0_FN, PH0_OUT, PH0_IN, 0 )) }, - { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) { + { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2, GROUP( PJ7_FN, PJ7_OUT, PJ7_IN, 0, PJ6_FN, PJ6_OUT, PJ6_IN, 0, PJ5_FN, PJ5_OUT, PJ5_IN, 0, @@ -715,9 +715,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PJ3_FN, PJ3_OUT, PJ3_IN, 0, PJ2_FN, PJ2_OUT, PJ2_IN, 0, PJ1_FN, PJ1_OUT, PJ1_IN, 0, - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, - { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) { + { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1, GROUP( 0, 0, P1MSEL14_0, P1MSEL14_1, P1MSEL13_0, P1MSEL13_1, @@ -733,9 +733,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { P1MSEL3_0, P1MSEL3_1, P1MSEL2_0, P1MSEL2_1, P1MSEL1_0, P1MSEL1_1, - P1MSEL0_0, P1MSEL0_1 } + P1MSEL0_0, P1MSEL0_1 )) }, - { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) { + { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1, GROUP( P2MSEL15_0, P2MSEL15_1, P2MSEL14_0, P2MSEL14_1, P2MSEL13_0, P2MSEL13_1, @@ -751,7 +751,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { P2MSEL3_0, P2MSEL3_1, P2MSEL2_0, P2MSEL2_1, P2MSEL1_0, P2MSEL1_1, - P2MSEL0_0, P2MSEL0_1 } + P2MSEL0_0, P2MSEL0_1 )) }, {} }; |