diff options
Diffstat (limited to 'drivers/pinctrl')
25 files changed, 924 insertions, 190 deletions
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 5ee61a470016..c0fe6091566a 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -851,7 +851,9 @@ static struct pinctrl *create_pinctrl(struct device *dev) kref_init(&p->users); /* Add the pinctrl handle to the global list */ + mutex_lock(&pinctrl_list_mutex); list_add_tail(&p->node, &pinctrl_list); + mutex_unlock(&pinctrl_list_mutex); return p; } @@ -1642,8 +1644,10 @@ static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev) device_root, pctldev, &pinctrl_groups_ops); debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO, device_root, pctldev, &pinctrl_gpioranges_ops); - pinmux_init_device_debugfs(device_root, pctldev); - pinconf_init_device_debugfs(device_root, pctldev); + if (pctldev->desc->pmxops) + pinmux_init_device_debugfs(device_root, pctldev); + if (pctldev->desc->confops) + pinconf_init_device_debugfs(device_root, pctldev); } static void pinctrl_remove_device_debugfs(struct pinctrl_dev *pctldev) diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 340fb4e6c600..eda13de2e7c0 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -186,7 +186,9 @@ int pinctrl_dt_to_map(struct pinctrl *p) /* CONFIG_OF enabled, p->dev not instantiated from DT */ if (!np) { - dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n"); + if (of_have_populated_dt()) + dev_dbg(p->dev, + "no of_node; not parsing pinctrl DT\n"); return 0; } diff --git a/drivers/pinctrl/pinctrl-adi2-bf54x.c b/drivers/pinctrl/pinctrl-adi2-bf54x.c index ea9d9ab9cda1..008a29e92e56 100644 --- a/drivers/pinctrl/pinctrl-adi2-bf54x.c +++ b/drivers/pinctrl/pinctrl-adi2-bf54x.c @@ -309,39 +309,6 @@ static const unsigned keys_8x8_pins[] = { GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, }; -static const struct adi_pin_group adi_pin_groups[] = { - ADI_PIN_GROUP("uart0grp", uart0_pins), - ADI_PIN_GROUP("uart1grp", uart1_pins), - ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins), - ADI_PIN_GROUP("uart2grp", uart2_pins), - ADI_PIN_GROUP("uart3grp", uart3_pins), - ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins), - ADI_PIN_GROUP("rsi0grp", rsi0_pins), - ADI_PIN_GROUP("spi0grp", spi0_pins), - ADI_PIN_GROUP("spi1grp", spi1_pins), - ADI_PIN_GROUP("twi0grp", twi0_pins), - ADI_PIN_GROUP("twi1grp", twi1_pins), - ADI_PIN_GROUP("rotarygrp", rotary_pins), - ADI_PIN_GROUP("can0grp", can0_pins), - ADI_PIN_GROUP("can1grp", can1_pins), - ADI_PIN_GROUP("smc0grp", smc0_pins), - ADI_PIN_GROUP("sport0grp", sport0_pins), - ADI_PIN_GROUP("sport1grp", sport1_pins), - ADI_PIN_GROUP("sport2grp", sport2_pins), - ADI_PIN_GROUP("sport3grp", sport3_pins), - ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins), - ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins), - ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins), - ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins), - ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins), - ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins), - ADI_PIN_GROUP("atapigrp", atapi_pins), - ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins), - ADI_PIN_GROUP("nfc0grp", nfc0_pins), - ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins), - ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins), -}; - static const unsigned short uart0_mux[] = { P_UART0_TX, P_UART0_RX, 0 @@ -513,6 +480,39 @@ static const unsigned short keys_8x8_mux[] = { 0 }; +static const struct adi_pin_group adi_pin_groups[] = { + ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux), + ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux), + ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux), + ADI_PIN_GROUP("uart2grp", uart2_pins, uart2_mux), + ADI_PIN_GROUP("uart3grp", uart3_pins, uart3_mux), + ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins, uart3_ctsrts_mux), + ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux), + ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux), + ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux), + ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux), + ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux), + ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux), + ADI_PIN_GROUP("can0grp", can0_pins, can0_mux), + ADI_PIN_GROUP("can1grp", can1_pins, can1_mux), + ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux), + ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux), + ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux), + ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux), + ADI_PIN_GROUP("sport3grp", sport3_pins, sport3_mux), + ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux), + ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux), + ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux), + ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux), + ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux), + ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux), + ADI_PIN_GROUP("atapigrp", atapi_pins, atapi_mux), + ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins, atapi_alter_mux), + ADI_PIN_GROUP("nfc0grp", nfc0_pins, nfc0_mux), + ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins, keys_4x4_mux), + ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins, keys_8x8_mux), +}; + static const char * const uart0grp[] = { "uart0grp" }; static const char * const uart1grp[] = { "uart1grp" }; static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" }; @@ -532,49 +532,45 @@ static const char * const sport0grp[] = { "sport0grp" }; static const char * const sport1grp[] = { "sport1grp" }; static const char * const sport2grp[] = { "sport2grp" }; static const char * const sport3grp[] = { "sport3grp" }; -static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" }; -static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" }; -static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" }; -static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" }; -static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" }; -static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" }; +static const char * const ppi0grp[] = { "ppi0_8bgrp", + "ppi0_16bgrp", + "ppi0_24bgrp" }; +static const char * const ppi1grp[] = { "ppi1_8bgrp", + "ppi1_16bgrp" }; +static const char * const ppi2grp[] = { "ppi2_8bgrp" }; static const char * const atapigrp[] = { "atapigrp" }; static const char * const atapialtergrp[] = { "atapialtergrp" }; static const char * const nfc0grp[] = { "nfc0grp" }; -static const char * const keys_4x4grp[] = { "keys_4x4grp" }; -static const char * const keys_8x8grp[] = { "keys_8x8grp" }; +static const char * const keysgrp[] = { "keys_4x4grp", + "keys_8x8grp" }; static const struct adi_pmx_func adi_pmx_functions[] = { - ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux), - ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux), - ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux), - ADI_PMX_FUNCTION("uart2", uart2grp, uart2_mux), - ADI_PMX_FUNCTION("uart3", uart3grp, uart3_mux), - ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp, uart3_ctsrts_mux), - ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux), - ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux), - ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux), - ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux), - ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux), - ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux), - ADI_PMX_FUNCTION("can0", can0grp, can0_mux), - ADI_PMX_FUNCTION("can1", can1grp, can1_mux), - ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux), - ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux), - ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux), - ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux), - ADI_PMX_FUNCTION("sport3", sport3grp, sport3_mux), - ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux), - ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux), - ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux), - ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux), - ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux), - ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux), - ADI_PMX_FUNCTION("atapi", atapigrp, atapi_mux), - ADI_PMX_FUNCTION("atapi_alter", atapialtergrp, atapi_alter_mux), - ADI_PMX_FUNCTION("nfc0", nfc0grp, nfc0_mux), - ADI_PMX_FUNCTION("keys_4x4", keys_4x4grp, keys_4x4_mux), - ADI_PMX_FUNCTION("keys_8x8", keys_8x8grp, keys_8x8_mux), + ADI_PMX_FUNCTION("uart0", uart0grp), + ADI_PMX_FUNCTION("uart1", uart1grp), + ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp), + ADI_PMX_FUNCTION("uart2", uart2grp), + ADI_PMX_FUNCTION("uart3", uart3grp), + ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp), + ADI_PMX_FUNCTION("rsi0", rsi0grp), + ADI_PMX_FUNCTION("spi0", spi0grp), + ADI_PMX_FUNCTION("spi1", spi1grp), + ADI_PMX_FUNCTION("twi0", twi0grp), + ADI_PMX_FUNCTION("twi1", twi1grp), + ADI_PMX_FUNCTION("rotary", rotarygrp), + ADI_PMX_FUNCTION("can0", can0grp), + ADI_PMX_FUNCTION("can1", can1grp), + ADI_PMX_FUNCTION("smc0", smc0grp), + ADI_PMX_FUNCTION("sport0", sport0grp), + ADI_PMX_FUNCTION("sport1", sport1grp), + ADI_PMX_FUNCTION("sport2", sport2grp), + ADI_PMX_FUNCTION("sport3", sport3grp), + ADI_PMX_FUNCTION("ppi0", ppi0grp), + ADI_PMX_FUNCTION("ppi1", ppi1grp), + ADI_PMX_FUNCTION("ppi2", ppi2grp), + ADI_PMX_FUNCTION("atapi", atapigrp), + ADI_PMX_FUNCTION("atapi_alter", atapialtergrp), + ADI_PMX_FUNCTION("nfc0", nfc0grp), + ADI_PMX_FUNCTION("keys", keysgrp), }; static const struct adi_pinctrl_soc_data adi_bf54x_soc = { diff --git a/drivers/pinctrl/pinctrl-adi2-bf60x.c b/drivers/pinctrl/pinctrl-adi2-bf60x.c index bf57aea2826c..4cb59fe9be70 100644 --- a/drivers/pinctrl/pinctrl-adi2-bf60x.c +++ b/drivers/pinctrl/pinctrl-adi2-bf60x.c @@ -259,37 +259,6 @@ static const unsigned lp3_pins[] = { GPIO_PF12, GPIO_PF13, GPIO_PF14, GPIO_PF15, }; -static const struct adi_pin_group adi_pin_groups[] = { - ADI_PIN_GROUP("uart0grp", uart0_pins), - ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins), - ADI_PIN_GROUP("uart1grp", uart1_pins), - ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins), - ADI_PIN_GROUP("rsi0grp", rsi0_pins), - ADI_PIN_GROUP("eth0grp", eth0_pins), - ADI_PIN_GROUP("eth1grp", eth1_pins), - ADI_PIN_GROUP("spi0grp", spi0_pins), - ADI_PIN_GROUP("spi1grp", spi1_pins), - ADI_PIN_GROUP("twi0grp", twi0_pins), - ADI_PIN_GROUP("twi1grp", twi1_pins), - ADI_PIN_GROUP("rotarygrp", rotary_pins), - ADI_PIN_GROUP("can0grp", can0_pins), - ADI_PIN_GROUP("smc0grp", smc0_pins), - ADI_PIN_GROUP("sport0grp", sport0_pins), - ADI_PIN_GROUP("sport1grp", sport1_pins), - ADI_PIN_GROUP("sport2grp", sport2_pins), - ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins), - ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins), - ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins), - ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins), - ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins), - ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins), - ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins), - ADI_PIN_GROUP("lp0grp", lp0_pins), - ADI_PIN_GROUP("lp1grp", lp1_pins), - ADI_PIN_GROUP("lp2grp", lp2_pins), - ADI_PIN_GROUP("lp3grp", lp3_pins), -}; - static const unsigned short uart0_mux[] = { P_UART0_TX, P_UART0_RX, 0 @@ -446,6 +415,37 @@ static const unsigned short lp3_mux[] = { 0 }; +static const struct adi_pin_group adi_pin_groups[] = { + ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux), + ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins, uart0_ctsrts_mux), + ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux), + ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux), + ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux), + ADI_PIN_GROUP("eth0grp", eth0_pins, eth0_mux), + ADI_PIN_GROUP("eth1grp", eth1_pins, eth1_mux), + ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux), + ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux), + ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux), + ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux), + ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux), + ADI_PIN_GROUP("can0grp", can0_pins, can0_mux), + ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux), + ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux), + ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux), + ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux), + ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux), + ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux), + ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux), + ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux), + ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux), + ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux), + ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins, ppi2_16b_mux), + ADI_PIN_GROUP("lp0grp", lp0_pins, lp0_mux), + ADI_PIN_GROUP("lp1grp", lp1_pins, lp1_mux), + ADI_PIN_GROUP("lp2grp", lp2_pins, lp2_mux), + ADI_PIN_GROUP("lp3grp", lp3_pins, lp3_mux), +}; + static const char * const uart0grp[] = { "uart0grp" }; static const char * const uart0ctsrtsgrp[] = { "uart0ctsrtsgrp" }; static const char * const uart1grp[] = { "uart1grp" }; @@ -463,47 +463,43 @@ static const char * const smc0grp[] = { "smc0grp" }; static const char * const sport0grp[] = { "sport0grp" }; static const char * const sport1grp[] = { "sport1grp" }; static const char * const sport2grp[] = { "sport2grp" }; -static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" }; -static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" }; -static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" }; -static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" }; -static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" }; -static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" }; -static const char * const ppi2_16bgrp[] = { "ppi2_16bgrp" }; +static const char * const ppi0grp[] = { "ppi0_8bgrp", + "ppi0_16bgrp", + "ppi0_24bgrp" }; +static const char * const ppi1grp[] = { "ppi1_8bgrp", + "ppi1_16bgrp" }; +static const char * const ppi2grp[] = { "ppi2_8bgrp", + "ppi2_16bgrp" }; static const char * const lp0grp[] = { "lp0grp" }; static const char * const lp1grp[] = { "lp1grp" }; static const char * const lp2grp[] = { "lp2grp" }; static const char * const lp3grp[] = { "lp3grp" }; static const struct adi_pmx_func adi_pmx_functions[] = { - ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux), - ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp, uart0_ctsrts_mux), - ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux), - ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux), - ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux), - ADI_PMX_FUNCTION("eth0", eth0grp, eth0_mux), - ADI_PMX_FUNCTION("eth1", eth1grp, eth1_mux), - ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux), - ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux), - ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux), - ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux), - ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux), - ADI_PMX_FUNCTION("can0", can0grp, can0_mux), - ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux), - ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux), - ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux), - ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux), - ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux), - ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux), - ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux), - ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux), - ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux), - ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux), - ADI_PMX_FUNCTION("ppi2_16b", ppi2_16bgrp, ppi2_16b_mux), - ADI_PMX_FUNCTION("lp0", lp0grp, lp0_mux), - ADI_PMX_FUNCTION("lp1", lp1grp, lp1_mux), - ADI_PMX_FUNCTION("lp2", lp2grp, lp2_mux), - ADI_PMX_FUNCTION("lp3", lp3grp, lp3_mux), + ADI_PMX_FUNCTION("uart0", uart0grp), + ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp), + ADI_PMX_FUNCTION("uart1", uart1grp), + ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp), + ADI_PMX_FUNCTION("rsi0", rsi0grp), + ADI_PMX_FUNCTION("eth0", eth0grp), + ADI_PMX_FUNCTION("eth1", eth1grp), + ADI_PMX_FUNCTION("spi0", spi0grp), + ADI_PMX_FUNCTION("spi1", spi1grp), + ADI_PMX_FUNCTION("twi0", twi0grp), + ADI_PMX_FUNCTION("twi1", twi1grp), + ADI_PMX_FUNCTION("rotary", rotarygrp), + ADI_PMX_FUNCTION("can0", can0grp), + ADI_PMX_FUNCTION("smc0", smc0grp), + ADI_PMX_FUNCTION("sport0", sport0grp), + ADI_PMX_FUNCTION("sport1", sport1grp), + ADI_PMX_FUNCTION("sport2", sport2grp), + ADI_PMX_FUNCTION("ppi0", ppi0grp), + ADI_PMX_FUNCTION("ppi1", ppi1grp), + ADI_PMX_FUNCTION("ppi2", ppi2grp), + ADI_PMX_FUNCTION("lp0", lp0grp), + ADI_PMX_FUNCTION("lp1", lp1grp), + ADI_PMX_FUNCTION("lp2", lp2grp), + ADI_PMX_FUNCTION("lp3", lp3grp), }; static const struct adi_pinctrl_soc_data adi_bf60x_soc = { diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index 7a39562c3e42..200ea1e72d40 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -89,6 +89,19 @@ struct gpio_port_saved { u32 mux; }; +/* + * struct gpio_pint_saved - PINT registers saved in PM operations + * + * @assign: ASSIGN register + * @edge_set: EDGE_SET register + * @invert_set: INVERT_SET register + */ +struct gpio_pint_saved { + u32 assign; + u32 edge_set; + u32 invert_set; +}; + /** * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO * banks can be mapped into one Pin interrupt controller. @@ -114,7 +127,7 @@ struct gpio_pint { int irq; struct irq_domain *domain[2]; struct gpio_pint_regs *regs; - struct adi_pm_pint_save saved_data; + struct gpio_pint_saved saved_data; int map_count; spinlock_t lock; @@ -160,7 +173,7 @@ struct adi_pinctrl { struct gpio_port { struct list_head node; void __iomem *base; - unsigned int irq_base; + int irq_base; unsigned int width; struct gpio_port_t *regs; struct gpio_port_saved saved_data; @@ -605,8 +618,8 @@ static struct pinctrl_ops adi_pctrl_ops = { .get_group_pins = adi_get_group_pins, }; -static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id, + unsigned group_id) { struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); struct gpio_port *port; @@ -614,7 +627,7 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, unsigned long flags; unsigned short *mux, pin; - mux = (unsigned short *)pinctrl->soc->functions[selector].mux; + mux = (unsigned short *)pinctrl->soc->groups[group_id].mux; while (*mux) { pin = P_IDENT(*mux); @@ -628,7 +641,7 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, spin_lock_irqsave(&port->lock, flags); portmux_setup(port, pin_to_offset(range, pin), - P_FUNCT2MUX(*mux)); + P_FUNCT2MUX(*mux)); port_setup(port, pin_to_offset(range, pin), false); mux++; @@ -638,8 +651,8 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned func_id, + unsigned group_id) { struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); struct gpio_port *port; @@ -647,7 +660,7 @@ static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned selector, unsigned long flags; unsigned short *mux, pin; - mux = (unsigned short *)pinctrl->soc->functions[selector].mux; + mux = (unsigned short *)pinctrl->soc->groups[group_id].mux; while (*mux) { pin = P_IDENT(*mux); diff --git a/drivers/pinctrl/pinctrl-adi2.h b/drivers/pinctrl/pinctrl-adi2.h index 1f06f8df1fa3..3ca29738213f 100644 --- a/drivers/pinctrl/pinctrl-adi2.h +++ b/drivers/pinctrl/pinctrl-adi2.h @@ -21,13 +21,15 @@ struct adi_pin_group { const char *name; const unsigned *pins; const unsigned num; + const unsigned short *mux; }; -#define ADI_PIN_GROUP(n, p) \ +#define ADI_PIN_GROUP(n, p, m) \ { \ .name = n, \ .pins = p, \ .num = ARRAY_SIZE(p), \ + .mux = m, \ } /** @@ -41,15 +43,13 @@ struct adi_pmx_func { const char *name; const char * const *groups; const unsigned num_groups; - const unsigned short *mux; }; -#define ADI_PMX_FUNCTION(n, g, m) \ +#define ADI_PMX_FUNCTION(n, g) \ { \ .name = n, \ .groups = g, \ .num_groups = ARRAY_SIZE(g), \ - .mux = m, \ } /** diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 38c6f8b9790e..5d24aaec5dbc 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1137,6 +1137,17 @@ static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) pinctrl_free_gpio(gpio); } +static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); + void __iomem *pio = at91_gpio->regbase; + unsigned mask = 1 << offset; + u32 osr; + + osr = readl_relaxed(pio + PIO_OSR); + return !(osr & mask); +} + static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); @@ -1286,22 +1297,22 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type) switch (type) { case IRQ_TYPE_EDGE_RISING: - irq_set_handler(d->irq, handle_simple_irq); + __irq_set_handler_locked(d->irq, handle_simple_irq); writel_relaxed(mask, pio + PIO_ESR); writel_relaxed(mask, pio + PIO_REHLSR); break; case IRQ_TYPE_EDGE_FALLING: - irq_set_handler(d->irq, handle_simple_irq); + __irq_set_handler_locked(d->irq, handle_simple_irq); writel_relaxed(mask, pio + PIO_ESR); writel_relaxed(mask, pio + PIO_FELLSR); break; case IRQ_TYPE_LEVEL_LOW: - irq_set_handler(d->irq, handle_level_irq); + __irq_set_handler_locked(d->irq, handle_level_irq); writel_relaxed(mask, pio + PIO_LSR); writel_relaxed(mask, pio + PIO_FELLSR); break; case IRQ_TYPE_LEVEL_HIGH: - irq_set_handler(d->irq, handle_level_irq); + __irq_set_handler_locked(d->irq, handle_level_irq); writel_relaxed(mask, pio + PIO_LSR); writel_relaxed(mask, pio + PIO_REHLSR); break; @@ -1310,7 +1321,7 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type) * disable additional interrupt modes: * fall back to default behavior */ - irq_set_handler(d->irq, handle_simple_irq); + __irq_set_handler_locked(d->irq, handle_simple_irq); writel_relaxed(mask, pio + PIO_AIMDR); return 0; case IRQ_TYPE_NONE: @@ -1325,6 +1336,31 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type) return 0; } +static unsigned int gpio_irq_startup(struct irq_data *d) +{ + struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); + unsigned pin = d->hwirq; + int ret; + + ret = gpio_lock_as_irq(&at91_gpio->chip, pin); + if (ret) { + dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n", + d->hwirq); + return ret; + } + gpio_irq_unmask(d); + return 0; +} + +static void gpio_irq_shutdown(struct irq_data *d) +{ + struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); + unsigned pin = d->hwirq; + + gpio_irq_mask(d); + gpio_unlock_as_irq(&at91_gpio->chip, pin); +} + #ifdef CONFIG_PM static u32 wakeups[MAX_GPIO_BANKS]; @@ -1399,6 +1435,8 @@ void at91_pinctrl_gpio_resume(void) static struct irq_chip gpio_irqchip = { .name = "GPIO", + .irq_startup = gpio_irq_startup, + .irq_shutdown = gpio_irq_shutdown, .irq_disable = gpio_irq_mask, .irq_mask = gpio_irq_mask, .irq_unmask = gpio_irq_unmask, @@ -1543,6 +1581,7 @@ static int at91_gpio_of_irq_setup(struct device_node *node, static struct gpio_chip at91_gpio_template = { .request = at91_gpio_request, .free = at91_gpio_free, + .get_direction = at91_gpio_get_direction, .direction_input = at91_gpio_direction_input, .get = at91_gpio_get, .direction_output = at91_gpio_direction_output, diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c index 155b1b3a0e7a..07c81306f2f3 100644 --- a/drivers/pinctrl/pinctrl-exynos.c +++ b/drivers/pinctrl/pinctrl-exynos.c @@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { }, }; +/* pin banks of exynos5260 pin-controller 0 */ +static struct samsung_pin_bank exynos5260_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5260 pin-controller 1 */ +static struct samsung_pin_bank exynos5260_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), +}; + +/* pin banks of exynos5260 pin-controller 2 */ +static struct samsung_pin_bank exynos5260_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +/* + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes + * three gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5260_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .weint_con = EXYNOS_WKUP_ECON_OFFSET, + .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .label = "exynos5260-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5260_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5260_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl2", + }, +}; + /* pin banks of exynos5420 pin-controller 0 */ static struct samsung_pin_bank exynos5420_pin_banks0[] = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c index 4779b8e0eee8..e118fb121e02 100644 --- a/drivers/pinctrl/pinctrl-imx.c +++ b/drivers/pinctrl/pinctrl-imx.c @@ -491,7 +491,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np, pin->mux_mode |= IOMUXC_CONFIG_SION; pin->config = config & ~IMX_PAD_SION; - dev_dbg(info->dev, "%s: %d 0x%08lx", info->pins[i].name, + dev_dbg(info->dev, "%s: %d 0x%08lx", info->pins[pin_id].name, pin->mux_mode, pin->config); } diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c index 17aecde1b51d..815384b377b5 100644 --- a/drivers/pinctrl/pinctrl-imx1-core.c +++ b/drivers/pinctrl/pinctrl-imx1-core.c @@ -45,7 +45,7 @@ struct imx1_pinctrl { #define MX1_DDIR 0x00 #define MX1_OCR 0x04 #define MX1_ICONFA 0x0c -#define MX1_ICONFB 0x10 +#define MX1_ICONFB 0x14 #define MX1_GIUS 0x20 #define MX1_GPR 0x38 #define MX1_PUEN 0x40 @@ -97,13 +97,13 @@ static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, u32 old_val; u32 new_val; - dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n", - reg, offset, value); - /* Use the next register if the pin's port pin number is >=16 */ if (pin_id % 32 >= 16) reg += 0x04; + dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n", + reg, offset, value); + /* Get current state of pins */ old_val = readl(reg); old_val &= mask; @@ -139,7 +139,7 @@ static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, u32 reg_offset) { void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; - int offset = pin_id % 16; + int offset = (pin_id % 16) * 2; /* Use the next register if the pin's port pin number is >=16 */ if (pin_id % 32 >= 16) diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c index ef2bf3126da6..2cfb1d4e4395 100644 --- a/drivers/pinctrl/pinctrl-msm.c +++ b/drivers/pinctrl/pinctrl-msm.c @@ -228,6 +228,11 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, *bit = g->drv_bit; *mask = 7; break; + case PIN_CONFIG_OUTPUT: + *reg = g->ctl_reg; + *bit = g->oe_bit; + *mask = 1; + break; default: dev_err(pctrl->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; @@ -301,6 +306,14 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_DRIVE_STRENGTH: arg = msm_regval_to_drive[arg]; break; + case PIN_CONFIG_OUTPUT: + /* Pin is not output */ + if (!arg) + return -EINVAL; + + val = readl(pctrl->regs + g->io_reg); + arg = !!(val & BIT(g->in_bit)); + break; default: dev_err(pctrl->dev, "Unsupported config parameter: %x\n", param); @@ -357,6 +370,20 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, else arg = msm_drive_to_regval[arg]; break; + case PIN_CONFIG_OUTPUT: + /* set output value */ + spin_lock_irqsave(&pctrl->lock, flags); + val = readl(pctrl->regs + g->io_reg); + if (arg) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + writel(val, pctrl->regs + g->io_reg); + spin_unlock_irqrestore(&pctrl->lock, flags); + + /* enable output */ + arg = 1; + break; default: dev_err(pctrl->dev, "Unsupported config parameter: %x\n", param); diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c index f944bf2172ef..9aeeb384ddf7 100644 --- a/drivers/pinctrl/pinctrl-msm8x74.c +++ b/drivers/pinctrl/pinctrl-msm8x74.c @@ -406,6 +406,7 @@ enum msm8x74_functions { MSM_MUX_blsp_i2c6, MSM_MUX_blsp_i2c11, MSM_MUX_blsp_spi1, + MSM_MUX_blsp_spi8, MSM_MUX_blsp_uart2, MSM_MUX_blsp_uart8, MSM_MUX_slimbus, @@ -416,6 +417,9 @@ static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" }; static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; static const char * const blsp_spi1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" }; +static const char * const blsp_spi8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; static const char * const blsp_uart2_groups[] = { "gpio4", "gpio5" }; static const char * const blsp_uart8_groups[] = { "gpio45", "gpio46" }; static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; @@ -425,6 +429,7 @@ static const struct msm_function msm8x74_functions[] = { FUNCTION(blsp_i2c6), FUNCTION(blsp_i2c11), FUNCTION(blsp_spi1), + FUNCTION(blsp_spi8), FUNCTION(blsp_uart2), FUNCTION(blsp_uart8), FUNCTION(slimbus), @@ -476,10 +481,10 @@ static const struct msm_pingroup msm8x74_groups[] = { PINGROUP(42, NA, NA, NA, NA, NA, NA, NA), PINGROUP(43, NA, NA, NA, NA, NA, NA, NA), PINGROUP(44, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(45, NA, blsp_uart8, NA, NA, NA, NA, NA), - PINGROUP(46, NA, blsp_uart8, NA, NA, NA, NA, NA), - PINGROUP(47, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(48, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA), + PINGROUP(46, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA), + PINGROUP(47, blsp_spi8, NA, NA, NA, NA, NA, NA), + PINGROUP(48, blsp_spi8, NA, NA, NA, NA, NA, NA), PINGROUP(49, NA, NA, NA, NA, NA, NA, NA), PINGROUP(50, NA, NA, NA, NA, NA, NA, NA), PINGROUP(51, NA, NA, NA, NA, NA, NA, NA), diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 53a11114927f..cec7762cf335 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -2035,27 +2035,29 @@ static const struct of_device_id nmk_pinctrl_match[] = { {}, }; -static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) +#ifdef CONFIG_PM_SLEEP +static int nmk_pinctrl_suspend(struct device *dev) { struct nmk_pinctrl *npct; - npct = platform_get_drvdata(pdev); + npct = dev_get_drvdata(dev); if (!npct) return -EINVAL; return pinctrl_force_sleep(npct->pctl); } -static int nmk_pinctrl_resume(struct platform_device *pdev) +static int nmk_pinctrl_resume(struct device *dev) { struct nmk_pinctrl *npct; - npct = platform_get_drvdata(pdev); + npct = dev_get_drvdata(dev); if (!npct) return -EINVAL; return pinctrl_force_default(npct->pctl); } +#endif static int nmk_pinctrl_probe(struct platform_device *pdev) { @@ -2144,17 +2146,18 @@ static struct platform_driver nmk_gpio_driver = { .probe = nmk_gpio_probe, }; +static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, + nmk_pinctrl_suspend, + nmk_pinctrl_resume); + static struct platform_driver nmk_pinctrl_driver = { .driver = { .owner = THIS_MODULE, .name = "pinctrl-nomadik", .of_match_table = nmk_pinctrl_match, + .pm = &nmk_pinctrl_pm_ops, }, .probe = nmk_pinctrl_probe, -#ifdef CONFIG_PM - .suspend = nmk_pinctrl_suspend, - .resume = nmk_pinctrl_resume, -#endif }; static int __init nmk_gpio_init(void) diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index 47ec2e8741e4..0324d4cb19b2 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -1120,6 +1120,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos4x12_pin_ctrl }, { .compatible = "samsung,exynos5250-pinctrl", .data = (void *)exynos5250_pin_ctrl }, + { .compatible = "samsung,exynos5260-pinctrl", + .data = (void *)exynos5260_pin_ctrl }, { .compatible = "samsung,exynos5420-pinctrl", .data = (void *)exynos5420_pin_ctrl }, { .compatible = "samsung,s5pv210-pinctrl", diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h index 30622d9afa2e..bab9c2122556 100644 --- a/drivers/pinctrl/pinctrl-samsung.h +++ b/drivers/pinctrl/pinctrl-samsung.h @@ -254,6 +254,7 @@ struct samsung_pmx_func { extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5260_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index de6459628b4f..81075f2a1d3f 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -662,6 +662,7 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_SLEW_RATE: + case PIN_CONFIG_LOW_POWER_MODE: default: *config = data; break; @@ -699,6 +700,7 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_INPUT_SCHMITT: case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_SLEW_RATE: + case PIN_CONFIG_LOW_POWER_MODE: shift = ffs(func->conf[i].mask) - 1; data &= ~func->conf[i].mask; data |= (arg << shift) & func->conf[i].mask; @@ -1101,6 +1103,7 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, + { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, }, }; struct pcs_conf_type prop4[] = { { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 320c27363cc8..9fb66aa796aa 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -13,7 +13,12 @@ #include <linux/slab.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/irq.h> +#include <linux/irqdesc.h> +#include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/of.h> +#include <linux/of_irq.h> #include <linux/of_gpio.h> #include <linux/of_address.h> #include <linux/regmap.h> @@ -266,11 +271,59 @@ struct st_pctl_group { struct st_pinconf *pin_conf; }; +/* + * Edge triggers are not supported at hardware level, it is supported by + * software by exploiting the level trigger support in hardware. + * Software uses a virtual register (EDGE_CONF) for edge trigger configuration + * of each gpio pin in a GPIO bank. + * + * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of + * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. + * + * bit allocation per pin is: + * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] + * -------------------------------------------------------- + * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | + * -------------------------------------------------------- + * + * A pin can have one of following the values in its edge configuration field. + * + * ------- ---------------------------- + * [0-3] - Description + * ------- ---------------------------- + * 0000 - No edge IRQ. + * 0001 - Falling edge IRQ. + * 0010 - Rising edge IRQ. + * 0011 - Rising and Falling edge IRQ. + * ------- ---------------------------- + */ + +#define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 +#define ST_IRQ_EDGE_MASK 0xf +#define ST_IRQ_EDGE_FALLING BIT(0) +#define ST_IRQ_EDGE_RISING BIT(1) +#define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) + +#define ST_IRQ_RISING_EDGE_CONF(pin) \ + (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) + +#define ST_IRQ_FALLING_EDGE_CONF(pin) \ + (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) + +#define ST_IRQ_BOTH_EDGE_CONF(pin) \ + (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) + +#define ST_IRQ_EDGE_CONF(conf, pin) \ + (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) + struct st_gpio_bank { struct gpio_chip gpio_chip; struct pinctrl_gpio_range range; void __iomem *base; struct st_pio_control pc; + struct irq_domain *domain; + unsigned long irq_edge_conf; + spinlock_t lock; }; struct st_pinctrl { @@ -284,6 +337,7 @@ struct st_pinctrl { int ngroups; struct regmap *regmap; const struct st_pctl_data *data; + void __iomem *irqmux_base; }; /* SOC specific data */ @@ -1200,6 +1254,194 @@ static int st_pctl_parse_functions(struct device_node *np, return 0; } +static int st_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct st_gpio_bank *bank = gpio_chip_to_bank(chip); + int irq = -ENXIO; + + if (offset < chip->ngpio) + irq = irq_find_mapping(bank->domain, offset); + + dev_info(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", + chip->label, offset + chip->base, irq); + return irq; +} + +static void st_gpio_irq_mask(struct irq_data *d) +{ + struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); + + writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); +} + +static void st_gpio_irq_unmask(struct irq_data *d) +{ + struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); + + writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); +} + +static unsigned int st_gpio_irq_startup(struct irq_data *d) +{ + struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); + + if (gpio_lock_as_irq(&bank->gpio_chip, d->hwirq)) + dev_err(bank->gpio_chip.dev, + "unable to lock HW IRQ %lu for IRQ\n", + d->hwirq); + + st_gpio_irq_unmask(d); + + return 0; +} + +static void st_gpio_irq_shutdown(struct irq_data *d) +{ + struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); + + st_gpio_irq_mask(d); + gpio_unlock_as_irq(&bank->gpio_chip, d->hwirq); +} + +static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) +{ + struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); + unsigned long flags; + int comp, pin = d->hwirq; + u32 val; + u32 pin_edge_conf = 0; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + comp = 0; + break; + case IRQ_TYPE_EDGE_FALLING: + comp = 0; + pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); + break; + case IRQ_TYPE_LEVEL_LOW: + comp = 1; + break; + case IRQ_TYPE_EDGE_RISING: + comp = 1; + pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); + break; + case IRQ_TYPE_EDGE_BOTH: + comp = st_gpio_get(&bank->gpio_chip, pin); + pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); + break; + default: + return -EINVAL; + } + + spin_lock_irqsave(&bank->lock, flags); + bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( + pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); + bank->irq_edge_conf |= pin_edge_conf; + spin_unlock_irqrestore(&bank->lock, flags); + + val = readl(bank->base + REG_PIO_PCOMP); + val &= ~BIT(pin); + val |= (comp << pin); + writel(val, bank->base + REG_PIO_PCOMP); + + return 0; +} + +/* + * As edge triggers are not supported at hardware level, it is supported by + * software by exploiting the level trigger support in hardware. + * + * Steps for detection raising edge interrupt in software. + * + * Step 1: CONFIGURE pin to detect level LOW interrupts. + * + * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, + * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. + * IGNORE calling the actual interrupt handler for the pin at this stage. + * + * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler + * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then + * DISPATCH the interrupt to the interrupt handler of the pin. + * + * step-1 ________ __________ + * | | step - 3 + * | | + * step -2 |_____| + * + * falling edge is also detected int the same way. + * + */ +static void __gpio_irq_handler(struct st_gpio_bank *bank) +{ + unsigned long port_in, port_mask, port_comp, active_irqs; + unsigned long bank_edge_mask, flags; + int n, val, ecfg; + + spin_lock_irqsave(&bank->lock, flags); + bank_edge_mask = bank->irq_edge_conf; + spin_unlock_irqrestore(&bank->lock, flags); + + for (;;) { + port_in = readl(bank->base + REG_PIO_PIN); + port_comp = readl(bank->base + REG_PIO_PCOMP); + port_mask = readl(bank->base + REG_PIO_PMASK); + + active_irqs = (port_in ^ port_comp) & port_mask; + + if (active_irqs == 0) + break; + + for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { + /* check if we are detecting fake edges ... */ + ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); + + if (ecfg) { + /* edge detection. */ + val = st_gpio_get(&bank->gpio_chip, n); + + writel(BIT(n), + val ? bank->base + REG_PIO_SET_PCOMP : + bank->base + REG_PIO_CLR_PCOMP); + + if (ecfg != ST_IRQ_EDGE_BOTH && + !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) + continue; + } + + generic_handle_irq(irq_find_mapping(bank->domain, n)); + } + } +} + +static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc) +{ + /* interrupt dedicated per bank */ + struct irq_chip *chip = irq_get_chip(irq); + struct st_gpio_bank *bank = irq_get_handler_data(irq); + + chained_irq_enter(chip, desc); + __gpio_irq_handler(bank); + chained_irq_exit(chip, desc); +} + +static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct st_pinctrl *info = irq_get_handler_data(irq); + unsigned long status; + int n; + + chained_irq_enter(chip, desc); + + status = readl(info->irqmux_base); + + for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK) + __gpio_irq_handler(&info->banks[n]); + + chained_irq_exit(chip, desc); +} + static struct gpio_chip st_gpio_template = { .request = st_gpio_request, .free = st_gpio_free, @@ -1210,6 +1452,34 @@ static struct gpio_chip st_gpio_template = { .ngpio = ST_GPIO_PINS_PER_BANK, .of_gpio_n_cells = 1, .of_xlate = st_gpio_xlate, + .to_irq = st_gpio_to_irq, +}; + +static struct irq_chip st_gpio_irqchip = { + .name = "GPIO", + .irq_mask = st_gpio_irq_mask, + .irq_unmask = st_gpio_irq_unmask, + .irq_set_type = st_gpio_irq_set_type, + .irq_startup = st_gpio_irq_startup, + .irq_shutdown = st_gpio_irq_shutdown, +}; + +static int st_gpio_irq_domain_map(struct irq_domain *h, + unsigned int virq, irq_hw_number_t hw) +{ + struct st_gpio_bank *bank = h->host_data; + + irq_set_chip(virq, &st_gpio_irqchip); + irq_set_handler(virq, handle_simple_irq); + set_irq_flags(virq, IRQF_VALID); + irq_set_chip_data(virq, bank); + + return 0; +} + +static struct irq_domain_ops st_gpio_irq_ops = { + .map = st_gpio_irq_domain_map, + .xlate = irq_domain_xlate_twocell, }; static int st_gpiolib_register_bank(struct st_pinctrl *info, @@ -1219,8 +1489,8 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, struct pinctrl_gpio_range *range = &bank->range; struct device *dev = info->dev; int bank_num = of_alias_get_id(np, "gpio"); - struct resource res; - int err; + struct resource res, irq_res; + int gpio_irq = 0, err, i; if (of_address_to_resource(np, 0, &res)) return -ENODEV; @@ -1233,6 +1503,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; bank->gpio_chip.of_node = np; + spin_lock_init(&bank->lock); of_property_read_string(np, "st,bank-name", &range->name); bank->gpio_chip.label = range->name; @@ -1248,6 +1519,51 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, } dev_info(dev, "%s bank added.\n", range->name); + /** + * GPIO bank can have one of the two possible types of + * interrupt-wirings. + * + * First type is via irqmux, single interrupt is used by multiple + * gpio banks. This reduces number of overall interrupts numbers + * required. All these banks belong to a single pincontroller. + * _________ + * | |----> [gpio-bank (n) ] + * | |----> [gpio-bank (n + 1)] + * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] + * | |----> [gpio-bank (... )] + * |_________|----> [gpio-bank (n + 7)] + * + * Second type has a dedicated interrupt per each gpio bank. + * + * [irqN]----> [gpio-bank (n)] + */ + + if (!of_irq_to_resource(np, 0, &irq_res)) { + gpio_irq = irq_res.start; + irq_set_chained_handler(gpio_irq, st_gpio_irq_handler); + irq_set_handler_data(gpio_irq, bank); + } + + if (info->irqmux_base > 0 || gpio_irq > 0) { + /* Setup IRQ domain */ + bank->domain = irq_domain_add_linear(np, + ST_GPIO_PINS_PER_BANK, + &st_gpio_irq_ops, bank); + if (!bank->domain) { + dev_err(dev, "Failed to add irq domain for %s\n", + np->full_name); + } else { + for (i = 0; i < ST_GPIO_PINS_PER_BANK; i++) { + if (irq_create_mapping(bank->domain, i) < 0) + dev_err(dev, + "Failed to map IRQ %i\n", i); + } + } + + } else { + dev_info(dev, "No IRQ support for %s bank\n", np->full_name); + } + return 0; } @@ -1276,6 +1592,8 @@ static int st_pctl_probe_dt(struct platform_device *pdev, struct device_node *np = pdev->dev.of_node; struct device_node *child; int grp_index = 0; + int irq = 0; + struct resource *res; st_pctl_dt_child_count(info, np); if (!info->nbanks) { @@ -1306,6 +1624,21 @@ static int st_pctl_probe_dt(struct platform_device *pdev, } info->data = of_match_node(st_pctl_of_match, np)->data; + irq = platform_get_irq(pdev, 0); + + if (irq > 0) { + res = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "irqmux"); + info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); + + if (IS_ERR(info->irqmux_base)) + return PTR_ERR(info->irqmux_base); + + irq_set_chained_handler(irq, st_gpio_irqmux_handler); + irq_set_handler_data(irq, info); + + } + pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; pdesc = devm_kzalloc(&pdev->dev, sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL); diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h index 6fd8d4d95140..3d6066988a72 100644 --- a/drivers/pinctrl/pinctrl-sunxi-pins.h +++ b/drivers/pinctrl/pinctrl-sunxi-pins.h @@ -1932,27 +1932,27 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */ + SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */ + SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */ + SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */ + SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */ + SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */ + SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, SUNXI_FUNCTION(0x0, "gpio_in"), diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index a2e93a2b5ff4..e767355ab0ad 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c @@ -645,7 +645,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, GFP_KERNEL); if (!pmx->regs) { dev_err(&pdev->dev, "Can't alloc regs pointer\n"); - return -ENODEV; + return -ENOMEM; } for (i = 0; i < pmx->nbanks; i++) { diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index c381ae63c508..2814440843df 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -2389,6 +2389,29 @@ static const unsigned int msiof3_tx_pins[] = { static const unsigned int msiof3_tx_mux[] = { MSIOF3_TXD_MARK, }; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 8), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -3231,6 +3254,13 @@ static const unsigned int usb0_pins[] = { static const unsigned int usb0_mux[] = { USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, }; +static const unsigned int usb0_ovc_vbus_pins[] = { + /* OVC/VBUS */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int usb0_ovc_vbus_mux[] = { + USB0_OVC_VBUS_MARK, +}; /* - USB1 ------------------------------------------------------------------- */ static const unsigned int usb1_pins[] = { /* PWEN, OVC */ @@ -3671,6 +3701,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof3_ss2), SH_PFC_PIN_GROUP(msiof3_rx), SH_PFC_PIN_GROUP(msiof3_tx), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -3789,6 +3822,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu0_to2), SH_PFC_PIN_GROUP(tpu0_to3), SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc_vbus), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), VIN_DATA_PIN_GROUP(vin0_data, 24), @@ -3970,6 +4004,12 @@ static const char * const msiof3_groups[] = { "msiof3_tx", }; +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -4134,6 +4174,7 @@ static const char * const tpu0_groups[] = { static const char * const usb0_groups[] = { "usb0", + "usb0_ovc_vbus", }; static const char * const usb1_groups[] = { @@ -4213,6 +4254,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 77d103fe39d9..7ac8d7fca91b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -1943,6 +1943,50 @@ static const unsigned int i2c4_c_pins[] = { static const unsigned int i2c4_c_mux[] = { SCL4_C_MARK, SDA4_C_MARK, }; +/* - I2C7 ------------------------------------------------------------------- */ +static const unsigned int i2c7_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int i2c7_mux[] = { + SCL7_MARK, SDA7_MARK, +}; +static const unsigned int i2c7_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), +}; +static const unsigned int i2c7_b_mux[] = { + SCL7_B_MARK, SDA7_B_MARK, +}; +static const unsigned int i2c7_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int i2c7_c_mux[] = { + SCL7_C_MARK, SDA7_C_MARK, +}; +/* - I2C8 ------------------------------------------------------------------- */ +static const unsigned int i2c8_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), +}; +static const unsigned int i2c8_mux[] = { + SCL8_MARK, SDA8_MARK, +}; +static const unsigned int i2c8_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), +}; +static const unsigned int i2c8_b_mux[] = { + SCL8_B_MARK, SDA8_B_MARK, +}; +static const unsigned int i2c8_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), +}; +static const unsigned int i2c8_c_mux[] = { + SCL8_C_MARK, SDA8_C_MARK, +}; /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ */ @@ -2135,6 +2179,53 @@ static const unsigned int msiof2_tx_pins[] = { static const unsigned int msiof2_tx_mux[] = { MSIOF2_TXD_MARK, }; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 8), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; + +static const unsigned int qspi_ctrl_b_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), +}; +static const unsigned int qspi_ctrl_b_mux[] = { + SPCLK_B_MARK, SSL_B_MARK, +}; +static const unsigned int qspi_data2_b_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), +}; +static const unsigned int qspi_data2_b_mux[] = { + MOSI_IO0_B_MARK, MISO_IO1_B_MARK, +}; +static const unsigned int qspi_data4_b_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), + RCAR_GP_PIN(6, 4), +}; +static const unsigned int qspi_data4_b_mux[] = { + SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK, + IO2_B_MARK, IO3_B_MARK, SSL_B_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -3123,6 +3214,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c4), SH_PFC_PIN_GROUP(i2c4_b), SH_PFC_PIN_GROUP(i2c4_c), + SH_PFC_PIN_GROUP(i2c7), + SH_PFC_PIN_GROUP(i2c7_b), + SH_PFC_PIN_GROUP(i2c7_c), + SH_PFC_PIN_GROUP(i2c8), + SH_PFC_PIN_GROUP(i2c8_b), + SH_PFC_PIN_GROUP(i2c8_c), SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), @@ -3149,6 +3246,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof2_ss2), SH_PFC_PIN_GROUP(msiof2_rx), SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(qspi_ctrl_b), + SH_PFC_PIN_GROUP(qspi_data2_b), + SH_PFC_PIN_GROUP(qspi_data4_b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -3335,6 +3438,18 @@ static const char * const i2c4_groups[] = { "i2c4_c", }; +static const char * const i2c7_groups[] = { + "i2c7", + "i2c7_b", + "i2c7_c", +}; + +static const char * const i2c8_groups[] = { + "i2c8", + "i2c8_b", + "i2c8_c", +}; + static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", @@ -3376,6 +3491,15 @@ static const char * const msiof2_groups[] = { "msiof2_tx", }; +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", + "qspi_ctrl_b", + "qspi_data2_b", + "qspi_data4_b", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_data_b", @@ -3566,11 +3690,14 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c7), + SH_PFC_FUNCTION(i2c8), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c index 2b9f32065920..c4dd3d5cf9c3 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas6.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c @@ -1,7 +1,8 @@ /* * pinctrl pads, groups, functions for CSR SiRFatlasVI * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. * * Licensed under GPLv2 or later. */ @@ -529,6 +530,40 @@ static const struct sirfsoc_padmux usp0_padmux = { static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; +static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = { + { + .group = 1, + .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), + }, +}; + +static const struct sirfsoc_padmux usp0_only_utfs_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask), + .muxmask = usp0_only_utfs_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(2) | BIT(6), + .funcval = 0, +}; + +static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 }; + +static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = { + { + .group = 1, + .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23), + }, +}; + +static const struct sirfsoc_padmux usp0_only_urfs_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask), + .muxmask = usp0_only_urfs_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(2) | BIT(9), + .funcval = 0, +}; + +static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 }; + static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = { { .group = 1, @@ -905,6 +940,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp", usp0_uart_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins), + SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins), SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp", usp1_uart_nostreamctrl_pins), @@ -953,6 +990,9 @@ static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; static const char * const usp0_uart_nostreamctrl_grp[] = { "usp0_uart_nostreamctrl_grp" }; static const char * const usp0grp[] = { "usp0grp" }; +static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" }; +static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" }; + static const char * const usp1grp[] = { "usp1grp" }; static const char * const usp1_uart_nostreamctrl_grp[] = { "usp1_uart_nostreamctrl_grp" }; @@ -1003,6 +1043,10 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, + usp0_only_utfs_padmux), + SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, + usp0_only_urfs_padmux), SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl", usp1_uart_nostreamctrl_grp, diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c index 37b42651d76a..8aa76f0776d7 100644 --- a/drivers/pinctrl/sirf/pinctrl-prima2.c +++ b/drivers/pinctrl/sirf/pinctrl-prima2.c @@ -1,7 +1,8 @@ /* * pinctrl pads, groups, functions for CSR SiRFprimaII * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. * * Licensed under GPLv2 or later. */ @@ -413,7 +414,7 @@ static const struct sirfsoc_padmux ac97_padmux = { .funcval = 0, }; -static const unsigned ac97_pins[] = { 33, 34, 35, 36 }; +static const unsigned ac97_pins[] = { 43, 44, 45, 46 }; static const struct sirfsoc_muxmask spi1_muxmask[] = { { diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index a0d6152701cd..72291cd5400b 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -1,7 +1,8 @@ /* * pinmux driver for CSR SiRFprimaII * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. * * Licensed under GPLv2 or later. */ diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c index b28d1af9c232..9802b67040cc 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wmt.c +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c @@ -276,7 +276,20 @@ static int wmt_pctl_dt_node_to_map_pull(struct wmt_pinctrl_data *data, if (!configs) return -ENOMEM; - configs[0] = pull; + switch (pull) { + case 0: + configs[0] = PIN_CONFIG_BIAS_DISABLE; + break; + case 1: + configs[0] = PIN_CONFIG_BIAS_PULL_DOWN; + break; + case 2: + configs[0] = PIN_CONFIG_BIAS_PULL_UP; + break; + default: + configs[0] = PIN_CONFIG_BIAS_DISABLE; + dev_err(data->dev, "invalid pull state %d - disabling\n", pull); + } map->type = PIN_MAP_TYPE_CONFIGS_PIN; map->data.configs.group_or_pin = data->groups[group]; |