diff options
Diffstat (limited to 'drivers/pinctrl')
36 files changed, 2167 insertions, 530 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 834c59950d1c..f646f070d98f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -172,15 +172,22 @@ config PINCTRL_GEMINI select GENERIC_PINCONF select MFD_SYSCON +config PINCTRL_MCP23S08_I2C + tristate + select REGMAP_I2C + +config PINCTRL_MCP23S08_SPI + tristate + select REGMAP_SPI + config PINCTRL_MCP23S08 tristate "Microchip MCP23xxx I/O expander" depends on SPI_MASTER || I2C - depends on I2C || I2C=n select GPIOLIB select GPIOLIB_IRQCHIP - select REGMAP_I2C if I2C - select REGMAP_SPI if SPI_MASTER select GENERIC_PINCONF + select PINCTRL_MCP23S08_I2C if I2C + select PINCTRL_MCP23S08_SPI if SPI_MASTER help SPI/I2C driver for Microchip MCP23S08 / MCP23S17 / MCP23S18 / MCP23008 / MCP23017 / MCP23018 I/O expanders. diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 0b36a1cfca8a..1731b2154df9 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -21,6 +21,8 @@ obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o +obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o +obj-$(CONFIG_PINCTRL_MCP23S08_SPI) += pinctrl-mcp23s08_spi.o obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index c784663b00ad..4ca44dd69e53 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -165,6 +165,13 @@ config PINCTRL_IMX8QXP help Say Y here to enable the imx8qxp pinctrl driver +config PINCTRL_IMX8DXL + bool "IMX8DXL pinctrl driver" + depends on IMX_SCU && ARCH_MXC && ARM64 + select PINCTRL_IMX_SCU + help + Say Y here to enable the imx8dxl pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 0ebd3af21e4d..c61722565289 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_IMX8MP) += pinctrl-imx8mp.o obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o +obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index c00d0022d311..0c1c0e72fa8e 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -60,7 +60,7 @@ struct imx1_pinctrl { /* * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX - * control register are seperated into function, output configuration, input + * control registers are separated into function, output configuration, input * configuration A, input configuration B, GPIO in use and data direction. * * Those controls that are represented by 1 bit have a direct mapping between diff --git a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c new file mode 100644 index 000000000000..7f32e57b7f6a --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019~2020 NXP + */ + +#include <dt-bindings/pinctrl/pads-imx8dxl.h> +#include <linux/err.h> +#include <linux/firmware/imx/sci.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +static const struct pinctrl_pin_desc imx8dxl_pinctrl_pads[] = { + IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_PERST_B), + IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_CLKREQ_B), + IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_WAKE_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC0), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC1), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC2), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC3), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_CLK), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_CMD), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA0), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA1), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA2), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA3), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA4), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA5), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA6), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA7), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_STROBE), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_RESET_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_RESET_B), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_VSELECT), + IMX_PINCTRL_PIN(IMX8DXL_CTL_NAND_RE_P_N), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_WP), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_CD_B), + IMX_PINCTRL_PIN(IMX8DXL_CTL_NAND_DQS_P_N), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD3), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD3), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_REFCLK_125M_25M), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_MDIO), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_MDC), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD3), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD3), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_REFCLK_125M_25M), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_SCK), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_SDO), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_SDI), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_CS0), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_CS1), + IMX_PINCTRL_PIN(IMX8DXL_MCLK_IN1), + IMX_PINCTRL_PIN(IMX8DXL_MCLK_IN0), + IMX_PINCTRL_PIN(IMX8DXL_MCLK_OUT0), + IMX_PINCTRL_PIN(IMX8DXL_UART1_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART1_RX), + IMX_PINCTRL_PIN(IMX8DXL_UART1_RTS_B), + IMX_PINCTRL_PIN(IMX8DXL_UART1_CTS_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_SCK), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_SDI), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_SDO), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_CS1), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_CS0), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN1), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN0), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN3), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN2), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN5), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN4), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN0_RX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN0_TX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN1_RX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN1_TX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN2_RX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN2_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART0_RX), + IMX_PINCTRL_PIN(IMX8DXL_UART0_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART2_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART2_RX), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH), + IMX_PINCTRL_PIN(IMX8DXL_JTAG_TRST_B), + IMX_PINCTRL_PIN(IMX8DXL_PMIC_I2C_SCL), + IMX_PINCTRL_PIN(IMX8DXL_PMIC_I2C_SDA), + IMX_PINCTRL_PIN(IMX8DXL_PMIC_INT_B), + IMX_PINCTRL_PIN(IMX8DXL_SCU_GPIO0_00), + IMX_PINCTRL_PIN(IMX8DXL_SCU_GPIO0_01), + IMX_PINCTRL_PIN(IMX8DXL_SCU_PMIC_STANDBY), + IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE1), + IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE0), + IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE2), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT1), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT2), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT3), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT4), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN0), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN1), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN2), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN3), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_SCK), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_SDO), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_SDI), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_CS0), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA1), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA0), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA3), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA2), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_SS0_B), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DQS), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_SCLK), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_SCLK), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DQS), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA1), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA0), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA3), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA2), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_SS0_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B) +}; + + +static struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = { + .pins = imx8dxl_pinctrl_pads, + .npins = ARRAY_SIZE(imx8dxl_pinctrl_pads), + .flags = IMX_USE_SCU, +}; + +static const struct of_device_id imx8dxl_pinctrl_of_match[] = { + { .compatible = "fsl,imx8dxl-iomuxc", }, + { /* sentinel */ } +}; + +static int imx8dxl_pinctrl_probe(struct platform_device *pdev) +{ + int ret; + + ret = imx_pinctrl_sc_ipc_init(pdev); + if (ret) + return ret; + + return imx_pinctrl_probe(pdev, &imx8dxl_pinctrl_info); +} + +static struct platform_driver imx8dxl_pinctrl_driver = { + .driver = { + .name = "fsl,imx8dxl-iomuxc", + .of_match_table = of_match_ptr(imx8dxl_pinctrl_of_match), + .suppress_bind_attrs = true, + }, + .probe = imx8dxl_pinctrl_probe, +}; + +static int __init imx8dxl_pinctrl_init(void) +{ + return platform_driver_register(&imx8dxl_pinctrl_driver); +} +arch_initcall(imx8dxl_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 701f9af63f5e..f32d3644c509 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -3,10 +3,12 @@ menu "MediaTek pinctrl drivers" depends on ARCH_MEDIATEK || COMPILE_TEST config EINT_MTK - bool "MediaTek External Interrupt Support" + tristate "MediaTek External Interrupt Support" depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS || COMPILE_TEST select GPIOLIB select IRQ_DOMAIN + default y if PINCTRL_MTK || PINCTRL_MTK_MOORE + default PINCTRL_MTK_PARIS config PINCTRL_MTK bool @@ -17,6 +19,9 @@ config PINCTRL_MTK select EINT_MTK select OF_GPIO +config PINCTRL_MTK_V2 + tristate + config PINCTRL_MTK_MOORE bool depends on OF @@ -25,15 +30,17 @@ config PINCTRL_MTK_MOORE select GENERIC_PINMUX_FUNCTIONS select GPIOLIB select OF_GPIO + select PINCTRL_MTK_V2 config PINCTRL_MTK_PARIS - bool + tristate depends on OF select PINMUX select GENERIC_PINCONF select GPIOLIB select EINT_MTK select OF_GPIO + select PINCTRL_MTK_V2 # For ARMv7 SoCs config PINCTRL_MT2701 @@ -80,7 +87,7 @@ config PINCTRL_MT2712 select PINCTRL_MTK config PINCTRL_MT6765 - bool "Mediatek MT6765 pin control" + tristate "Mediatek MT6765 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index a74325abd877..4b7132876e71 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -2,8 +2,9 @@ # Core obj-$(CONFIG_EINT_MTK) += mtk-eint.o obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o -obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o pinctrl-mtk-common-v2.o -obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_V2) += pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o +obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o # SoC Drivers obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 7e526bcf5e0b..22736f60c16c 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -15,6 +15,7 @@ #include <linux/io.h> #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> +#include <linux/module.h> #include <linux/of_irq.h> #include <linux/platform_device.h> @@ -379,6 +380,7 @@ int mtk_eint_do_suspend(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_suspend); int mtk_eint_do_resume(struct mtk_eint *eint) { @@ -386,6 +388,7 @@ int mtk_eint_do_resume(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_resume); int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, unsigned int debounce) @@ -440,6 +443,7 @@ int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_set_debounce); int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) { @@ -451,6 +455,7 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) return irq; } +EXPORT_SYMBOL_GPL(mtk_eint_find_irq); int mtk_eint_do_init(struct mtk_eint *eint) { @@ -495,3 +500,7 @@ int mtk_eint_do_init(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek EINT Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6765.c b/drivers/pinctrl/mediatek/pinctrl-mt6765.c index 905dae8c3fd8..2c59d3936256 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c @@ -6,6 +6,7 @@ * */ +#include <linux/module.h> #include "pinctrl-mtk-mt6765.h" #include "pinctrl-paris.h" @@ -1103,3 +1104,6 @@ static int __init mt6765_pinctrl_init(void) return platform_driver_register(&mt6765_pinctrl_driver); } arch_initcall(mt6765_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT6765 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index d3169a87e1b3..b77b18fe5adc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -12,6 +12,7 @@ #include <linux/gpio/driver.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/module.h> #include <linux/of_irq.h> #include "mtk-eint.h" @@ -204,6 +205,7 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, return 0; } +EXPORT_SYMBOL_GPL(mtk_hw_set_value); int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int field, int *value) @@ -223,6 +225,7 @@ int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, return 0; } +EXPORT_SYMBOL_GPL(mtk_hw_get_value); static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) { @@ -361,6 +364,7 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) return mtk_eint_do_init(hw->eint); } +EXPORT_SYMBOL_GPL(mtk_build_eint); /* Revision 0 */ int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, @@ -380,6 +384,7 @@ int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set); int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *res) @@ -402,6 +407,7 @@ int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get); int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup) @@ -421,6 +427,7 @@ int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set); int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, int *res) @@ -440,6 +447,7 @@ int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get); /* Revision 1 */ int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, @@ -454,6 +462,7 @@ int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1); int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *res) @@ -471,6 +480,7 @@ int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1); int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup) @@ -490,6 +500,7 @@ int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1); int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -515,6 +526,7 @@ int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1); /* Combo for the following pull register type: * 1. PU + PD @@ -715,6 +727,7 @@ int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, out: return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, @@ -735,6 +748,7 @@ int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, out: return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo); /* Revision 0 */ int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, @@ -764,6 +778,7 @@ int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set); int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) @@ -788,6 +803,7 @@ int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get); /* Revision 1 */ int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, @@ -809,6 +825,7 @@ int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1); int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) @@ -826,18 +843,21 @@ int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1); int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 arg) { return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg); } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw); int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) { return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val); } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw); int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -878,6 +898,7 @@ int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set); int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -920,6 +941,7 @@ int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get); int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 arg) @@ -946,6 +968,7 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set); int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *val) @@ -969,3 +992,8 @@ int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); +MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs"); diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 3853ec3a2a8e..d006ce4c9238 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -10,6 +10,7 @@ */ #include <linux/gpio/driver.h> +#include <linux/module.h> #include <dt-bindings/pinctrl/mt65xx.h> #include "pinctrl-paris.h" @@ -633,6 +634,7 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, return len; } +EXPORT_SYMBOL_GPL(mtk_pctrl_show_one_pin); #define PIN_DBG_BUF_SZ 96 static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, @@ -1021,6 +1023,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, return 0; } +EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe); static int mtk_paris_pinctrl_suspend(struct device *device) { @@ -1040,3 +1043,6 @@ const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = { .suspend_noirq = mtk_paris_pinctrl_suspend, .resume_noirq = mtk_paris_pinctrl_resume, }; + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris"); diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index bbc919bef2bf..079f8ee8d353 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -549,6 +549,18 @@ static const struct pinconf_ops meson_pinconf_ops = { .is_generic = true, }; +static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio) +{ + struct meson_pinctrl *pc = gpiochip_get_data(chip); + int ret; + + ret = meson_pinconf_get_output(pc, gpio); + if (ret < 0) + return ret; + + return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false); @@ -591,6 +603,8 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) pc->chip.parent = pc->dev; pc->chip.request = gpiochip_generic_request; pc->chip.free = gpiochip_generic_free; + pc->chip.set_config = gpiochip_generic_config; + pc->chip.get_direction = meson_gpio_get_direction; pc->chip.direction_input = meson_gpio_direction_input; pc->chip.direction_output = meson_gpio_direction_output; pc->chip.get = meson_gpio_get; diff --git a/drivers/pinctrl/nomadik/pinctrl-ab8505.c b/drivers/pinctrl/nomadik/pinctrl-ab8505.c index 5e6e7d28390a..b93af1fb37f0 100644 --- a/drivers/pinctrl/nomadik/pinctrl-ab8505.c +++ b/drivers/pinctrl/nomadik/pinctrl-ab8505.c @@ -178,6 +178,7 @@ static const struct abx500_pingroup ab8505_groups[] = { AB8505_PIN_GROUP(gpio40_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(gpio41_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(uartrxdata_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio50_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(gpio52_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(gpio53_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B), diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c index b9246e0b4fe2..acad3887cc74 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c @@ -691,18 +691,21 @@ static const struct nmk_pingroup nmk_db8500_groups[] = { DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(kpskaskb_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(modem_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(kp_a_2, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc1dir_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A), @@ -760,7 +763,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = { DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C), @@ -955,6 +958,7 @@ static const struct nmk_function nmk_db8500_functions[] = { FUNCTION(spi0), FUNCTION(spi2), FUNCTION(remap), + FUNCTION(sbag), FUNCTION(ptm), FUNCTION(rf), FUNCTION(hx), diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index ca7bbe4164c0..ba25c4654391 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1343,8 +1343,6 @@ static const struct nmk_cfg_param nmk_cfg_params[] = { static int nmk_dt_pin_config(int index, int val, unsigned long *config) { - int ret = 0; - if (nmk_cfg_params[index].choice == NULL) *config = nmk_cfg_params[index].config; else { @@ -1354,7 +1352,7 @@ static int nmk_dt_pin_config(int index, int val, unsigned long *config) nmk_cfg_params[index].choice[val]; } } - return ret; + return 0; } static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c index f7dff4f14101..d1a7d9836787 100644 --- a/drivers/pinctrl/pinctrl-bm1880.c +++ b/drivers/pinctrl/pinctrl-bm1880.c @@ -408,6 +408,7 @@ static const struct bm1880_pctrl_group bm1880_pctrl_groups[] = { BM1880_PINCTRL_GRP(pwm34), BM1880_PINCTRL_GRP(pwm35), BM1880_PINCTRL_GRP(pwm36), + BM1880_PINCTRL_GRP(pwm37), BM1880_PINCTRL_GRP(i2c0), BM1880_PINCTRL_GRP(i2c1), BM1880_PINCTRL_GRP(i2c2), diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index e5dcf77fe43d..6a8d44504f94 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1977,6 +1977,25 @@ static const struct pinctrl_ops ingenic_pctlops = { .dt_free_map = pinconf_generic_dt_free_map, }; +static int ingenic_gpio_irq_request(struct irq_data *data) +{ + struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); + int ret; + + ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); + if (ret) + return ret; + + return gpiochip_reqres_irq(gpio_chip, data->hwirq); +} + +static void ingenic_gpio_irq_release(struct irq_data *data) +{ + struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); + + return gpiochip_relres_irq(gpio_chip, data->hwirq); +} + static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, int pin, int func) { @@ -2338,6 +2357,8 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; + jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; + jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; girq = &jzgc->gc.irq; diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c index aa92f141b865..626e02d7a1ba 100644 --- a/drivers/pinctrl/pinctrl-lantiq.c +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -221,7 +221,7 @@ static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux) return i; } -/* dont assume .mfp is linearly mapped. find the mfp with the correct .pin */ +/* don't assume .mfp is linearly mapped. find the mfp with the correct .pin */ static int match_mfp(const struct ltq_pinmux_info *info, int pin) { int i; diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 3a235487e38d..151931b593f6 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -1,34 +1,23 @@ // SPDX-License-Identifier: GPL-2.0-only /* MCP23S08 SPI/I2C GPIO driver */ +#include <linux/bitops.h> #include <linux/kernel.h> #include <linux/device.h> #include <linux/mutex.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> +#include <linux/export.h> #include <linux/gpio/driver.h> -#include <linux/i2c.h> -#include <linux/spi/spi.h> -#include <linux/spi/mcp23s08.h> #include <linux/slab.h> #include <asm/byteorder.h> #include <linux/interrupt.h> -#include <linux/of_device.h> #include <linux/regmap.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> -/* - * MCP types supported by driver - */ -#define MCP_TYPE_S08 0 -#define MCP_TYPE_S17 1 -#define MCP_TYPE_008 2 -#define MCP_TYPE_017 3 -#define MCP_TYPE_S18 4 -#define MCP_TYPE_018 5 - -#define MCP_MAX_DEV_PER_CS 8 +#include "pinctrl-mcp23s08.h" /* Registers are all 8 bits wide. * @@ -53,31 +42,6 @@ #define MCP_GPIO 0x09 #define MCP_OLAT 0x0a -struct mcp23s08; - -struct mcp23s08 { - u8 addr; - bool irq_active_high; - bool reg_shift; - - u16 irq_rise; - u16 irq_fall; - int irq; - bool irq_controller; - int cached_gpio; - /* lock protects regmap access with bypass/cache flags */ - struct mutex lock; - - struct gpio_chip chip; - struct irq_chip irq_chip; - - struct regmap *regmap; - struct device *dev; - - struct pinctrl_dev *pctldev; - struct pinctrl_desc pinctrl_desc; -}; - static const struct reg_default mcp23x08_defaults[] = { {.reg = MCP_IODIR, .def = 0xff}, {.reg = MCP_IPOL, .def = 0x00}, @@ -109,7 +73,7 @@ static const struct regmap_access_table mcp23x08_precious_table = { .n_yes_ranges = 1, }; -static const struct regmap_config mcp23x08_regmap = { +const struct regmap_config mcp23x08_regmap = { .reg_bits = 8, .val_bits = 8, @@ -121,6 +85,7 @@ static const struct regmap_config mcp23x08_regmap = { .cache_type = REGCACHE_FLAT, .max_register = MCP_OLAT, }; +EXPORT_SYMBOL_GPL(mcp23x08_regmap); static const struct reg_default mcp23x16_defaults[] = { {.reg = MCP_IODIR << 1, .def = 0xffff}, @@ -153,7 +118,7 @@ static const struct regmap_access_table mcp23x16_precious_table = { .n_yes_ranges = 1, }; -static const struct regmap_config mcp23x17_regmap = { +const struct regmap_config mcp23x17_regmap = { .reg_bits = 8, .val_bits = 16, @@ -166,6 +131,7 @@ static const struct regmap_config mcp23x17_regmap = { .cache_type = REGCACHE_FLAT, .val_format_endian = REGMAP_ENDIAN_LITTLE, }; +EXPORT_SYMBOL_GPL(mcp23x17_regmap); static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) { @@ -309,80 +275,6 @@ static const struct pinconf_ops mcp_pinconf_ops = { /*----------------------------------------------------------------------*/ -#ifdef CONFIG_SPI_MASTER - -static int mcp23sxx_spi_write(void *context, const void *data, size_t count) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - struct spi_message m; - struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, - { .tx_buf = data, .len = count, }, }; - - spi_message_init(&m); - spi_message_add_tail(&t[0], &m); - spi_message_add_tail(&t[1], &m); - - return spi_sync(spi, &m); -} - -static int mcp23sxx_spi_gather_write(void *context, - const void *reg, size_t reg_size, - const void *val, size_t val_size) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - struct spi_message m; - struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, - { .tx_buf = reg, .len = reg_size, }, - { .tx_buf = val, .len = val_size, }, }; - - spi_message_init(&m); - spi_message_add_tail(&t[0], &m); - spi_message_add_tail(&t[1], &m); - spi_message_add_tail(&t[2], &m); - - return spi_sync(spi, &m); -} - -static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, - void *val, size_t val_size) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - u8 tx[2]; - - if (reg_size != 1) - return -EINVAL; - - tx[0] = mcp->addr | 0x01; - tx[1] = *((u8 *) reg); - - return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); -} - -static const struct regmap_bus mcp23sxx_spi_regmap = { - .write = mcp23sxx_spi_write, - .gather_write = mcp23sxx_spi_gather_write, - .read = mcp23sxx_spi_read, -}; - -#endif /* CONFIG_SPI_MASTER */ - -/*----------------------------------------------------------------------*/ - -/* A given spi_device can represent up to eight mcp23sxx chips - * sharing the same chipselect but using different addresses - * (e.g. chips #0 and #3 might be populated, but not #1 or $2). - * Driver data holds all the per-chip data. - */ -struct mcp23s08_driver_data { - unsigned ngpio; - struct mcp23s08 *mcp[8]; - struct mcp23s08 chip[]; -}; - - static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) { struct mcp23s08 *mcp = gpiochip_get_data(chip); @@ -562,7 +454,6 @@ static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct mcp23s08 *mcp = gpiochip_get_data(gc); unsigned int pos = data->hwirq; - int status = 0; if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { mcp_set_bit(mcp, MCP_INTCON, pos, false); @@ -585,7 +476,7 @@ static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) } else return -EINVAL; - return status; + return 0; } static void mcp23s08_irq_bus_lock(struct irq_data *data) @@ -656,21 +547,25 @@ static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp) /*----------------------------------------------------------------------*/ -static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, - void *data, unsigned addr, unsigned type, - unsigned int base, int cs) +int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, + unsigned int addr, unsigned int type, unsigned int base) { int status, ret; bool mirror = false; bool open_drain = false; - struct regmap_config *one_regmap_config = NULL; - int raw_chip_address = (addr & ~0x40) >> 1; mutex_init(&mcp->lock); mcp->dev = dev; mcp->addr = addr; + mcp->irq_active_high = false; + mcp->irq_chip.name = dev_name(dev); + mcp->irq_chip.irq_mask = mcp23s08_irq_mask; + mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; + mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; + mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; + mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; mcp->chip.direction_input = mcp23s08_direction_input; mcp->chip.get = mcp23s08_get; @@ -681,83 +576,6 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, mcp->chip.of_node = dev->of_node; #endif - switch (type) { -#ifdef CONFIG_SPI_MASTER - case MCP_TYPE_S08: - case MCP_TYPE_S17: - switch (type) { - case MCP_TYPE_S08: - one_regmap_config = - devm_kmemdup(dev, &mcp23x08_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - mcp->reg_shift = 0; - mcp->chip.ngpio = 8; - mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, - "mcp23s08.%d", raw_chip_address); - break; - case MCP_TYPE_S17: - one_regmap_config = - devm_kmemdup(dev, &mcp23x17_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, - "mcp23s17.%d", raw_chip_address); - break; - } - if (!one_regmap_config) - return -ENOMEM; - - one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", raw_chip_address); - mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, - one_regmap_config); - break; - - case MCP_TYPE_S18: - one_regmap_config = - devm_kmemdup(dev, &mcp23x17_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - if (!one_regmap_config) - return -ENOMEM; - mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, - one_regmap_config); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23s18"; - break; -#endif /* CONFIG_SPI_MASTER */ - -#if IS_ENABLED(CONFIG_I2C) - case MCP_TYPE_008: - mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap); - mcp->reg_shift = 0; - mcp->chip.ngpio = 8; - mcp->chip.label = "mcp23008"; - break; - - case MCP_TYPE_017: - mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23017"; - break; - - case MCP_TYPE_018: - mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23018"; - break; -#endif /* CONFIG_I2C */ - - default: - dev_err(dev, "invalid device type (%d)\n", type); - return -EINVAL; - } - - if (IS_ERR(mcp->regmap)) - return PTR_ERR(mcp->regmap); - mcp->chip.base = base; mcp->chip.can_sleep = true; mcp->chip.parent = dev; @@ -816,14 +634,6 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, goto fail; } - if (one_regmap_config) { - mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, - "mcp23xxx-pinctrl.%d", raw_chip_address); - if (!mcp->pinctrl_desc.name) - return -ENOMEM; - } else { - mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; - } mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; mcp->pinctrl_desc.confops = &mcp_pinconf_ops; mcp->pinctrl_desc.npins = mcp->chip.ngpio; @@ -847,291 +657,5 @@ fail: dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); return ret; } - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_OF -#ifdef CONFIG_SPI_MASTER -static const struct of_device_id mcp23s08_spi_of_match[] = { - { - .compatible = "microchip,mcp23s08", - .data = (void *) MCP_TYPE_S08, - }, - { - .compatible = "microchip,mcp23s17", - .data = (void *) MCP_TYPE_S17, - }, - { - .compatible = "microchip,mcp23s18", - .data = (void *) MCP_TYPE_S18, - }, -/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ - { - .compatible = "mcp,mcp23s08", - .data = (void *) MCP_TYPE_S08, - }, - { - .compatible = "mcp,mcp23s17", - .data = (void *) MCP_TYPE_S17, - }, - { }, -}; -MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); -#endif - -#if IS_ENABLED(CONFIG_I2C) -static const struct of_device_id mcp23s08_i2c_of_match[] = { - { - .compatible = "microchip,mcp23008", - .data = (void *) MCP_TYPE_008, - }, - { - .compatible = "microchip,mcp23017", - .data = (void *) MCP_TYPE_017, - }, - { - .compatible = "microchip,mcp23018", - .data = (void *) MCP_TYPE_018, - }, -/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ - { - .compatible = "mcp,mcp23008", - .data = (void *) MCP_TYPE_008, - }, - { - .compatible = "mcp,mcp23017", - .data = (void *) MCP_TYPE_017, - }, - { }, -}; -MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); -#endif -#endif /* CONFIG_OF */ - - -#if IS_ENABLED(CONFIG_I2C) - -static int mcp230xx_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct mcp23s08_platform_data *pdata, local_pdata; - struct mcp23s08 *mcp; - int status; - - pdata = dev_get_platdata(&client->dev); - if (!pdata) { - pdata = &local_pdata; - pdata->base = -1; - } - - mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); - if (!mcp) - return -ENOMEM; - - mcp->irq = client->irq; - mcp->irq_chip.name = dev_name(&client->dev); - mcp->irq_chip.irq_mask = mcp23s08_irq_mask; - mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; - mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; - mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; - mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; - - status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, - id->driver_data, pdata->base, 0); - if (status) - return status; - - i2c_set_clientdata(client, mcp); - - return 0; -} - -static const struct i2c_device_id mcp230xx_id[] = { - { "mcp23008", MCP_TYPE_008 }, - { "mcp23017", MCP_TYPE_017 }, - { "mcp23018", MCP_TYPE_018 }, - { }, -}; -MODULE_DEVICE_TABLE(i2c, mcp230xx_id); - -static struct i2c_driver mcp230xx_driver = { - .driver = { - .name = "mcp230xx", - .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), - }, - .probe = mcp230xx_probe, - .id_table = mcp230xx_id, -}; - -static int __init mcp23s08_i2c_init(void) -{ - return i2c_add_driver(&mcp230xx_driver); -} - -static void mcp23s08_i2c_exit(void) -{ - i2c_del_driver(&mcp230xx_driver); -} - -#else - -static int __init mcp23s08_i2c_init(void) { return 0; } -static void mcp23s08_i2c_exit(void) { } - -#endif /* CONFIG_I2C */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SPI_MASTER - -static int mcp23s08_probe(struct spi_device *spi) -{ - struct mcp23s08_platform_data *pdata, local_pdata; - unsigned addr; - int chips = 0; - struct mcp23s08_driver_data *data; - int status, type; - unsigned ngpio = 0; - const struct of_device_id *match; - - match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); - if (match) - type = (int)(uintptr_t)match->data; - else - type = spi_get_device_id(spi)->driver_data; - - pdata = dev_get_platdata(&spi->dev); - if (!pdata) { - pdata = &local_pdata; - pdata->base = -1; - - status = device_property_read_u32(&spi->dev, - "microchip,spi-present-mask", &pdata->spi_present_mask); - if (status) { - status = device_property_read_u32(&spi->dev, - "mcp,spi-present-mask", - &pdata->spi_present_mask); - - if (status) { - dev_err(&spi->dev, "missing spi-present-mask"); - return -ENODEV; - } - } - } - - if (!pdata->spi_present_mask || pdata->spi_present_mask > 0xff) { - dev_err(&spi->dev, "invalid spi-present-mask"); - return -ENODEV; - } - - for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { - if (pdata->spi_present_mask & BIT(addr)) - chips++; - } - - if (!chips) - return -ENODEV; - - data = devm_kzalloc(&spi->dev, - struct_size(data, chip, chips), GFP_KERNEL); - if (!data) - return -ENOMEM; - - spi_set_drvdata(spi, data); - - for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { - if (!(pdata->spi_present_mask & BIT(addr))) - continue; - chips--; - data->mcp[addr] = &data->chip[chips]; - data->mcp[addr]->irq = spi->irq; - data->mcp[addr]->irq_chip.name = dev_name(&spi->dev); - data->mcp[addr]->irq_chip.irq_mask = mcp23s08_irq_mask; - data->mcp[addr]->irq_chip.irq_unmask = mcp23s08_irq_unmask; - data->mcp[addr]->irq_chip.irq_set_type = mcp23s08_irq_set_type; - data->mcp[addr]->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; - data->mcp[addr]->irq_chip.irq_bus_sync_unlock = - mcp23s08_irq_bus_unlock; - status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, - 0x40 | (addr << 1), type, - pdata->base, addr); - if (status < 0) - return status; - - if (pdata->base != -1) - pdata->base += data->mcp[addr]->chip.ngpio; - ngpio += data->mcp[addr]->chip.ngpio; - } - data->ngpio = ngpio; - - return 0; -} - -static const struct spi_device_id mcp23s08_ids[] = { - { "mcp23s08", MCP_TYPE_S08 }, - { "mcp23s17", MCP_TYPE_S17 }, - { "mcp23s18", MCP_TYPE_S18 }, - { }, -}; -MODULE_DEVICE_TABLE(spi, mcp23s08_ids); - -static struct spi_driver mcp23s08_driver = { - .probe = mcp23s08_probe, - .id_table = mcp23s08_ids, - .driver = { - .name = "mcp23s08", - .of_match_table = of_match_ptr(mcp23s08_spi_of_match), - }, -}; - -static int __init mcp23s08_spi_init(void) -{ - return spi_register_driver(&mcp23s08_driver); -} - -static void mcp23s08_spi_exit(void) -{ - spi_unregister_driver(&mcp23s08_driver); -} - -#else - -static int __init mcp23s08_spi_init(void) { return 0; } -static void mcp23s08_spi_exit(void) { } - -#endif /* CONFIG_SPI_MASTER */ - -/*----------------------------------------------------------------------*/ - -static int __init mcp23s08_init(void) -{ - int ret; - - ret = mcp23s08_spi_init(); - if (ret) - goto spi_fail; - - ret = mcp23s08_i2c_init(); - if (ret) - goto i2c_fail; - - return 0; - - i2c_fail: - mcp23s08_spi_exit(); - spi_fail: - return ret; -} -/* register after spi/i2c postcore initcall and before - * subsys initcalls that may rely on these GPIOs - */ -subsys_initcall(mcp23s08_init); - -static void __exit mcp23s08_exit(void) -{ - mcp23s08_spi_exit(); - mcp23s08_i2c_exit(); -} -module_exit(mcp23s08_exit); - +EXPORT_SYMBOL_GPL(mcp23s08_probe_one); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-mcp23s08.h b/drivers/pinctrl/pinctrl-mcp23s08.h new file mode 100644 index 000000000000..90dc27081a3c --- /dev/null +++ b/drivers/pinctrl/pinctrl-mcp23s08.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* MCP23S08 SPI/I2C GPIO driver */ + +#include <linux/gpio/driver.h> +#include <linux/irq.h> +#include <linux/mutex.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/types.h> + +/* + * MCP types supported by driver + */ +#define MCP_TYPE_S08 1 +#define MCP_TYPE_S17 2 +#define MCP_TYPE_008 3 +#define MCP_TYPE_017 4 +#define MCP_TYPE_S18 5 +#define MCP_TYPE_018 6 + +struct device; +struct regmap; + +struct pinctrl_dev; + +struct mcp23s08 { + u8 addr; + bool irq_active_high; + bool reg_shift; + + u16 irq_rise; + u16 irq_fall; + int irq; + bool irq_controller; + int cached_gpio; + /* lock protects regmap access with bypass/cache flags */ + struct mutex lock; + + struct gpio_chip chip; + struct irq_chip irq_chip; + + struct regmap *regmap; + struct device *dev; + + struct pinctrl_dev *pctldev; + struct pinctrl_desc pinctrl_desc; +}; + +extern const struct regmap_config mcp23x08_regmap; +extern const struct regmap_config mcp23x17_regmap; + +int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, + unsigned int addr, unsigned int type, unsigned int base); diff --git a/drivers/pinctrl/pinctrl-mcp23s08_i2c.c b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c new file mode 100644 index 000000000000..e0b001c8c08c --- /dev/null +++ b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* MCP23S08 I2C GPIO driver */ + +#include <linux/i2c.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/regmap.h> + +#include "pinctrl-mcp23s08.h" + +static int mcp230xx_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + unsigned int type = id->driver_data; + struct mcp23s08 *mcp; + int ret; + + mcp = devm_kzalloc(dev, sizeof(*mcp), GFP_KERNEL); + if (!mcp) + return -ENOMEM; + + switch (type) { + case MCP_TYPE_008: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x08_regmap); + mcp->reg_shift = 0; + mcp->chip.ngpio = 8; + mcp->chip.label = "mcp23008"; + break; + + case MCP_TYPE_017: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23017"; + break; + + case MCP_TYPE_018: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23018"; + break; + + default: + dev_err(dev, "invalid device type (%d)\n", type); + return -EINVAL; + } + + if (IS_ERR(mcp->regmap)) + return PTR_ERR(mcp->regmap); + + mcp->irq = client->irq; + mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; + + ret = mcp23s08_probe_one(mcp, dev, client->addr, type, -1); + if (ret) + return ret; + + i2c_set_clientdata(client, mcp); + + return 0; +} + +static const struct i2c_device_id mcp230xx_id[] = { + { "mcp23008", MCP_TYPE_008 }, + { "mcp23017", MCP_TYPE_017 }, + { "mcp23018", MCP_TYPE_018 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, mcp230xx_id); + +static const struct of_device_id mcp23s08_i2c_of_match[] = { + { + .compatible = "microchip,mcp23008", + .data = (void *) MCP_TYPE_008, + }, + { + .compatible = "microchip,mcp23017", + .data = (void *) MCP_TYPE_017, + }, + { + .compatible = "microchip,mcp23018", + .data = (void *) MCP_TYPE_018, + }, +/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ + { + .compatible = "mcp,mcp23008", + .data = (void *) MCP_TYPE_008, + }, + { + .compatible = "mcp,mcp23017", + .data = (void *) MCP_TYPE_017, + }, + { } +}; +MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); + +static struct i2c_driver mcp230xx_driver = { + .driver = { + .name = "mcp230xx", + .of_match_table = mcp23s08_i2c_of_match, + }, + .probe = mcp230xx_probe, + .id_table = mcp230xx_id, +}; + +static int __init mcp23s08_i2c_init(void) +{ + return i2c_add_driver(&mcp230xx_driver); +} + +/* + * Register after I²C postcore initcall and before + * subsys initcalls that may rely on these GPIOs. + */ +subsys_initcall(mcp23s08_i2c_init); + +static void mcp23s08_i2c_exit(void) +{ + i2c_del_driver(&mcp230xx_driver); +} +module_exit(mcp23s08_i2c_exit); + +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-mcp23s08_spi.c b/drivers/pinctrl/pinctrl-mcp23s08_spi.c new file mode 100644 index 000000000000..e06fb885fd2b --- /dev/null +++ b/drivers/pinctrl/pinctrl-mcp23s08_spi.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* MCP23S08 SPI GPIO driver */ + +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/property.h> +#include <linux/regmap.h> +#include <linux/spi/spi.h> + +#include "pinctrl-mcp23s08.h" + +#define MCP_MAX_DEV_PER_CS 8 + +/* + * A given spi_device can represent up to eight mcp23sxx chips + * sharing the same chipselect but using different addresses + * (e.g. chips #0 and #3 might be populated, but not #1 or #2). + * Driver data holds all the per-chip data. + */ +struct mcp23s08_driver_data { + unsigned ngpio; + struct mcp23s08 *mcp[8]; + struct mcp23s08 chip[]; +}; + +static int mcp23sxx_spi_write(void *context, const void *data, size_t count) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + struct spi_message m; + struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, + { .tx_buf = data, .len = count, }, }; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + + return spi_sync(spi, &m); +} + +static int mcp23sxx_spi_gather_write(void *context, + const void *reg, size_t reg_size, + const void *val, size_t val_size) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + struct spi_message m; + struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, + { .tx_buf = reg, .len = reg_size, }, + { .tx_buf = val, .len = val_size, }, }; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + spi_message_add_tail(&t[2], &m); + + return spi_sync(spi, &m); +} + +static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + u8 tx[2]; + + if (reg_size != 1) + return -EINVAL; + + tx[0] = mcp->addr | 0x01; + tx[1] = *((u8 *) reg); + + return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); +} + +static const struct regmap_bus mcp23sxx_spi_regmap = { + .write = mcp23sxx_spi_write, + .gather_write = mcp23sxx_spi_gather_write, + .read = mcp23sxx_spi_read, +}; + +static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, + unsigned int addr, unsigned int type) +{ + const struct regmap_config *config; + struct regmap_config *copy; + const char *name; + + switch (type) { + case MCP_TYPE_S08: + mcp->reg_shift = 0; + mcp->chip.ngpio = 8; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s08.%d", addr); + + config = &mcp23x08_regmap; + name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + break; + + case MCP_TYPE_S17: + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s17.%d", addr); + + config = &mcp23x17_regmap; + name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + break; + + case MCP_TYPE_S18: + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23s18"; + + config = &mcp23x17_regmap; + name = config->name; + break; + + default: + dev_err(dev, "invalid device type (%d)\n", type); + return -EINVAL; + } + + copy = devm_kmemdup(dev, &config, sizeof(config), GFP_KERNEL); + if (!copy) + return -ENOMEM; + + copy->name = name; + + mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, copy); + if (IS_ERR(mcp->regmap)) + return PTR_ERR(mcp->regmap); + + return 0; +} + +static int mcp23s08_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct mcp23s08_driver_data *data; + unsigned long spi_present_mask; + const void *match; + unsigned int addr; + unsigned int ngpio = 0; + int chips; + int type; + int ret; + u32 v; + + match = device_get_match_data(dev); + if (match) + type = (int)(uintptr_t)match; + else + type = spi_get_device_id(spi)->driver_data; + + ret = device_property_read_u32(dev, "microchip,spi-present-mask", &v); + if (ret) { + ret = device_property_read_u32(dev, "mcp,spi-present-mask", &v); + if (ret) { + dev_err(dev, "missing spi-present-mask"); + return ret; + } + } + spi_present_mask = v; + + if (!spi_present_mask || spi_present_mask >= BIT(MCP_MAX_DEV_PER_CS)) { + dev_err(dev, "invalid spi-present-mask"); + return -ENODEV; + } + + chips = hweight_long(spi_present_mask); + + data = devm_kzalloc(dev, struct_size(data, chip, chips), GFP_KERNEL); + if (!data) + return -ENOMEM; + + spi_set_drvdata(spi, data); + + for_each_set_bit(addr, &spi_present_mask, MCP_MAX_DEV_PER_CS) { + data->mcp[addr] = &data->chip[--chips]; + data->mcp[addr]->irq = spi->irq; + + ret = mcp23s08_spi_regmap_init(data->mcp[addr], dev, addr, type); + if (ret) + return ret; + + data->mcp[addr]->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, + "mcp23xxx-pinctrl.%d", + addr); + if (!data->mcp[addr]->pinctrl_desc.name) + return -ENOMEM; + + ret = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1), type, -1); + if (ret < 0) + return ret; + + ngpio += data->mcp[addr]->chip.ngpio; + } + data->ngpio = ngpio; + + return 0; +} + +static const struct spi_device_id mcp23s08_ids[] = { + { "mcp23s08", MCP_TYPE_S08 }, + { "mcp23s17", MCP_TYPE_S17 }, + { "mcp23s18", MCP_TYPE_S18 }, + { } +}; +MODULE_DEVICE_TABLE(spi, mcp23s08_ids); + +static const struct of_device_id mcp23s08_spi_of_match[] = { + { + .compatible = "microchip,mcp23s08", + .data = (void *) MCP_TYPE_S08, + }, + { + .compatible = "microchip,mcp23s17", + .data = (void *) MCP_TYPE_S17, + }, + { + .compatible = "microchip,mcp23s18", + .data = (void *) MCP_TYPE_S18, + }, +/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ + { + .compatible = "mcp,mcp23s08", + .data = (void *) MCP_TYPE_S08, + }, + { + .compatible = "mcp,mcp23s17", + .data = (void *) MCP_TYPE_S17, + }, + { } +}; +MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); + +static struct spi_driver mcp23s08_driver = { + .probe = mcp23s08_probe, + .id_table = mcp23s08_ids, + .driver = { + .name = "mcp23s08", + .of_match_table = mcp23s08_spi_of_match, + }, +}; + +static int __init mcp23s08_spi_init(void) +{ + return spi_register_driver(&mcp23s08_driver); +} + +/* + * Register after SPI postcore initcall and before + * subsys initcalls that may rely on these GPIOs. + */ +subsys_initcall(mcp23s08_spi_init); + +static void mcp23s08_spi_exit(void) +{ + spi_unregister_driver(&mcp23s08_driver); +} +module_exit(mcp23s08_spi_exit); + +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-rk805.c b/drivers/pinctrl/pinctrl-rk805.c index cccbe072274e..c6f4229eb106 100644 --- a/drivers/pinctrl/pinctrl-rk805.c +++ b/drivers/pinctrl/pinctrl-rk805.c @@ -73,7 +73,7 @@ struct rk805_pctrl_info { int num_pin_groups; const struct pinctrl_pin_desc *pins; unsigned int num_pins; - struct rk805_pin_config *pin_cfg; + const struct rk805_pin_config *pin_cfg; }; enum rk805_pinmux_option { @@ -121,7 +121,7 @@ static const struct rk805_pin_group rk805_pin_groups[] = { #define RK805_GPIO0_VAL_MSK BIT(0) #define RK805_GPIO1_VAL_MSK BIT(1) -static struct rk805_pin_config rk805_gpio_cfgs[] = { +static const struct rk805_pin_config rk805_gpio_cfgs[] = { { .reg = RK805_OUT_REG, .val_msk = RK805_GPIO0_VAL_MSK, diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 098951346339..c07324d1f265 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -508,8 +508,8 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, } map_num += grp->npins; - new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), - GFP_KERNEL); + + new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); if (!new_map) return -ENOMEM; @@ -519,7 +519,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, /* create mux map */ parent = of_get_parent(np); if (!parent) { - devm_kfree(pctldev->dev, new_map); + kfree(new_map); return -EINVAL; } new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; @@ -546,6 +546,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned num_maps) { + kfree(map); } static const struct pinctrl_ops rockchip_pctrl_ops = { @@ -2940,14 +2941,14 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, sizeof(struct rockchip_pmx_func), GFP_KERNEL); if (!info->functions) - return -EINVAL; + return -ENOMEM; info->groups = devm_kcalloc(dev, info->ngroups, sizeof(struct rockchip_pin_group), GFP_KERNEL); if (!info->groups) - return -EINVAL; + return -ENOMEM; i = 0; diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index da2d8365c690..ff4a7fb518bb 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -418,7 +418,7 @@ static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = { }; static const struct rza1_swio_entry rza1l_swio_entries[] = { - [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins }, + [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins }, }; /* RZ/A1L (r7s72102x) pinmux flags table */ diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 60100b45f5e5..1aae803c12cd 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -288,7 +288,7 @@ static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, struct pinctrl_gpio_range *range; enum pin_config_param param; u32 arg; - int dir, i, ret; + int i, ret; range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); if (!range) { @@ -296,10 +296,6 @@ static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, return -EINVAL; } - dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin); - if (dir < 0) - return dir; - for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(configs[i]); arg = pinconf_to_config_argument(configs[i]); diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 6e74bd87d959..708bc91862fe 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -988,7 +988,7 @@ static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl, /* * In order to mask the differences between 16 and 8 bit expander * devices we set up a sligthly ficticious regmap that pretends to be - * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh + * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh * pair/quartet) registers and transparently reconstructs those * registers via multiple I2C/SMBus reads * diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index c5d4428f1f94..ff1ee159dca2 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -216,4 +216,13 @@ config PINCTRL_SM8150 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8150 platform. +config PINCTRL_SM8250 + tristate "Qualcomm Technologies Inc SM8250 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM8250 platform. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index d9e09045a776..061ec9fb659b 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o +obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 9a398a211d30..898fc041e197 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -23,7 +23,6 @@ #include <linux/pm.h> #include <linux/log2.h> #include <linux/qcom_scm.h> -#include <linux/io.h> #include <linux/soc/qcom/irq.h> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c new file mode 100644 index 000000000000..a660f1274b66 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -0,0 +1,1361 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +static const char * const sm8250_tiles[] = { + "west", + "south", + "north", +}; + +enum { + WEST, + SOUTH, + NORTH, +}; + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = REG_SIZE * id + 0x4, \ + .intr_cfg_reg = REG_SIZE * id + 0x8, \ + .intr_status_reg = REG_SIZE * id + 0xc, \ + .intr_target_reg = REG_SIZE * id + 0x8, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = NORTH, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = SOUTH, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8250_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "SDC2_CLK"), + PINCTRL_PIN(181, "SDC2_CMD"), + PINCTRL_PIN(182, "SDC2_DATA"), + PINCTRL_PIN(183, "UFS_RESET"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); + +static const unsigned int ufs_reset_pins[] = { 180 }; +static const unsigned int sdc2_clk_pins[] = { 181 }; +static const unsigned int sdc2_cmd_pins[] = { 182 }; +static const unsigned int sdc2_data_pins[] = { 183 }; + +enum sm8250_functions { + msm_mux_aoss_cti, + msm_mux_atest, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_dp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_pci_e2, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_clk, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_sp_cmu, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif0_clk, + msm_mux_tsif0_data, + msm_mux_tsif0_en, + msm_mux_tsif0_error, + msm_mux_tsif0_sync, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const tsif1_data_groups[] = { + "gpio75", +}; +static const char * const sdc41_groups[] = { + "gpio75", +}; +static const char * const tsif1_sync_groups[] = { + "gpio76", +}; +static const char * const sdc40_groups[] = { + "gpio76", +}; +static const char * const aoss_cti_groups[] = { + "gpio77", +}; +static const char * const phase_flag_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio103", "gpio104", "gpio115", "gpio116", "gpio117", "gpio118", + "gpio119", "gpio120", "gpio122", "gpio124", "gpio125", +}; +static const char * const sd_write_groups[] = { + "gpio78", +}; +static const char * const pci_e0_groups[] = { + "gpio79", "gpio80", +}; +static const char * const pci_e1_groups[] = { + "gpio82", "gpio83", +}; +static const char * const pci_e2_groups[] = { + "gpio85", "gpio86", +}; +static const char * const tgu_ch0_groups[] = { + "gpio85", +}; +static const char * const atest_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio85", "gpio86", "gpio87", "gpio88", + "gpio89", +}; +static const char * const tgu_ch3_groups[] = { + "gpio86", +}; +static const char * const tsif1_error_groups[] = { + "gpio90", +}; +static const char * const tgu_ch1_groups[] = { + "gpio90", +}; +static const char * const tsif0_error_groups[] = { + "gpio91", +}; +static const char * const tgu_ch2_groups[] = { + "gpio91", +}; +static const char * const cam_mclk_groups[] = { + "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", +}; +static const char * const ddr_bist_groups[] = { + "gpio94", "gpio95", "gpio143", "gpio144", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio96", +}; +static const char * const pll_reset_groups[] = { + "gpio97", +}; +static const char * const cci_i2c_groups[] = { + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107", "gpio108", +}; +static const char * const qdss_gpio_groups[] = { + "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio160", + "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", + "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", + "gpio173", "gpio174", "gpio175", "gpio176", "gpio177", +}; +static const char * const gcc_gp1_groups[] = { + "gpio106", "gpio136", +}; +static const char * const gcc_gp2_groups[] = { + "gpio107", "gpio137", +}; +static const char * const gcc_gp3_groups[] = { + "gpio108", "gpio138", +}; +static const char * const cci_timer0_groups[] = { + "gpio109", +}; +static const char * const cci_timer1_groups[] = { + "gpio110", +}; +static const char * const cci_timer2_groups[] = { + "gpio111", +}; +static const char * const cci_timer3_groups[] = { + "gpio112", +}; +static const char * const cci_async_groups[] = { + "gpio112", "gpio113", "gpio114", +}; +static const char * const cci_timer4_groups[] = { + "gpio113", +}; +static const char * const qup2_groups[] = { + "gpio115", "gpio116", "gpio117", "gpio118", +}; +static const char * const qup3_groups[] = { + "gpio119", "gpio120", "gpio121", "gpio122", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio123", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio123", +}; +static const char * const qup9_groups[] = { + "gpio125", "gpio126", "gpio127", "gpio128", +}; +static const char * const qup10_groups[] = { + "gpio129", "gpio130", "gpio131", "gpio132", +}; +static const char * const mi2s2_sck_groups[] = { + "gpio133", +}; +static const char * const mi2s2_data0_groups[] = { + "gpio134", +}; +static const char * const mi2s2_ws_groups[] = { + "gpio135", +}; +static const char * const pri_mi2s_groups[] = { + "gpio136", +}; +static const char * const sec_mi2s_groups[] = { + "gpio137", +}; +static const char * const audio_ref_groups[] = { + "gpio137", +}; +static const char * const mi2s2_data1_groups[] = { + "gpio137", +}; +static const char * const mi2s0_sck_groups[] = { + "gpio138", +}; +static const char * const mi2s0_data0_groups[] = { + "gpio139", +}; +static const char * const mi2s0_data1_groups[] = { + "gpio140", +}; +static const char * const mi2s0_ws_groups[] = { + "gpio141", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio142", "gpio143", "gpio144", "gpio145", +}; +static const char * const mi2s1_sck_groups[] = { + "gpio142", +}; +static const char * const mi2s1_data0_groups[] = { + "gpio143", +}; +static const char * const mi2s1_data1_groups[] = { + "gpio144", +}; +static const char * const mi2s1_ws_groups[] = { + "gpio145", +}; +static const char * const cri_trng0_groups[] = { + "gpio159", +}; +static const char * const cri_trng1_groups[] = { + "gpio160", +}; +static const char * const cri_trng_groups[] = { + "gpio161", +}; +static const char * const sp_cmu_groups[] = { + "gpio162", +}; +static const char * const prng_rosc_groups[] = { + "gpio163", +}; +static const char * const qup19_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", +}; +static const char * const qdss_cti_groups[] = { + "gpio0", "gpio2", "gpio2", "gpio44", "gpio45", "gpio46", "gpio92", + "gpio93", +}; +static const char * const qup1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const ibi_i3c_groups[] = { + "gpio4", "gpio5", "gpio24", "gpio25", "gpio28", "gpio29", "gpio40", + "gpio41", +}; +static const char * const qup_l4_groups[] = { + "gpio6", "gpio14", "gpio46", "gpio123", +}; +static const char * const qup_l5_groups[] = { + "gpio7", "gpio15", "gpio47", "gpio124", +}; +static const char * const qup4_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const qup5_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const qup6_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const qup7_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const qup8_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const qup0_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const qup12_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; +static const char * const qup13_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const qup14_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio40", "gpio43", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio41", "gpio42", +}; +static const char * const vsense_trigger_groups[] = { + "gpio42", +}; +static const char * const qup15_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; +static const char * const dbg_out_groups[] = { + "gpio44", +}; +static const char * const qup16_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; +static const char * const qup17_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio52", "gpio53", +}; +static const char * const jitter_bist_groups[] = { + "gpio54", +}; +static const char * const pll_bist_groups[] = { + "gpio55", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio55", "gpio56", +}; +static const char * const qup18_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; +static const char * const qup11_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio64", "gpio90", +}; +static const char * const qup_l6_groups[] = { + "gpio64", "gpio77", "gpio92", "gpio93", +}; +static const char * const usb_phy_groups[] = { + "gpio65", +}; +static const char * const pll_clk_groups[] = { + "gpio65", +}; +static const char * const mdp_vsync_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio122", "gpio124", +}; +static const char * const dp_lcd_groups[] = { + "gpio67", +}; +static const char * const dp_hot_groups[] = { + "gpio68", +}; +static const char * const qspi_cs_groups[] = { + "gpio69", "gpio75", +}; +static const char * const tsif0_clk_groups[] = { + "gpio69", +}; +static const char * const qspi0_groups[] = { + "gpio70", +}; +static const char * const tsif0_en_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio70", +}; +static const char * const qspi1_groups[] = { + "gpio71", +}; +static const char * const tsif0_data_groups[] = { + "gpio71", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio71", +}; +static const char * const qspi2_groups[] = { + "gpio72", +}; +static const char * const tsif0_sync_groups[] = { + "gpio72", +}; +static const char * const sdc43_groups[] = { + "gpio72", +}; +static const char * const qspi_clk_groups[] = { + "gpio73", +}; +static const char * const tsif1_clk_groups[] = { + "gpio73", +}; +static const char * const sdc4_clk_groups[] = { + "gpio73", +}; +static const char * const qspi3_groups[] = { + "gpio74", +}; +static const char * const tsif1_en_groups[] = { + "gpio74", +}; +static const char * const sdc42_groups[] = { + "gpio74", +}; + +static const struct msm_function sm8250_functions[] = { + FUNCTION(aoss_cti), + FUNCTION(atest), + FUNCTION(audio_ref), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(dp_hot), + FUNCTION(dp_lcd), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gpio), + FUNCTION(ibi_i3c), + FUNCTION(jitter_bist), + FUNCTION(lpass_slimbus), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync0), + FUNCTION(mdp_vsync1), + FUNCTION(mdp_vsync2), + FUNCTION(mdp_vsync3), + FUNCTION(mi2s0_data0), + FUNCTION(mi2s0_data1), + FUNCTION(mi2s0_sck), + FUNCTION(mi2s0_ws), + FUNCTION(mi2s1_data0), + FUNCTION(mi2s1_data1), + FUNCTION(mi2s1_sck), + FUNCTION(mi2s1_ws), + FUNCTION(mi2s2_data0), + FUNCTION(mi2s2_data1), + FUNCTION(mi2s2_sck), + FUNCTION(mi2s2_ws), + FUNCTION(pci_e0), + FUNCTION(pci_e1), + FUNCTION(pci_e2), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_bypassnl), + FUNCTION(pll_clk), + FUNCTION(pll_reset), + FUNCTION(pri_mi2s), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qspi0), + FUNCTION(qspi1), + FUNCTION(qspi2), + FUNCTION(qspi3), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qup0), + FUNCTION(qup1), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(qup16), + FUNCTION(qup17), + FUNCTION(qup18), + FUNCTION(qup19), + FUNCTION(qup2), + FUNCTION(qup3), + FUNCTION(qup4), + FUNCTION(qup5), + FUNCTION(qup6), + FUNCTION(qup7), + FUNCTION(qup8), + FUNCTION(qup9), + FUNCTION(qup_l4), + FUNCTION(qup_l5), + FUNCTION(qup_l6), + FUNCTION(sd_write), + FUNCTION(sdc40), + FUNCTION(sdc41), + FUNCTION(sdc42), + FUNCTION(sdc43), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(sec_mi2s), + FUNCTION(sp_cmu), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(tgu_ch2), + FUNCTION(tgu_ch3), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(tsif0_clk), + FUNCTION(tsif0_data), + FUNCTION(tsif0_en), + FUNCTION(tsif0_error), + FUNCTION(tsif0_sync), + FUNCTION(tsif1_clk), + FUNCTION(tsif1_data), + FUNCTION(tsif1_en), + FUNCTION(tsif1_error), + FUNCTION(tsif1_sync), + FUNCTION(usb2phy_ac), + FUNCTION(usb_phy), + FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8250_groups[] = { + [0] = PINGROUP(0, SOUTH, qup19, qdss_cti, _, _, _, _, _, _, _), + [1] = PINGROUP(1, SOUTH, qup19, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, SOUTH, qup19, qdss_cti, qdss_cti, _, _, _, _, _, _), + [3] = PINGROUP(3, SOUTH, qup19, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _), + [5] = PINGROUP(5, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _), + [6] = PINGROUP(6, NORTH, qup1, qup_l4, _, _, _, _, _, _, _), + [7] = PINGROUP(7, NORTH, qup1, qup_l5, _, _, _, _, _, _, _), + [8] = PINGROUP(8, NORTH, qup4, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, NORTH, qup4, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, NORTH, qup4, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, NORTH, qup4, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, NORTH, qup5, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, NORTH, qup5, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, NORTH, qup5, qup_l4, _, _, _, _, _, _, _), + [15] = PINGROUP(15, NORTH, qup5, qup_l5, _, _, _, _, _, _, _), + [16] = PINGROUP(16, NORTH, qup6, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, NORTH, qup6, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, NORTH, qup6, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, NORTH, qup6, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, NORTH, qup7, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, NORTH, qup7, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, NORTH, qup7, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, NORTH, qup7, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _), + [25] = PINGROUP(25, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _), + [26] = PINGROUP(26, SOUTH, qup8, atest, _, _, _, _, _, _, _), + [27] = PINGROUP(27, SOUTH, qup8, atest, _, _, _, _, _, _, _), + [28] = PINGROUP(28, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _), + [29] = PINGROUP(29, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _), + [30] = PINGROUP(30, NORTH, qup0, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, NORTH, qup0, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, SOUTH, qup12, _, atest, _, _, _, _, _, _), + [33] = PINGROUP(33, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [34] = PINGROUP(34, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [35] = PINGROUP(35, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [36] = PINGROUP(36, SOUTH, qup13, atest, _, _, _, _, _, _, _), + [37] = PINGROUP(37, SOUTH, qup13, atest, _, _, _, _, _, _, _), + [38] = PINGROUP(38, SOUTH, qup13, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, SOUTH, qup13, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, SOUTH, qup14, ibi_i3c, _, ddr_pxi3, _, _, _, _, _), + [41] = PINGROUP(41, SOUTH, qup14, ibi_i3c, _, ddr_pxi1, _, _, _, _, _), + [42] = PINGROUP(42, SOUTH, qup14, vsense_trigger, ddr_pxi1, _, _, _, _, _, _), + [43] = PINGROUP(43, SOUTH, qup14, ddr_pxi3, _, _, _, _, _, _, _), + [44] = PINGROUP(44, SOUTH, qup15, qdss_cti, dbg_out, _, _, _, _, _, _), + [45] = PINGROUP(45, SOUTH, qup15, qdss_cti, phase_flag, _, _, _, _, _, _), + [46] = PINGROUP(46, SOUTH, qup15, qup_l4, qdss_cti, phase_flag, _, _, _, _, _), + [47] = PINGROUP(47, SOUTH, qup15, qup_l5, phase_flag, _, _, _, _, _, _), + [48] = PINGROUP(48, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [49] = PINGROUP(49, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [50] = PINGROUP(50, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [51] = PINGROUP(51, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [52] = PINGROUP(52, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _), + [53] = PINGROUP(53, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _), + [54] = PINGROUP(54, SOUTH, qup17, jitter_bist, _, _, _, _, _, _, _), + [55] = PINGROUP(55, SOUTH, qup17, pll_bist, ddr_pxi2, _, _, _, _, _, _), + [56] = PINGROUP(56, SOUTH, qup18, ddr_pxi2, _, _, _, _, _, _, _), + [57] = PINGROUP(57, SOUTH, qup18, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, SOUTH, qup18, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, SOUTH, qup18, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, SOUTH, qup11, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, SOUTH, qup11, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, SOUTH, qup11, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, SOUTH, qup11, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, SOUTH, usb2phy_ac, qup_l6, _, _, _, _, _, _, _), + [65] = PINGROUP(65, SOUTH, usb_phy, pll_clk, _, _, _, _, _, _, _), + [66] = PINGROUP(66, NORTH, mdp_vsync, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, NORTH, mdp_vsync, dp_lcd, _, _, _, _, _, _, _), + [68] = PINGROUP(68, NORTH, mdp_vsync, dp_hot, _, _, _, _, _, _, _), + [69] = PINGROUP(69, SOUTH, qspi_cs, tsif0_clk, phase_flag, _, _, _, _, _, _), + [70] = PINGROUP(70, SOUTH, qspi0, tsif0_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, phase_flag, _, _), + [71] = PINGROUP(71, SOUTH, qspi1, tsif0_data, sdc4_cmd, phase_flag, _, _, _, _, _), + [72] = PINGROUP(72, SOUTH, qspi2, tsif0_sync, sdc43, phase_flag, _, _, _, _, _), + [73] = PINGROUP(73, SOUTH, qspi_clk, tsif1_clk, sdc4_clk, phase_flag, _, _, _, _, _), + [74] = PINGROUP(74, SOUTH, qspi3, tsif1_en, sdc42, phase_flag, _, _, _, _, _), + [75] = PINGROUP(75, SOUTH, qspi_cs, tsif1_data, sdc41, _, _, _, _, _, _), + [76] = PINGROUP(76, SOUTH, tsif1_sync, sdc40, _, _, _, _, _, _, _), + [77] = PINGROUP(77, NORTH, qup_l6, aoss_cti, phase_flag, _, _, _, _, _, _), + [78] = PINGROUP(78, NORTH, sd_write, phase_flag, _, _, _, _, _, _, _), + [79] = PINGROUP(79, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _), + [80] = PINGROUP(80, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _), + [81] = PINGROUP(81, NORTH, phase_flag, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _), + [83] = PINGROUP(83, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _), + [84] = PINGROUP(84, NORTH, phase_flag, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, SOUTH, pci_e2, tgu_ch0, atest, _, _, _, _, _, _), + [86] = PINGROUP(86, SOUTH, pci_e2, tgu_ch3, atest, _, _, _, _, _, _), + [87] = PINGROUP(87, SOUTH, atest, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, SOUTH, _, atest, _, _, _, _, _, _, _), + [89] = PINGROUP(89, SOUTH, _, atest, _, _, _, _, _, _, _), + [90] = PINGROUP(90, SOUTH, tsif1_error, usb2phy_ac, tgu_ch1, _, _, _, _, _, _), + [91] = PINGROUP(91, SOUTH, tsif0_error, tgu_ch2, _, _, _, _, _, _, _), + [92] = PINGROUP(92, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _), + [93] = PINGROUP(93, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _), + [94] = PINGROUP(94, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _), + [95] = PINGROUP(95, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _), + [96] = PINGROUP(96, NORTH, cam_mclk, pll_bypassnl, qdss_gpio, _, _, _, _, _, _), + [97] = PINGROUP(97, NORTH, cam_mclk, pll_reset, qdss_gpio, _, _, _, _, _, _), + [98] = PINGROUP(98, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [99] = PINGROUP(99, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [100] = PINGROUP(100, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [101] = PINGROUP(101, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [102] = PINGROUP(102, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [103] = PINGROUP(103, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [104] = PINGROUP(104, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [105] = PINGROUP(105, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [106] = PINGROUP(106, NORTH, cci_i2c, gcc_gp1, qdss_gpio, _, _, _, _, _, _), + [107] = PINGROUP(107, NORTH, cci_i2c, gcc_gp2, qdss_gpio, _, _, _, _, _, _), + [108] = PINGROUP(108, NORTH, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _, _, _), + [109] = PINGROUP(109, NORTH, cci_timer0, qdss_gpio, _, _, _, _, _, _, _), + [110] = PINGROUP(110, NORTH, cci_timer1, qdss_gpio, _, _, _, _, _, _, _), + [111] = PINGROUP(111, NORTH, cci_timer2, qdss_gpio, _, _, _, _, _, _, _), + [112] = PINGROUP(112, NORTH, cci_timer3, cci_async, _, _, _, _, _, _, _), + [113] = PINGROUP(113, NORTH, cci_timer4, cci_async, _, _, _, _, _, _, _), + [114] = PINGROUP(114, NORTH, cci_async, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [116] = PINGROUP(116, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [117] = PINGROUP(117, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [118] = PINGROUP(118, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [119] = PINGROUP(119, NORTH, qup3, phase_flag, _, _, _, _, _, _, _), + [120] = PINGROUP(120, NORTH, qup3, phase_flag, _, _, _, _, _, _, _), + [121] = PINGROUP(121, NORTH, qup3, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, NORTH, qup3, mdp_vsync, phase_flag, _, _, _, _, _, _), + [123] = PINGROUP(123, NORTH, qup_l4, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), + [124] = PINGROUP(124, NORTH, qup_l5, mdp_vsync, phase_flag, _, _, _, _, _, _), + [125] = PINGROUP(125, SOUTH, qup9, phase_flag, _, _, _, _, _, _, _), + [126] = PINGROUP(126, SOUTH, qup9, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, SOUTH, qup9, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, SOUTH, qup9, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, SOUTH, qup10, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, SOUTH, qup10, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, SOUTH, qup10, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, SOUTH, qup10, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, WEST, mi2s2_sck, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, WEST, mi2s2_data0, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, WEST, mi2s2_ws, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, WEST, pri_mi2s, gcc_gp1, _, _, _, _, _, _, _), + [137] = PINGROUP(137, WEST, sec_mi2s, audio_ref, mi2s2_data1, gcc_gp2, _, _, _, _, _), + [138] = PINGROUP(138, WEST, mi2s0_sck, gcc_gp3, _, _, _, _, _, _, _), + [139] = PINGROUP(139, WEST, mi2s0_data0, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, WEST, mi2s0_data1, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, WEST, mi2s0_ws, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, WEST, lpass_slimbus, mi2s1_sck, _, _, _, _, _, _, _), + [143] = PINGROUP(143, WEST, lpass_slimbus, mi2s1_data0, ddr_bist, _, _, _, _, _, _), + [144] = PINGROUP(144, WEST, lpass_slimbus, mi2s1_data1, ddr_bist, _, _, _, _, _, _), + [145] = PINGROUP(145, WEST, lpass_slimbus, mi2s1_ws, _, _, _, _, _, _, _), + [146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, _), + [161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, _), + [162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, _), + [163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, _), + [164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _), + [180] = UFS_RESET(ufs_reset, 0xb8000), + [181] = SDC_PINGROUP(sdc2_clk, 0x7000, 14, 6), + [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3), + [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sm8250_pinctrl = { + .pins = sm8250_pins, + .npins = ARRAY_SIZE(sm8250_pins), + .functions = sm8250_functions, + .nfunctions = ARRAY_SIZE(sm8250_functions), + .groups = sm8250_groups, + .ngroups = ARRAY_SIZE(sm8250_groups), + .ngpios = 181, + .tiles = sm8250_tiles, + .ntiles = ARRAY_SIZE(sm8250_tiles), +}; + +static int sm8250_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8250_pinctrl); +} + +static const struct of_device_id sm8250_pinctrl_of_match[] = { + { .compatible = "qcom,sm8250-pinctrl", }, + { }, +}; + +static struct platform_driver sm8250_pinctrl_driver = { + .driver = { + .name = "sm8250-pinctrl", + .of_match_table = sm8250_pinctrl_of_match, + }, + .probe = sm8250_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8250_pinctrl_init(void) +{ + return platform_driver_register(&sm8250_pinctrl_driver); +} +arch_initcall(sm8250_pinctrl_init); + +static void __exit sm8250_pinctrl_exit(void) +{ + platform_driver_unregister(&sm8250_pinctrl_driver); +} +module_exit(sm8250_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sm8250 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match); diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index d20974a55d93..e2916aaa8304 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -1963,8 +1963,9 @@ static const struct pinmux_func pinmux_func_gpios[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* "name" addr register_size Field_Width */ - /* where Field_Width is 1 for single mode registers or 4 for upto 16 - mode registers and modes are described in assending order [0..16] */ + /* where Field_Width is 1 for single mode registers or 4 for up to 16 + * mode registers and modes are described in assending order [0..15] + */ { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP( 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c index 8a08c4afc6a8..9e5b61449999 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c @@ -103,8 +103,11 @@ static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev) rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(rstc)) { - dev_err(&pdev->dev, "Reset controller missing\n"); - return PTR_ERR(rstc); + ret = PTR_ERR(rstc); + if (ret == -EPROBE_DEFER) + return ret; + dev_err(&pdev->dev, "Reset controller missing err=%d\n", ret); + return ret; } ret = reset_control_deassert(rstc); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c index 6f7b3767f453..43922ab81666 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c @@ -123,7 +123,7 @@ static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl, unsigned *num_pins) { /* - * For the tegra-xusb pad controller groups are synonomous + * For the tegra-xusb pad controller groups are synonymous * with lanes/pins and there is always one lane/pin per group. */ *pins = &pinctrl->desc->pins[group].number; diff --git a/drivers/pinctrl/zte/pinctrl-zx.c b/drivers/pinctrl/zte/pinctrl-zx.c index 786bf89487d6..80d00ab8c110 100644 --- a/drivers/pinctrl/zte/pinctrl-zx.c +++ b/drivers/pinctrl/zte/pinctrl-zx.c @@ -94,7 +94,7 @@ static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, if (data->aon_pin) { /* * It's an AON pin, whose mux register offset and bit position - * can be caluculated from pin number. Each register covers 16 + * can be calculated from pin number. Each register covers 16 * pins, and each pin occupies 2 bits. */ u16 aoffset = pindesc->number / 16 * 4; |