diff options
Diffstat (limited to 'drivers/reset')
| -rw-r--r-- | drivers/reset/Kconfig | 14 | ||||
| -rw-r--r-- | drivers/reset/Makefile | 3 | ||||
| -rw-r--r-- | drivers/reset/reset-a10sr.c | 138 | ||||
| -rw-r--r-- | drivers/reset/reset-ath79.c | 27 | ||||
| -rw-r--r-- | drivers/reset/reset-imx7.c | 158 | ||||
| -rw-r--r-- | drivers/reset/reset-meson.c | 12 | ||||
| -rw-r--r-- | drivers/reset/reset-oxnas.c | 6 | ||||
| -rw-r--r-- | drivers/reset/reset-pistachio.c | 9 | ||||
| -rw-r--r-- | drivers/reset/reset-socfpga.c | 13 | ||||
| -rw-r--r-- | drivers/reset/reset-sunxi.c | 18 | ||||
| -rw-r--r-- | drivers/reset/reset-uniphier.c | 37 |
11 files changed, 373 insertions, 62 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index f4cdfe94b9ec..d21c07ccc94e 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -14,6 +14,13 @@ menuconfig RESET_CONTROLLER if RESET_CONTROLLER +config RESET_A10SR + tristate "Altera Arria10 System Resource Reset" + depends on MFD_ALTERA_A10SR + help + This option enables support for the external reset functions for + peripheral PHYs on the Altera Arria10 System Resource Chip. + config RESET_ATH79 bool "AR71xx Reset Driver" if COMPILE_TEST default ATH79 @@ -27,6 +34,13 @@ config RESET_BERLIN help This enables the reset controller driver for Marvell Berlin SoCs. +config RESET_IMX7 + bool "i.MX7 Reset Driver" if COMPILE_TEST + default SOC_IMX7D + select MFD_SYSCON + help + This enables the reset controller driver for i.MX7 SoCs. + config RESET_LPC18XX bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST default ARCH_LPC18XX diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 2cd3f6c45165..02a74db94339 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -2,8 +2,10 @@ obj-y += core.o obj-y += hisilicon/ obj-$(CONFIG_ARCH_STI) += sti/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ +obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o obj-$(CONFIG_RESET_ATH79) += reset-ath79.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o +obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o @@ -15,3 +17,4 @@ obj-$(CONFIG_TI_SYSCON_RESET) += reset-ti-syscon.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_ZX2967) += reset-zx2967.o obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o + diff --git a/drivers/reset/reset-a10sr.c b/drivers/reset/reset-a10sr.c new file mode 100644 index 000000000000..37496bd27fa2 --- /dev/null +++ b/drivers/reset/reset-a10sr.c @@ -0,0 +1,138 @@ +/* + * Copyright Intel Corporation (C) 2017. All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + * + * Reset driver for Altera Arria10 MAX5 System Resource Chip + * + * Adapted from reset-socfpga.c + */ + +#include <linux/err.h> +#include <linux/mfd/altera-a10sr.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> + +#include <dt-bindings/reset/altr,rst-mgr-a10sr.h> + +struct a10sr_reset { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static inline struct a10sr_reset *to_a10sr_rst(struct reset_controller_dev *rc) +{ + return container_of(rc, struct a10sr_reset, rcdev); +} + +static inline int a10sr_reset_shift(unsigned long id) +{ + switch (id) { + case A10SR_RESET_ENET_HPS: + return 1; + case A10SR_RESET_PCIE: + case A10SR_RESET_FILE: + case A10SR_RESET_BQSPI: + case A10SR_RESET_USB: + return id + 11; + default: + return -EINVAL; + } +} + +static int a10sr_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct a10sr_reset *a10r = to_a10sr_rst(rcdev); + int offset = a10sr_reset_shift(id); + u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); + int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset); + + return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask); +} + +static int a10sr_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return a10sr_reset_update(rcdev, id, true); +} + +static int a10sr_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return a10sr_reset_update(rcdev, id, false); +} + +static int a10sr_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + struct a10sr_reset *a10r = to_a10sr_rst(rcdev); + int offset = a10sr_reset_shift(id); + u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); + int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset); + unsigned int value; + + ret = regmap_read(a10r->regmap, index, &value); + if (ret < 0) + return ret; + + return !!(value & mask); +} + +static const struct reset_control_ops a10sr_reset_ops = { + .assert = a10sr_reset_assert, + .deassert = a10sr_reset_deassert, + .status = a10sr_reset_status, +}; + +static int a10sr_reset_probe(struct platform_device *pdev) +{ + struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent); + struct a10sr_reset *a10r; + + a10r = devm_kzalloc(&pdev->dev, sizeof(struct a10sr_reset), + GFP_KERNEL); + if (!a10r) + return -ENOMEM; + + a10r->rcdev.owner = THIS_MODULE; + a10r->rcdev.nr_resets = A10SR_RESET_NUM; + a10r->rcdev.ops = &a10sr_reset_ops; + a10r->rcdev.of_node = pdev->dev.of_node; + a10r->regmap = a10sr->regmap; + + platform_set_drvdata(pdev, a10r); + + return devm_reset_controller_register(&pdev->dev, &a10r->rcdev); +} + +static const struct of_device_id a10sr_reset_of_match[] = { + { .compatible = "altr,a10sr-reset" }, + { }, +}; +MODULE_DEVICE_TABLE(of, a10sr_reset_of_match); + +static struct platform_driver a10sr_reset_driver = { + .probe = a10sr_reset_probe, + .driver = { + .name = "altr_a10sr_reset", + }, +}; +module_platform_driver(a10sr_reset_driver); + +MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>"); +MODULE_DESCRIPTION("Altera Arria10 System Resource Reset Controller Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/reset/reset-ath79.c b/drivers/reset/reset-ath79.c index 6b97631f5489..2674880e5492 100644 --- a/drivers/reset/reset-ath79.c +++ b/drivers/reset/reset-ath79.c @@ -1,4 +1,7 @@ /* + * AR71xx Reset Controller Driver + * Author: Alban Bedel + * * Copyright (C) 2015 Alban Bedel <albeu@free.fr> * * This program is free software; you can redistribute it and/or modify @@ -13,7 +16,7 @@ */ #include <linux/io.h> -#include <linux/module.h> +#include <linux/init.h> #include <linux/platform_device.h> #include <linux/reset-controller.h> #include <linux/reboot.h> @@ -127,31 +130,17 @@ static int ath79_reset_probe(struct platform_device *pdev) return 0; } -static int ath79_reset_remove(struct platform_device *pdev) -{ - struct ath79_reset *ath79_reset = platform_get_drvdata(pdev); - - unregister_restart_handler(&ath79_reset->restart_nb); - - return 0; -} - static const struct of_device_id ath79_reset_dt_ids[] = { { .compatible = "qca,ar7100-reset", }, { }, }; -MODULE_DEVICE_TABLE(of, ath79_reset_dt_ids); static struct platform_driver ath79_reset_driver = { .probe = ath79_reset_probe, - .remove = ath79_reset_remove, .driver = { - .name = "ath79-reset", - .of_match_table = ath79_reset_dt_ids, + .name = "ath79-reset", + .of_match_table = ath79_reset_dt_ids, + .suppress_bind_attrs = true, }, }; -module_platform_driver(ath79_reset_driver); - -MODULE_AUTHOR("Alban Bedel <albeu@free.fr>"); -MODULE_DESCRIPTION("AR71xx Reset Controller Driver"); -MODULE_LICENSE("GPL"); +builtin_platform_driver(ath79_reset_driver); diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c new file mode 100644 index 000000000000..4db177bc89bc --- /dev/null +++ b/drivers/reset/reset-imx7.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 System Reset Controller (SRC) driver + * + * Author: Andrey Smirnov <andrew.smirnov@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/mfd/syscon.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> +#include <linux/regmap.h> +#include <dt-bindings/reset/imx7-reset.h> + +struct imx7_src { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +enum imx7_src_registers { + SRC_A7RCR0 = 0x0004, + SRC_M4RCR = 0x000c, + SRC_ERCR = 0x0014, + SRC_HSICPHY_RCR = 0x001c, + SRC_USBOPHY1_RCR = 0x0020, + SRC_USBOPHY2_RCR = 0x0024, + SRC_MIPIPHY_RCR = 0x0028, + SRC_PCIEPHY_RCR = 0x002c, + SRC_DDRC_RCR = 0x1000, +}; + +struct imx7_src_signal { + unsigned int offset, bit; +}; + +static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = { + [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) }, + [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) }, + [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) }, + [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) }, + [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) }, + [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) }, + [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) }, + [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) }, + [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) }, + [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) }, + [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) }, + [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) }, + [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) }, + [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) }, + [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) }, + [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) }, + [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) }, + [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) }, + [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) }, + [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) }, + [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) }, + [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, + [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, + [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) }, + [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) }, +}; + +static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct imx7_src, rcdev); +} + +static int imx7_reset_set(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct imx7_src *imx7src = to_imx7_src(rcdev); + const struct imx7_src_signal *signal = &imx7_src_signals[id]; + unsigned int value = 0; + + switch (id) { + case IMX7_RESET_PCIEPHY: + /* + * wait for more than 10us to release phy g_rst and + * btnrst + */ + if (!assert) + udelay(10); + break; + + case IMX7_RESET_PCIE_CTRL_APPS_EN: + value = (assert) ? 0 : signal->bit; + break; + } + + return regmap_update_bits(imx7src->regmap, + signal->offset, signal->bit, value); +} + +static int imx7_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx7_reset_set(rcdev, id, true); +} + +static int imx7_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx7_reset_set(rcdev, id, false); +} + +static const struct reset_control_ops imx7_reset_ops = { + .assert = imx7_reset_assert, + .deassert = imx7_reset_deassert, +}; + +static int imx7_reset_probe(struct platform_device *pdev) +{ + struct imx7_src *imx7src; + struct device *dev = &pdev->dev; + struct regmap_config config = { .name = "src" }; + + imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL); + if (!imx7src) + return -ENOMEM; + + imx7src->regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(imx7src->regmap)) { + dev_err(dev, "Unable to get imx7-src regmap"); + return PTR_ERR(imx7src->regmap); + } + regmap_attach_dev(dev, imx7src->regmap, &config); + + imx7src->rcdev.owner = THIS_MODULE; + imx7src->rcdev.nr_resets = IMX7_RESET_NUM; + imx7src->rcdev.ops = &imx7_reset_ops; + imx7src->rcdev.of_node = dev->of_node; + + return devm_reset_controller_register(dev, &imx7src->rcdev); +} + +static const struct of_device_id imx7_reset_dt_ids[] = { + { .compatible = "fsl,imx7d-src", }, + { /* sentinel */ }, +}; + +static struct platform_driver imx7_reset_driver = { + .probe = imx7_reset_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = imx7_reset_dt_ids, + }, +}; +builtin_platform_driver(imx7_reset_driver); diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index c32f11a30c5f..a8b915eb8b58 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -1,4 +1,6 @@ /* + * Amlogic Meson Reset Controller driver + * * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * @@ -53,7 +55,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include <linux/err.h> -#include <linux/module.h> +#include <linux/init.h> #include <linux/io.h> #include <linux/of.h> #include <linux/platform_device.h> @@ -95,7 +97,6 @@ static const struct of_device_id meson_reset_dt_ids[] = { { .compatible = "amlogic,meson-gxbb-reset", }, { /* sentinel */ }, }; -MODULE_DEVICE_TABLE(of, meson_reset_dt_ids); static int meson_reset_probe(struct platform_device *pdev) { @@ -128,9 +129,4 @@ static struct platform_driver meson_reset_driver = { .of_match_table = meson_reset_dt_ids, }, }; - -module_platform_driver(meson_reset_driver); - -MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); -MODULE_DESCRIPTION("Amlogic Meson Reset Controller driver"); -MODULE_LICENSE("Dual BSD/GPL"); +builtin_platform_driver(meson_reset_driver); diff --git a/drivers/reset/reset-oxnas.c b/drivers/reset/reset-oxnas.c index 0d9036dea010..cf5b9742b86e 100644 --- a/drivers/reset/reset-oxnas.c +++ b/drivers/reset/reset-oxnas.c @@ -18,7 +18,7 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/err.h> -#include <linux/module.h> +#include <linux/init.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/reset-controller.h> @@ -83,7 +83,6 @@ static const struct of_device_id oxnas_reset_dt_ids[] = { { .compatible = "oxsemi,ox820-reset", }, { /* sentinel */ }, }; -MODULE_DEVICE_TABLE(of, oxnas_reset_dt_ids); static int oxnas_reset_probe(struct platform_device *pdev) { @@ -123,5 +122,4 @@ static struct platform_driver oxnas_reset_driver = { .of_match_table = oxnas_reset_dt_ids, }, }; - -module_platform_driver(oxnas_reset_driver); +builtin_platform_driver(oxnas_reset_driver); diff --git a/drivers/reset/reset-pistachio.c b/drivers/reset/reset-pistachio.c index bbc4c06dd33b..11d651b44e81 100644 --- a/drivers/reset/reset-pistachio.c +++ b/drivers/reset/reset-pistachio.c @@ -10,7 +10,7 @@ * version 2, as published by the Free Software Foundation. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> @@ -128,7 +128,6 @@ static const struct of_device_id pistachio_reset_dt_ids[] = { { .compatible = "img,pistachio-reset", }, { /* sentinel */ }, }; -MODULE_DEVICE_TABLE(of, pistachio_reset_dt_ids); static struct platform_driver pistachio_reset_driver = { .probe = pistachio_reset_probe, @@ -137,8 +136,4 @@ static struct platform_driver pistachio_reset_driver = { .of_match_table = pistachio_reset_dt_ids, }, }; -module_platform_driver(pistachio_reset_driver); - -MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>"); -MODULE_DESCRIPTION("Pistacho Reset Controller Driver"); -MODULE_LICENSE("GPL v2"); +builtin_platform_driver(pistachio_reset_driver); diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 43e4a9f39b9b..07224c019892 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -25,7 +25,8 @@ #include <linux/spinlock.h> #include <linux/types.h> -#define NR_BANKS 4 +#define BANK_INCREMENT 4 +#define NR_BANKS 8 struct socfpga_reset_data { spinlock_t lock; @@ -46,8 +47,8 @@ static int socfpga_reset_assert(struct reset_controller_dev *rcdev, spin_lock_irqsave(&data->lock, flags); - reg = readl(data->membase + (bank * NR_BANKS)); - writel(reg | BIT(offset), data->membase + (bank * NR_BANKS)); + reg = readl(data->membase + (bank * BANK_INCREMENT)); + writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT)); spin_unlock_irqrestore(&data->lock, flags); return 0; @@ -67,8 +68,8 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev, spin_lock_irqsave(&data->lock, flags); - reg = readl(data->membase + (bank * NR_BANKS)); - writel(reg & ~BIT(offset), data->membase + (bank * NR_BANKS)); + reg = readl(data->membase + (bank * BANK_INCREMENT)); + writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT)); spin_unlock_irqrestore(&data->lock, flags); @@ -84,7 +85,7 @@ static int socfpga_reset_status(struct reset_controller_dev *rcdev, int offset = id % BITS_PER_LONG; u32 reg; - reg = readl(data->membase + (bank * NR_BANKS)); + reg = readl(data->membase + (bank * BANK_INCREMENT)); return !(reg & BIT(offset)); } diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c index b44f6b5f87b6..cd585cd2f04d 100644 --- a/drivers/reset/reset-sunxi.c +++ b/drivers/reset/reset-sunxi.c @@ -34,15 +34,16 @@ static int sunxi_reset_assert(struct reset_controller_dev *rcdev, struct sunxi_reset_data *data = container_of(rcdev, struct sunxi_reset_data, rcdev); - int bank = id / BITS_PER_LONG; - int offset = id % BITS_PER_LONG; + int reg_width = sizeof(u32); + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); unsigned long flags; u32 reg; spin_lock_irqsave(&data->lock, flags); - reg = readl(data->membase + (bank * 4)); - writel(reg & ~BIT(offset), data->membase + (bank * 4)); + reg = readl(data->membase + (bank * reg_width)); + writel(reg & ~BIT(offset), data->membase + (bank * reg_width)); spin_unlock_irqrestore(&data->lock, flags); @@ -55,15 +56,16 @@ static int sunxi_reset_deassert(struct reset_controller_dev *rcdev, struct sunxi_reset_data *data = container_of(rcdev, struct sunxi_reset_data, rcdev); - int bank = id / BITS_PER_LONG; - int offset = id % BITS_PER_LONG; + int reg_width = sizeof(u32); + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); unsigned long flags; u32 reg; spin_lock_irqsave(&data->lock, flags); - reg = readl(data->membase + (bank * 4)); - writel(reg | BIT(offset), data->membase + (bank * 4)); + reg = readl(data->membase + (bank * reg_width)); + writel(reg | BIT(offset), data->membase + (bank * reg_width)); spin_unlock_irqrestore(&data->lock, flags); diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 9c11be3d3450..c4ba89832796 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -50,6 +50,15 @@ struct uniphier_reset_data { } /* System reset data */ +#define UNIPHIER_SLD3_SYS_RESET_NAND(id) \ + UNIPHIER_RESETX((id), 0x2004, 2) + +#define UNIPHIER_LD11_SYS_RESET_NAND(id) \ + UNIPHIER_RESETX((id), 0x200c, 0) + +#define UNIPHIER_LD11_SYS_RESET_EMMC(id) \ + UNIPHIER_RESETX((id), 0x200c, 2) + #define UNIPHIER_SLD3_SYS_RESET_STDMAC(id) \ UNIPHIER_RESETX((id), 0x2000, 10) @@ -65,12 +74,14 @@ struct uniphier_reset_data { #define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \ UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17) -const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = { + UNIPHIER_SLD3_SYS_RESET_NAND(2), UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */ UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { + UNIPHIER_SLD3_SYS_RESET_NAND(2), UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), @@ -78,7 +89,8 @@ const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { + UNIPHIER_SLD3_SYS_RESET_NAND(2), UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), @@ -86,7 +98,8 @@ const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { + UNIPHIER_SLD3_SYS_RESET_NAND(2), UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), @@ -100,12 +113,16 @@ const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { + UNIPHIER_LD11_SYS_RESET_NAND(2), + UNIPHIER_LD11_SYS_RESET_EMMC(4), UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */ UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { +static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { + UNIPHIER_LD11_SYS_RESET_NAND(2), + UNIPHIER_LD11_SYS_RESET_EMMC(4), UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */ UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */ UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ @@ -134,7 +151,7 @@ const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { #define UNIPHIER_MIO_RESET_DMAC(id) \ UNIPHIER_RESETX((id), 0x110, 17) -const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = { +static const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = { UNIPHIER_MIO_RESET_SD(0, 0), UNIPHIER_MIO_RESET_SD(1, 1), UNIPHIER_MIO_RESET_SD(2, 2), @@ -154,7 +171,7 @@ const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = { UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = { +static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = { UNIPHIER_MIO_RESET_SD(0, 0), UNIPHIER_MIO_RESET_SD(1, 1), UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1), @@ -171,7 +188,7 @@ const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = { #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ UNIPHIER_RESETX((id), 0x114, 24 + (ch)) -const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { +static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { UNIPHIER_PERI_RESET_UART(0, 0), UNIPHIER_PERI_RESET_UART(1, 1), UNIPHIER_PERI_RESET_UART(2, 2), @@ -184,7 +201,7 @@ const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { UNIPHIER_RESET_END, }; -const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { +static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { UNIPHIER_PERI_RESET_UART(0, 0), UNIPHIER_PERI_RESET_UART(1, 1), UNIPHIER_PERI_RESET_UART(2, 2), |