diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf527')
| -rw-r--r-- | include/asm-blackfin/mach-bf527/anomaly.h | 80 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/bfin_serial_5xx.h | 48 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/bfin_sir.h | 133 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/blackfin.h | 15 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/cdefBF52x_base.h | 90 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/dma.h | 3 |
6 files changed, 300 insertions, 69 deletions
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h index a89120445be6..735fa02fafb2 100644 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ b/include/asm-blackfin/mach-bf527/anomaly.h @@ -2,12 +2,12 @@ * File: include/asm-blackfin/mach-bf527/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -15,35 +15,85 @@ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ #define ANOMALY_05000328 (1) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ #define ANOMALY_05000337 (1) -/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */ +/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ +#define ANOMALY_05000341 (1) +/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ #define ANOMALY_05000342 (1) -/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ +/* USB Calibration Value Is Not Initialized */ +#define ANOMALY_05000346 (1) +/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ #define ANOMALY_05000347 (1) +/* Security Features Are Not Functional */ +#define ANOMALY_05000348 (__SILICON_REVISION__ < 1) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (1) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* Incorrect Revision Number in DSPID Register */ +#define ANOMALY_05000364 (__SILICON_REVISION__ > 0) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* New Feature: Higher Default CCLK Rate */ +#define ANOMALY_05000368 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) +/* Authentication Fails To Initiate */ +#define ANOMALY_05000376 (__SILICON_REVISION__ > 0) +/* Data Read From L3 Memory by USB DMA May be Corrupted */ +#define ANOMALY_05000380 (1) +/* USB Full-speed Mode not Fully Tested */ +#define ANOMALY_05000381 (1) +/* New Feature: Boot from OTP Memory */ +#define ANOMALY_05000385 (1) +/* New Feature: bfrom_SysControl() Routine */ +#define ANOMALY_05000386 (1) +/* New Feature: Programmable Preboot Settings */ +#define ANOMALY_05000387 (1) +/* Reset Vector Must Not Be in SDRAM Memory Space */ +#define ANOMALY_05000389 (1) +/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */ +#define ANOMALY_05000392 (1) +/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000393 (1) +/* New Feature: Log Buffer Functionality */ +#define ANOMALY_05000394 (1) +/* New Feature: Hook Routine Functionality */ +#define ANOMALY_05000395 (1) +/* New Feature: Header Indirect Bit */ +#define ANOMALY_05000396 (1) +/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */ +#define ANOMALY_05000397 (1) +/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */ +#define ANOMALY_05000398 (1) +/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */ +#define ANOMALY_05000399 (1) +/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ +#define ANOMALY_05000401 (1) /* Anomalies that don't exist on this proc */ -#define ANOMALY_05000323 (0) -#define ANOMALY_05000244 (0) -#define ANOMALY_05000198 (0) #define ANOMALY_05000125 (0) #define ANOMALY_05000158 (0) -#define ANOMALY_05000273 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000244 (0) +#define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) -#define ANOMALY_05000230 (0) +#define ANOMALY_05000312 (0) +#define ANOMALY_05000323 (0) +#define ANOMALY_05000363 (0) + #endif diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h index c0694ecd2ecd..f0ab2736a680 100644 --- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h @@ -1,22 +1,38 @@ +/* + * file: include/asm-blackfin/mach-bf527/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver head file + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + #include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define NR_PORTS 2 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) @@ -92,7 +108,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) bfin_write16(uart->port.membase + OFFSET_LSR, -1); } -struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; diff --git a/include/asm-blackfin/mach-bf527/bfin_sir.h b/include/asm-blackfin/mach-bf527/bfin_sir.h new file mode 100644 index 000000000000..0612d0c9501c --- /dev/null +++ b/include/asm-blackfin/mach-bf527/bfin_sir.h @@ -0,0 +1,133 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include <linux/serial.h> +#include <asm/dma.h> +#include <asm/portmux.h> + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART0_RX, + CH_UART0_RX, + CH_UART0_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + 0xFFC02000, + IRQ_UART1_RX, + CH_UART1_RX, + CH_UART1_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) +{ + unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); + port->lsr |= (lsr & (BI|FE|PE|OE)); + return lsr | port->lsr; +} + +static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) +{ + port->lsr = 0; + bfin_read16(port->membase + OFFSET_LSR); +} + +#define DRIVER_NAME "bfin_sir" + +static void bfin_sir_hw_init(void) +{ +#ifdef CONFIG_BFIN_SIR0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_BFIN_SIR1 + peripheral_request(P_UART1_TX, DRIVER_NAME); + peripheral_request(P_UART1_RX, DRIVER_NAME); +#endif + SSYNC(); +} diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h index 1bd07e30781c..2891727b6176 100644 --- a/include/asm-blackfin/mach-bf527/blackfin.h +++ b/include/asm-blackfin/mach-bf527/blackfin.h @@ -64,6 +64,21 @@ #define STATUS_P1 0x02 #define STATUS_P0 0x01 +#define BFIN_UART_NR_PORTS 2 + +#define OFFSET_THR 0x00 /* Transmit Holding register */ +#define OFFSET_RBR 0x00 /* Receive Buffer register */ +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_IER 0x04 /* Interrupt Enable Register */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_GCTL 0x24 /* Global Control Register */ + /* DPMC*/ #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h index 3f4de5d9d4cb..9dbdbec8ea1b 100644 --- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h +++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h @@ -29,18 +29,71 @@ */ #ifndef _CDEF_BF52X_H +#define _CDEF_BF52X_H + +#include <asm/system.h> +#include <asm/blackfin.h> #include "defBF52x_base.h" +/* Include core specific register pointer definitions */ +#include <asm/mach-common/cdef_LPBlackfin.h> + /* ==== begin from cdefBF534.h ==== */ /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + local_irq_restore(flags); +} #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +/* Writing to VR_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_VR_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + + bfin_write16(VR_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + local_irq_restore(flags); +} #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) @@ -873,39 +926,6 @@ /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) - /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ #define bfin_read_PORTGIO() bfin_read16(PORTGIO) diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h index 2dfee12864f6..49dd693223e8 100644 --- a/include/asm-blackfin/mach-bf527/dma.h +++ b/include/asm-blackfin/mach-bf527/dma.h @@ -59,7 +59,4 @@ #define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */ #endif -extern int channel2irq(unsigned int channel); -extern struct dma_register *base_addr[]; - #endif |