diff options
Diffstat (limited to 'include/asm-blackfin')
28 files changed, 222 insertions, 129 deletions
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 716df7c85923..76033831eb35 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -37,7 +37,9 @@ #include <linux/linkage.h> #include <linux/types.h> -#if defined(CONFIG_DMA_UNCACHED_2M) +#if defined(CONFIG_DMA_UNCACHED_4M) +# define DMA_UNCACHED_REGION (4 * 1024 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_2M) # define DMA_UNCACHED_REGION (2 * 1024 * 1024) #elif defined(CONFIG_DMA_UNCACHED_1M) # define DMA_UNCACHED_REGION (1024 * 1024) @@ -103,13 +105,6 @@ extern int sram_free(const void*); extern void *sram_alloc_with_lsl(size_t, unsigned long); extern int sram_free_with_lsl(const void*); -extern void led_on(int); -extern void led_off(int); -extern void led_toggle(int); -extern void led_disp_num(int); -extern void led_toggle_num(int); -extern void init_leds(void); - extern const char bfin_board_name[]; extern unsigned long wall_jiffies; diff --git a/include/asm-blackfin/checksum.h b/include/asm-blackfin/checksum.h index 2638f2586d2f..6f6af2b8e9e0 100644 --- a/include/asm-blackfin/checksum.h +++ b/include/asm-blackfin/checksum.h @@ -15,7 +15,7 @@ * * it's best to have buff aligned on a 32-bit boundary */ -unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum); +__wsum csum_partial(const void *buff, int len, __wsum sum); /* * the same as csum_partial, but copies from src while it @@ -25,8 +25,8 @@ unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum); * better 64-bit) boundary */ -unsigned int csum_partial_copy(const unsigned char *src, unsigned char *dst, - int len, int sum); +__wsum csum_partial_copy(const void *src, void *dst, + int len, __wsum sum); /* * the same as csum_partial_copy, but copies from user space. @@ -35,20 +35,19 @@ unsigned int csum_partial_copy(const unsigned char *src, unsigned char *dst, * better 64-bit) boundary */ -extern unsigned int csum_partial_copy_from_user(const unsigned char *src, - unsigned char *dst, int len, - int sum, int *csum_err); +extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst, + int len, __wsum sum, int *csum_err); #define csum_partial_copy_nocheck(src, dst, len, sum) \ csum_partial_copy((src), (dst), (len), (sum)) -unsigned short ip_fast_csum(unsigned char *iph, unsigned int ihl); +__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl); /* * Fold a partial checksum */ -static inline unsigned int csum_fold(unsigned int sum) +static inline __sum16 csum_fold(__wsum sum) { while (sum >> 16) sum = (sum & 0xffff) + (sum >> 16); @@ -60,9 +59,9 @@ static inline unsigned int csum_fold(unsigned int sum) * returns a 16-bit checksum, already complemented */ -static inline unsigned int -csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, unsigned short len, - unsigned short proto, unsigned int sum) +static inline __wsum +csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) { __asm__ ("%0 = %0 + %1;\n\t" @@ -84,9 +83,9 @@ csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, unsigned short len, return (sum); } -static inline unsigned short int -csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len, - unsigned short proto, unsigned int sum) +static inline __sum16 +csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) { return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum)); } @@ -96,6 +95,6 @@ csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len, * in icmp.c */ -extern unsigned short ip_compute_csum(const unsigned char *buff, int len); +extern __sum16 ip_compute_csum(const void *buff, int len); #endif /* _BFIN_CHECKSUM_H */ diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h index 686cf83a5269..7f34cd384f12 100644 --- a/include/asm-blackfin/dpmc.h +++ b/include/asm-blackfin/dpmc.h @@ -1,7 +1,7 @@ /* * include/asm-blackfin/dpmc.h - Miscellaneous IOCTL commands for Dynamic Power * Management Controller Driver. - * Copyright (C) 2004 Analog Device Inc. + * Copyright (C) 2004-2008 Analog Device Inc. * */ #ifndef _BLACKFIN_DPMC_H_ @@ -65,6 +65,14 @@ void disable_wdog_timer(void); extern unsigned long get_cclk(void); extern unsigned long get_sclk(void); +struct bfin_dpmc_platform_data { + const unsigned int *tuple_tab; + unsigned short tabsize; + unsigned short vr_settling_time; /* in us */ +}; + +#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16)) + #endif /* __KERNEL__ */ #endif /*_BLACKFIN_DPMC_H_*/ diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h index 562c6d3a3232..c4f721e0d00d 100644 --- a/include/asm-blackfin/entry.h +++ b/include/asm-blackfin/entry.h @@ -17,6 +17,11 @@ #define PF_DTRACE_OFF 1 #define PF_DTRACE_BIT 5 +/* + * NOTE! The single-stepping code assumes that all interrupt handlers + * start by saving SYSCFG on the stack with their first instruction. + */ + /* This one is used for exceptions, emulation, and NMI. It doesn't push RETI and doesn't do cli. */ #define SAVE_ALL_SYS save_context_no_interrupts diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index 27ff532a806c..ff95e9d88342 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h @@ -437,7 +437,6 @@ void gpio_set_value(unsigned gpio, int arg); int gpio_get_value(unsigned gpio); #ifndef BF548_FAMILY -#define gpio_get_value(gpio) get_gpio_data(gpio) #define gpio_set_value(gpio, value) set_gpio_data(gpio, value) #endif diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index 574fe56989d1..cbbf7ffdbbff 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -117,10 +117,12 @@ static inline unsigned int readl(const volatile void __iomem *addr) extern void outsb(unsigned long port, const void *addr, unsigned long count); extern void outsw(unsigned long port, const void *addr, unsigned long count); +extern void outsw_8(unsigned long port, const void *addr, unsigned long count); extern void outsl(unsigned long port, const void *addr, unsigned long count); extern void insb(unsigned long port, void *addr, unsigned long count); extern void insw(unsigned long port, void *addr, unsigned long count); +extern void insw_8(unsigned long port, void *addr, unsigned long count); extern void insl(unsigned long port, void *addr, unsigned long count); extern void insl_16(unsigned long port, void *addr, unsigned long count); diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h index 735fa02fafb2..4725268a5ada 100644 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ b/include/asm-blackfin/mach-bf527/anomaly.h @@ -15,12 +15,16 @@ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ #define ANOMALY_05000328 (1) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ @@ -92,7 +96,6 @@ #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) -#define ANOMALY_05000312 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000363 (0) diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h index f0ab2736a680..2526b6ed6faa 100644 --- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h @@ -44,10 +44,21 @@ #define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) #define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v) #define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v) +#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) +#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) #define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v) #define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) #define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + +#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) +#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) +#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) +#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) +#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS @@ -85,7 +96,7 @@ struct bfin_serial_port { struct work_struct tx_dma_workqueue; #endif #ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct work_struct cts_workqueue; + struct timer_list cts_timer; int cts_pin; int rts_pin; #endif diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h index 2891727b6176..297821e2d79a 100644 --- a/include/asm-blackfin/mach-bf527/blackfin.h +++ b/include/asm-blackfin/mach-bf527/blackfin.h @@ -39,22 +39,22 @@ #include "defBF522.h" #include "anomaly.h" -#if defined(CONFIG_BF527) +#if defined(CONFIG_BF527) || defined(CONFIG_BF526) #include "defBF527.h" #endif -#if defined(CONFIG_BF525) +#if defined(CONFIG_BF525) || defined(CONFIG_BF524) #include "defBF525.h" #endif #if !defined(__ASSEMBLY__) #include "cdefBF522.h" -#if defined(CONFIG_BF527) +#if defined(CONFIG_BF527) || defined(CONFIG_BF526) #include "cdefBF527.h" #endif -#if defined(CONFIG_BF525) +#if defined(CONFIG_BF525) || defined(CONFIG_BF524) #include "cdefBF525.h" #endif #endif diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index 5a6dcc5fa36c..8f7ea112fd3a 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -2,7 +2,7 @@ * File: include/asm-blackfin/mach-bf533/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ @@ -176,6 +176,21 @@ #define ANOMALY_05000315 (1) /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ #define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* UART Break Signal Issues */ +#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) +/* PPI Does Not Start Properly In Specific Mode */ +#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) + /* These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. @@ -249,20 +264,6 @@ #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) /* Internal Voltage Regulator may not start up */ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) -/* UART Break Signal Issues */ -#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) -/* PPI Does Not Start Properly In Specific Mode */ -#define ANOMALY_05000400 (__SILICON_REVISION__ == 5) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ == 5) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000266 (0) diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index fbe88dee3e2d..ebf592b59aab 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -44,10 +44,21 @@ #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) +#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) +#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + +#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) +#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) +#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) +#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) +#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) + #ifdef CONFIG_BFIN_UART0_CTSRTS # define CONFIG_SERIAL_BFIN_CTSRTS # ifndef CONFIG_UART0_CTS_PIN @@ -77,7 +88,7 @@ struct bfin_serial_port { # endif #endif #ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct work_struct cts_workqueue; + struct timer_list cts_timer; int cts_pin; int rts_pin; #endif diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h index 17e1548cec08..0ab4dd7494cf 100644 --- a/include/asm-blackfin/mach-bf533/defBF532.h +++ b/include/asm-blackfin/mach-bf533/defBF532.h @@ -468,6 +468,8 @@ #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h index 832e6f6122da..5aa38e5da6b7 100644 --- a/include/asm-blackfin/mach-bf533/irq.h +++ b/include/asm-blackfin/mach-bf533/irq.h @@ -66,12 +66,13 @@ Core Emulation ** DMA8/9 Interrupt IVG13 28 DMA10/11 Interrupt IVG13 29 Watchdog Timer IVG13 30 - Software Interrupt 1 IVG14 31 - Software Interrupt 2 -- + + Softirq IVG14 31 + System Call -- (lowest priority) IVG15 32 * */ -#define SYS_IRQS 32 -#define NR_PERI_INTS 24 +#define SYS_IRQS 31 +#define NR_PERI_INTS 24 /* The ABSTRACT IRQ definitions */ /** the first seven of the following are fixed, the rest you change if you need to **/ @@ -96,7 +97,7 @@ Core Emulation ** #define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ #define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ #define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ -#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ +#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ #define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */ #define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */ #define IRQ_TMR0 23 /*Timer 0 */ @@ -108,9 +109,6 @@ Core Emulation ** #define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */ #define IRQ_WATCH 30 /*Watch Dog Timer */ -#define IRQ_SW_INT1 31 /*Software Int 1 */ -#define IRQ_SW_INT2 32 /*Software Int 2 (reserved for SYSCALL) */ - #define IRQ_PF0 33 #define IRQ_PF1 34 #define IRQ_PF2 35 diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index a6b08facb242..8460ab9c324f 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -2,7 +2,7 @@ * File: include/asm-blackfin/mach-bf537/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ @@ -132,8 +132,8 @@ #define ANOMALY_05000322 (1) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) -/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */ -#define ANOMALY_05000350 (__SILICON_REVISION__ < 3) +/* New Feature: UART Remains Enabled after UART Boot */ +#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (1) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ @@ -145,12 +145,10 @@ /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3) +#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) - - /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) #define ANOMALY_05000158 (0) diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h index fd100a415b98..1bf56ffa22f9 100644 --- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h @@ -44,10 +44,21 @@ #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) +#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) +#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + +#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) +#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) +#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) +#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) +#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS @@ -85,7 +96,7 @@ struct bfin_serial_port { struct work_struct tx_dma_workqueue; #endif #ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct work_struct cts_workqueue; + struct timer_list cts_timer; int cts_pin; int rts_pin; #endif diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h index be6f2ff77f31..2e68a8a1e730 100644 --- a/include/asm-blackfin/mach-bf537/irq.h +++ b/include/asm-blackfin/mach-bf537/irq.h @@ -34,24 +34,23 @@ /* * Interrupt source definitions - Event Source Core Event Name -Core Emulation ** - Events (highest priority) EMU 0 - Reset RST 1 - NMI NMI 2 - Exception EVX 3 - Reserved -- 4 - Hardware Error IVHW 5 - Core Timer IVTMR 6 * - -..... - - Software Interrupt 1 IVG14 31 - Software Interrupt 2 -- - (lowest priority) IVG15 32 * + * Event Source Core Event Name + * Core Emulation ** + * Events (highest priority) EMU 0 + * Reset RST 1 + * NMI NMI 2 + * Exception EVX 3 + * Reserved -- 4 + * Hardware Error IVHW 5 + * Core Timer IVTMR 6 + * ..... + * + * Softirq IVG14 + * System Call -- + * (lowest priority) IVG15 */ -#define SYS_IRQS 41 +#define SYS_IRQS 39 #define NR_PERI_INTS 32 /* The ABSTRACT IRQ definitions */ @@ -95,10 +94,8 @@ Core Emulation ** #define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ #define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ #define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */ -#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ +#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ #define IRQ_WATCH 38 /*Watch Dog Timer */ -#define IRQ_SW_INT1 40 /*Software Int 1 */ -#define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */ #define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ #define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */ diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 49d3cebc5293..3ad59655881a 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -75,6 +75,8 @@ #define ANOMALY_05000365 (1) /* Addressing Conflict between Boot ROM and Asynchronous Memory */ #define ANOMALY_05000369 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) /* Mobile DDR Operation Not Functional */ #define ANOMALY_05000377 (1) /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index 6547027cd3e6..5e29446a8e03 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -54,6 +54,15 @@ #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) #define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v) +#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */ +#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */ + +#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) +#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS)) +#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS)) +#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) +#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS @@ -90,7 +99,7 @@ struct bfin_serial_port { struct work_struct tx_dma_workqueue; #endif #ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct work_struct cts_workqueue; + struct timer_list cts_timer; int cts_pin; int rts_pin; #endif @@ -178,7 +187,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) #ifdef CONFIG_BFIN_UART1_CTSRTS peripheral_request(P_UART1_RTS, DRIVER_NAME); - peripheral_request(P_UART1_CTS DRIVER_NAME); + peripheral_request(P_UART1_CTS, DRIVER_NAME); #endif #endif @@ -193,7 +202,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) #ifdef CONFIG_BFIN_UART3_CTSRTS peripheral_request(P_UART3_RTS, DRIVER_NAME); - peripheral_request(P_UART3_CTS DRIVER_NAME); + peripheral_request(P_UART3_CTS, DRIVER_NAME); #endif #endif SSYNC(); diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index 08f90c21fe8a..e022e896cb18 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -2329,6 +2329,26 @@ #define KPADWE 0x1000 /* Keypad Wake-Up Enable */ #define ROTWE 0x2000 /* Rotary Wake-Up Enable */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN_5 0x0000 /* GAIN = 5*/ +#define GAIN_10 0x0004 /* GAIN = 1*/ +#define GAIN_20 0x0008 /* GAIN = 2*/ +#define GAIN_50 0x000C /* GAIN = 5*/ + +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + /* Bit masks for NFC_CTL */ #define WR_DLY 0xf /* Write Strobe Delay */ diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h index 82157caa96a2..5c5d7d7d695f 100644 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ b/include/asm-blackfin/mach-bf561/anomaly.h @@ -2,7 +2,7 @@ * File: include/asm-blackfin/mach-bf561/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h index 8a4e66d1db37..8aa02780e642 100644 --- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h @@ -44,10 +44,21 @@ #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) +#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) +#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + +#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) +#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) +#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) +#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) +#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) + #ifdef CONFIG_BFIN_UART0_CTSRTS # define CONFIG_SERIAL_BFIN_CTSRTS # ifndef CONFIG_UART0_CTS_PIN @@ -77,7 +88,7 @@ struct bfin_serial_port { # endif #endif #ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct work_struct cts_workqueue; + struct timer_list cts_timer; int cts_pin; int rts_pin; #endif diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index 366c9b9a0cb7..1ab50e906fe7 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h @@ -868,6 +868,34 @@ #define CHIPID_FAMILY 0x0FFFF000 #define CHIPID_MANUFACTURE 0x00000FFE +/* VR_CTL Masks */ +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5*/ +#define GAIN_10 0x0004 /* GAIN = 1*/ +#define GAIN_20 0x0008 /* GAIN = 2*/ +#define GAIN_50 0x000C /* GAIN = 5*/ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ + /* PLL_DIV Masks */ #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h index 21d982003e75..8bc46cd89a02 100644 --- a/include/asm-blackfin/mach-bf561/dma.h +++ b/include/asm-blackfin/mach-bf561/dma.h @@ -25,11 +25,11 @@ #define CH_MEM_STREAM1_SRC 27 /* RX */ #define CH_MEM_STREAM2_DEST 28 #define CH_MEM_STREAM2_SRC 29 -#define CH_MEM_STREAM3_SRC 30 -#define CH_MEM_STREAM3_DEST 31 +#define CH_MEM_STREAM3_DEST 30 +#define CH_MEM_STREAM3_SRC 31 #define CH_IMEM_STREAM0_DEST 32 #define CH_IMEM_STREAM0_SRC 33 -#define CH_IMEM_STREAM1_SRC 34 -#define CH_IMEM_STREAM1_DEST 35 +#define CH_IMEM_STREAM1_DEST 34 +#define CH_IMEM_STREAM1_SRC 35 #endif diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h index 83f0383957d2..6698389c5564 100644 --- a/include/asm-blackfin/mach-bf561/irq.h +++ b/include/asm-blackfin/mach-bf561/irq.h @@ -118,12 +118,13 @@ Supplemental interrupt 0 IVG7 69 supplemental interrupt 1 IVG7 70 - Software Interrupt 1 IVG14 71 - Software Interrupt 2 IVG15 72 * - (lowest priority) + Softirq IVG14 + System Call -- + (lowest priority) IVG15 + **********************************************************************/ -#define SYS_IRQS 72 +#define SYS_IRQS 71 #define NR_PERI_INTS 64 /* @@ -237,9 +238,7 @@ #define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ #define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ #define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */ -#define IRQ_SW_INT1 71 /* Software Interrupt 1 */ -#define IRQ_SW_INT2 72 /* Software Interrupt 2 */ - /* reserved for SYSCALL */ + #define IRQ_PF0 73 #define IRQ_PF1 74 #define IRQ_PF2 75 diff --git a/include/asm-blackfin/mach-common/context.S b/include/asm-blackfin/mach-common/context.S index fd0ebe1862b8..c0e630edfb9a 100644 --- a/include/asm-blackfin/mach-common/context.S +++ b/include/asm-blackfin/mach-common/context.S @@ -28,6 +28,11 @@ */ /* + * NOTE! The single-stepping code assumes that all interrupt handlers + * start by saving SYSCFG on the stack with their first instruction. + */ + +/* * Code to save processor context. * We even save the register which are preserved by a function call * - r4, r5, r6, r7, p3, p4, p5 diff --git a/include/asm-blackfin/serial.h b/include/asm-blackfin/serial.h new file mode 100644 index 000000000000..994dd869558c --- /dev/null +++ b/include/asm-blackfin/serial.h @@ -0,0 +1,5 @@ +/* + * include/asm-blackfin/serial.h + */ + +#define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h index 6e5859b6ea32..ddc43ce38533 100644 --- a/include/asm-blackfin/time.h +++ b/include/asm-blackfin/time.h @@ -24,6 +24,8 @@ #ifndef CONFIG_CPU_FREQ #define TIME_SCALE 1 +#define __bfin_cycles_off (0) +#define __bfin_cycles_mod (0) #else /* * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . @@ -31,6 +33,8 @@ * adjust the Core Timer Presale Register. This way we don't lose time. */ #define TIME_SCALE 4 +extern unsigned long long __bfin_cycles_off; +extern unsigned int __bfin_cycles_mod; #endif #endif diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h index 9785a6d531c6..8441cbc2bf9e 100644 --- a/include/asm-blackfin/types.h +++ b/include/asm-blackfin/types.h @@ -8,30 +8,12 @@ * not a major issue. However, for interoperability, libraries still * need to be careful to avoid a name clashes. */ +#include <asm-generic/int-ll64.h> + #ifndef __ASSEMBLY__ typedef unsigned short umode_t; -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -/* HK0617 -- Changes to unsigned long temporarily */ -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - #endif /* __ASSEMBLY__ */ /* * These aren't exported outside the kernel to avoid name space clashes @@ -42,18 +24,6 @@ __extension__ typedef unsigned long long __u64; #ifndef __ASSEMBLY__ -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - /* Dma addresses are 32-bits wide. */ typedef u32 dma_addr_t; |