diff options
Diffstat (limited to 'include/asm-m32r')
| -rw-r--r-- | include/asm-m32r/assembler.h | 10 | ||||
| -rw-r--r-- | include/asm-m32r/atomic.h | 1 | ||||
| -rw-r--r-- | include/asm-m32r/cacheflush.h | 2 | ||||
| -rw-r--r-- | include/asm-m32r/irq.h | 16 | ||||
| -rw-r--r-- | include/asm-m32r/m32102.h | 38 | ||||
| -rw-r--r-- | include/asm-m32r/m32104ut/m32104ut_pld.h | 163 | ||||
| -rw-r--r-- | include/asm-m32r/m32r.h | 8 | ||||
| -rw-r--r-- | include/asm-m32r/mman.h | 1 | ||||
| -rw-r--r-- | include/asm-m32r/system.h | 12 | ||||
| -rw-r--r-- | include/asm-m32r/unistd.h | 12 |
10 files changed, 233 insertions, 30 deletions
diff --git a/include/asm-m32r/assembler.h b/include/asm-m32r/assembler.h index e1dff9d6baad..b7f4d8aaeb46 100644 --- a/include/asm-m32r/assembler.h +++ b/include/asm-m32r/assembler.h @@ -52,7 +52,7 @@ or3 \reg, \reg, #low(\x) .endm -#if !defined(CONFIG_CHIP_M32102) +#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) #define STI(reg) STI_M reg .macro STI_M reg setpsw #0x40 -> nop @@ -64,7 +64,7 @@ clrpsw #0x40 -> nop ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1). .endm -#else /* CONFIG_CHIP_M32102 */ +#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ #define STI(reg) STI_M reg .macro STI_M reg mvfc \reg, psw @@ -191,12 +191,12 @@ and \reg, sp .endm -#if !defined(CONFIG_CHIP_M32102) +#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) .macro SWITCH_TO_KERNEL_STACK ; switch to kernel stack (spi) clrpsw #0x80 -> nop .endm -#else /* CONFIG_CHIP_M32102 */ +#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ .macro SWITCH_TO_KERNEL_STACK push r0 ; save r0 for working mvfc r0, psw @@ -218,7 +218,7 @@ .fillinsn 2: .endm -#endif /* CONFIG_CHIP_M32102 */ +#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ #endif /* __ASSEMBLY__ */ diff --git a/include/asm-m32r/atomic.h b/include/asm-m32r/atomic.h index ef1fb8ea4726..70761278b6cb 100644 --- a/include/asm-m32r/atomic.h +++ b/include/asm-m32r/atomic.h @@ -313,4 +313,5 @@ static __inline__ void atomic_set_mask(unsigned long mask, atomic_t *addr) #define smp_mb__before_atomic_inc() barrier() #define smp_mb__after_atomic_inc() barrier() +#include <asm-generic/atomic.h> #endif /* _ASM_M32R_ATOMIC_H */ diff --git a/include/asm-m32r/cacheflush.h b/include/asm-m32r/cacheflush.h index 46fc4c325108..e57427b6e249 100644 --- a/include/asm-m32r/cacheflush.h +++ b/include/asm-m32r/cacheflush.h @@ -7,7 +7,7 @@ extern void _flush_cache_all(void); extern void _flush_cache_copyback_all(void); -#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) +#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104) #define flush_cache_all() do { } while (0) #define flush_cache_mm(mm) do { } while (0) #define flush_cache_range(vma, start, end) do { } while (0) diff --git a/include/asm-m32r/irq.h b/include/asm-m32r/irq.h index 8ed77968ecb4..ca943954572a 100644 --- a/include/asm-m32r/irq.h +++ b/include/asm-m32r/irq.h @@ -65,6 +65,22 @@ #define NR_IRQS \ (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \ + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ) + +#elif defined(CONFIG_PLAT_M32104UT) +/* + * IRQ definitions for M32104UT + * M32104 Chip: 64 interrupts + * ICU of M32104UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin + */ +#define M32104UT_NUM_CPU_IRQ (64) +#define M32104UT_NUM_PLD_IRQ (32) +#define M32104UT_IRQ_BASE 0 +#define M32104UT_CPU_IRQ_BASE M32104UT_IRQ_BASE +#define M32104UT_PLD_IRQ_BASE (M32104UT_CPU_IRQ_BASE + M32104UT_NUM_CPU_IRQ) + +#define NR_IRQS \ + (M32104UT_NUM_CPU_IRQ + M32104UT_NUM_PLD_IRQ) + #else #define NR_IRQS 64 #endif diff --git a/include/asm-m32r/m32102.h b/include/asm-m32r/m32102.h index cb98101f4f6e..a1f0d1fe9eb8 100644 --- a/include/asm-m32r/m32102.h +++ b/include/asm-m32r/m32102.h @@ -11,7 +11,11 @@ /*======================================================================* * Special Function Register *======================================================================*/ +#if !defined(CONFIG_CHIP_M32104) #define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */ +#else +#define M32R_SFR_OFFSET (0x00700000) /* 0x00700000-0x007FFFFF 1[MB] */ +#endif /* * Clock and Power Management registers. @@ -100,7 +104,7 @@ #define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */ #define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */ -#ifdef CONFIG_CHIP_M32700 +#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32104) #define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */ #define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */ #define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */ @@ -113,7 +117,7 @@ #define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */ #define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */ #define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */ -#else /* not CONFIG_CHIP_M32700 */ +#else /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */ #define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */ #define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */ #define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */ @@ -126,7 +130,7 @@ #define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */ #define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */ #define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */ -#endif /* not CONFIG_CHIP_M32700 */ +#endif /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */ #define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */ #define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */ @@ -241,8 +245,24 @@ #define M32R_IRQ_MFT1 (17) /* MFT1 */ #define M32R_IRQ_MFT2 (18) /* MFT2 */ #define M32R_IRQ_MFT3 (19) /* MFT3 */ -#define M32R_IRQ_MFT4 (20) /* MFT4 */ -#define M32R_IRQ_MFT5 (21) /* MFT5 */ +#ifdef CONFIG_CHIP_M32104 +#define M32R_IRQ_MFTX0 (24) /* MFTX0 */ +#define M32R_IRQ_MFTX1 (25) /* MFTX1 */ +#define M32R_IRQ_DMA0 (32) /* DMA0 */ +#define M32R_IRQ_DMA1 (33) /* DMA1 */ +#define M32R_IRQ_DMA2 (34) /* DMA2 */ +#define M32R_IRQ_DMA3 (35) /* DMA3 */ +#define M32R_IRQ_SIO0_R (40) /* SIO0 send */ +#define M32R_IRQ_SIO0_S (41) /* SIO0 receive */ +#define M32R_IRQ_SIO1_R (42) /* SIO1 send */ +#define M32R_IRQ_SIO1_S (43) /* SIO1 receive */ +#define M32R_IRQ_SIO2_R (44) /* SIO2 send */ +#define M32R_IRQ_SIO2_S (45) /* SIO2 receive */ +#define M32R_IRQ_SIO3_R (46) /* SIO3 send */ +#define M32R_IRQ_SIO3_S (47) /* SIO3 receive */ +#define M32R_IRQ_ADC (56) /* ADC */ +#define M32R_IRQ_PC (57) /* PC */ +#else /* ! M32104 */ #define M32R_IRQ_DMA0 (32) /* DMA0 */ #define M32R_IRQ_DMA1 (33) /* DMA1 */ #define M32R_IRQ_SIO0_R (48) /* SIO0 send */ @@ -255,6 +275,7 @@ #define M32R_IRQ_SIO3_S (55) /* SIO3 receive */ #define M32R_IRQ_SIO4_R (56) /* SIO4 send */ #define M32R_IRQ_SIO4_S (57) /* SIO4 receive */ +#endif /* ! M32104 */ #ifdef CONFIG_SMP #define M32R_IRQ_IPI0 (56) @@ -281,15 +302,12 @@ #define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP) #define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP) +#endif /* CONFIG_SMP */ + #ifndef __ASSEMBLY__ -/* For NETDEV WATCHDOG */ typedef struct { unsigned long icucr; /* ICU Control Register */ } icu_data_t; - -extern icu_data_t icu_data[]; #endif -#endif /* CONFIG_SMP */ - #endif /* _M32102_H_ */ diff --git a/include/asm-m32r/m32104ut/m32104ut_pld.h b/include/asm-m32r/m32104ut/m32104ut_pld.h new file mode 100644 index 000000000000..a4eac20553df --- /dev/null +++ b/include/asm-m32r/m32104ut/m32104ut_pld.h @@ -0,0 +1,163 @@ +/* + * include/asm/m32104ut/m32104ut_pld.h + * + * Definitions for Programable Logic Device(PLD) on M32104UT board. + * Based on m32700ut_pld.h + * + * Copyright (c) 2002 Takeo Takahashi + * Copyright (c) 2005 Naoto Sugai + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file "COPYING" in the main directory of + * this archive for more details. + */ + +#ifndef _M32104UT_M32104UT_PLD_H +#define _M32104UT_M32104UT_PLD_H + +#include <linux/config.h> + +#if defined(CONFIG_PLAT_M32104UT) +#define PLD_PLAT_BASE 0x02c00000 +#else +#error "no platform configuration" +#endif + +#ifndef __ASSEMBLY__ +/* + * C functions use non-cache address. + */ +#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */) +#define __reg8 (volatile unsigned char *) +#define __reg16 (volatile unsigned short *) +#define __reg32 (volatile unsigned int *) +#else +#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET) +#define __reg8 +#define __reg16 +#define __reg32 +#endif /* __ASSEMBLY__ */ + +/* CFC */ +#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000) +#define PLD_CFSTS __reg16(PLD_BASE + 0x0002) +#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004) +#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006) + +/* MMC */ +#define PLD_MMCCR __reg16(PLD_BASE + 0x4000) +#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002) +#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006) +#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a) +#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c) +#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e) +#define PLD_MMCDET __reg16(PLD_BASE + 0x4010) +#define PLD_MMCWP __reg16(PLD_BASE + 0x4012) +#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000) +#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000) +#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000) +#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006) + +/* ICU + * ICUISTS: status register + * ICUIREQ0: request register + * ICUIREQ1: request register + * ICUCR3: control register for CFIREQ# interrupt + * ICUCR4: control register for CFC Card insert interrupt + * ICUCR5: control register for CFC Card eject interrupt + * ICUCR6: control register for external interrupt + * ICUCR11: control register for MMC Card insert/eject interrupt + * ICUCR13: control register for SC error interrupt + * ICUCR14: control register for SC receive interrupt + * ICUCR15: control register for SC send interrupt + */ + +#define PLD_IRQ_INT0 (M32104UT_PLD_IRQ_BASE + 0) /* None */ +#define PLD_IRQ_CFIREQ (M32104UT_PLD_IRQ_BASE + 3) /* CF IREQ */ +#define PLD_IRQ_CFC_INSERT (M32104UT_PLD_IRQ_BASE + 4) /* CF Insert */ +#define PLD_IRQ_CFC_EJECT (M32104UT_PLD_IRQ_BASE + 5) /* CF Eject */ +#define PLD_IRQ_EXINT (M32104UT_PLD_IRQ_BASE + 6) /* EXINT */ +#define PLD_IRQ_MMCCARD (M32104UT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */ +#define PLD_IRQ_SC_ERROR (M32104UT_PLD_IRQ_BASE + 13) /* SC error */ +#define PLD_IRQ_SC_RCV (M32104UT_PLD_IRQ_BASE + 14) /* SC receive */ +#define PLD_IRQ_SC_SND (M32104UT_PLD_IRQ_BASE + 15) /* SC send */ + +#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002) +#define PLD_ICUISTS_VECB_MASK (0xf000) +#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK) +#define PLD_ICUISTS_ISN_MASK (0x07c0) +#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK) +#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104) +#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106) +#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108) +#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a) +#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114) +#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118) +#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a) +#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c) +#define PLD_ICUCR_IEN (0x1000) +#define PLD_ICUCR_IREQ (0x0100) +#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */ +#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */ +#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */ +#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */ +#define PLD_ICUCR_ILEVEL0 (0x0000) +#define PLD_ICUCR_ILEVEL1 (0x0001) +#define PLD_ICUCR_ILEVEL2 (0x0002) +#define PLD_ICUCR_ILEVEL3 (0x0003) +#define PLD_ICUCR_ILEVEL4 (0x0004) +#define PLD_ICUCR_ILEVEL5 (0x0005) +#define PLD_ICUCR_ILEVEL6 (0x0006) +#define PLD_ICUCR_ILEVEL7 (0x0007) + +/* Power Control of MMC and CF */ +#define PLD_CPCR __reg16(PLD_BASE + 0x14000) +#define PLD_CPCR_CDP 0x0001 + +/* LED Control + * + * 1: DIP swich side + * 2: Reset switch side + */ +#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002) +#define PLD_IOLED_1_ON 0x001 +#define PLD_IOLED_1_OFF 0x000 +#define PLD_IOLED_2_ON 0x002 +#define PLD_IOLED_2_OFF 0x000 + +/* DIP Switch + * 0: Write-protect of Flash Memory (0:protected, 1:non-protected) + * 1: - + * 2: - + * 3: - + */ +#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004) +#define PLD_IOSWSTS_IOSW2 0x0200 +#define PLD_IOSWSTS_IOSW1 0x0100 +#define PLD_IOSWSTS_IOWP0 0x0001 + +/* CRC */ +#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000) +#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002) +#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004) +#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006) +#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008) +#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a) + +/* RTC */ +#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000) +#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002) +#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004) +#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006) +#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008) + +/* SIM Card */ +#define PLD_SCCR __reg16(PLD_BASE + 0x38000) +#define PLD_SCMOD __reg16(PLD_BASE + 0x38004) +#define PLD_SCSTS __reg16(PLD_BASE + 0x38006) +#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008) +#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a) +#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c) +#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e) + +#endif /* _M32104UT_M32104UT_PLD_H */ diff --git a/include/asm-m32r/m32r.h b/include/asm-m32r/m32r.h index ec142be00862..b133ca61acf1 100644 --- a/include/asm-m32r/m32r.h +++ b/include/asm-m32r/m32r.h @@ -14,7 +14,7 @@ #include <asm/m32r_mp_fpga.h> #elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \ || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ - || defined(CONFIG_CHIP_OPSP) + || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104) #include <asm/m32102.h> #endif @@ -43,6 +43,10 @@ #include <asm/m32700ut/m32700ut_pld.h> #endif +#if defined(CONFIG_PLAT_M32104UT) +#include <asm/m32104ut/m32104ut_pld.h> +#endif /* CONFIG_PLAT_M32104 */ + /* * M32R Register */ @@ -122,7 +126,7 @@ #include <asm/page.h> #ifdef CONFIG_MMU -#define NONCACHE_OFFSET __PAGE_OFFSET+0x20000000 +#define NONCACHE_OFFSET (__PAGE_OFFSET + 0x20000000) #else #define NONCACHE_OFFSET __PAGE_OFFSET #endif /* CONFIG_MMU */ diff --git a/include/asm-m32r/mman.h b/include/asm-m32r/mman.h index 011f6d9ec5cc..12e29747bc84 100644 --- a/include/asm-m32r/mman.h +++ b/include/asm-m32r/mman.h @@ -37,6 +37,7 @@ #define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */ #define MADV_WILLNEED 0x3 /* pre-fault pages */ #define MADV_DONTNEED 0x4 /* discard these pages */ +#define MADV_REMOVE 0x5 /* remove these pages & resources */ /* compatibility flags */ #define MAP_ANON MAP_ANONYMOUS diff --git a/include/asm-m32r/system.h b/include/asm-m32r/system.h index 5eee832b73a0..dcf619a0a0b0 100644 --- a/include/asm-m32r/system.h +++ b/include/asm-m32r/system.h @@ -69,12 +69,12 @@ } while(0) /* Interrupt Control */ -#if !defined(CONFIG_CHIP_M32102) +#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) #define local_irq_enable() \ __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory") #define local_irq_disable() \ __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory") -#else /* CONFIG_CHIP_M32102 */ +#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ static inline void local_irq_enable(void) { unsigned long tmpreg; @@ -96,7 +96,7 @@ static inline void local_irq_disable(void) "mvtc %0, psw \n\t" : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory"); } -#endif /* CONFIG_CHIP_M32102 */ +#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ #define local_save_flags(x) \ __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */) @@ -105,13 +105,13 @@ static inline void local_irq_disable(void) __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \ : "r" (x) : "cbit", "memory") -#if !defined(CONFIG_CHIP_M32102) +#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) #define local_irq_save(x) \ __asm__ __volatile__( \ "mvfc %0, psw; \n\t" \ "clrpsw #0x40 -> nop; \n\t" \ : "=r" (x) : /* no input */ : "memory") -#else /* CONFIG_CHIP_M32102 */ +#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ #define local_irq_save(x) \ ({ \ unsigned long tmpreg; \ @@ -124,7 +124,7 @@ static inline void local_irq_disable(void) : "=r" (x), "=&r" (tmpreg) \ : : "cbit", "memory"); \ }) -#endif /* CONFIG_CHIP_M32102 */ +#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ #define irqs_disabled() \ ({ \ diff --git a/include/asm-m32r/unistd.h b/include/asm-m32r/unistd.h index ac399e1f7bc0..39be87ca2a5a 100644 --- a/include/asm-m32r/unistd.h +++ b/include/asm-m32r/unistd.h @@ -319,7 +319,7 @@ type name(void) \ register long __scno __asm__ ("r7") = __NR_##name; \ register long __res __asm__("r0"); \ __asm__ __volatile__ (\ - "trap #" SYSCALL_VECTOR \ + "trap #" SYSCALL_VECTOR "|| nop"\ : "=r" (__res) \ : "r" (__scno) \ : "memory"); \ @@ -332,7 +332,7 @@ type name(type1 arg1) \ register long __scno __asm__ ("r7") = __NR_##name; \ register long __res __asm__ ("r0") = (long)(arg1); \ __asm__ __volatile__ (\ - "trap #" SYSCALL_VECTOR \ + "trap #" SYSCALL_VECTOR "|| nop"\ : "=r" (__res) \ : "r" (__scno), "0" (__res) \ : "memory"); \ @@ -346,7 +346,7 @@ register long __scno __asm__ ("r7") = __NR_##name; \ register long __arg2 __asm__ ("r1") = (long)(arg2); \ register long __res __asm__ ("r0") = (long)(arg1); \ __asm__ __volatile__ (\ - "trap #" SYSCALL_VECTOR \ + "trap #" SYSCALL_VECTOR "|| nop"\ : "=r" (__res) \ : "r" (__scno), "0" (__res), "r" (__arg2) \ : "memory"); \ @@ -361,7 +361,7 @@ register long __arg3 __asm__ ("r2") = (long)(arg3); \ register long __arg2 __asm__ ("r1") = (long)(arg2); \ register long __res __asm__ ("r0") = (long)(arg1); \ __asm__ __volatile__ (\ - "trap #" SYSCALL_VECTOR \ + "trap #" SYSCALL_VECTOR "|| nop"\ : "=r" (__res) \ : "r" (__scno), "0" (__res), "r" (__arg2), \ "r" (__arg3) \ @@ -378,7 +378,7 @@ register long __arg3 __asm__ ("r2") = (long)(arg3); \ register long __arg2 __asm__ ("r1") = (long)(arg2); \ register long __res __asm__ ("r0") = (long)(arg1); \ __asm__ __volatile__ (\ - "trap #" SYSCALL_VECTOR \ + "trap #" SYSCALL_VECTOR "|| nop"\ : "=r" (__res) \ : "r" (__scno), "0" (__res), "r" (__arg2), \ "r" (__arg3), "r" (__arg4) \ @@ -397,7 +397,7 @@ register long __arg3 __asm__ ("r2") = (long)(arg3); \ register long __arg2 __asm__ ("r1") = (long)(arg2); \ register long __res __asm__ ("r0") = (long)(arg1); \ __asm__ __volatile__ (\ - "trap #" SYSCALL_VECTOR \ + "trap #" SYSCALL_VECTOR "|| nop"\ : "=r" (__res) \ : "r" (__scno), "0" (__res), "r" (__arg2), \ "r" (__arg3), "r" (__arg4), "r" (__arg5) \ |