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-rw-r--r--include/asm-sh/cpu-sh3/adc.h28
-rw-r--r--include/asm-sh/cpu-sh3/addrspace.h19
-rw-r--r--include/asm-sh/cpu-sh3/cache.h43
-rw-r--r--include/asm-sh/cpu-sh3/cacheflush.h70
-rw-r--r--include/asm-sh/cpu-sh3/dac.h41
-rw-r--r--include/asm-sh/cpu-sh3/dma.h51
-rw-r--r--include/asm-sh/cpu-sh3/freq.h27
-rw-r--r--include/asm-sh/cpu-sh3/gpio.h67
-rw-r--r--include/asm-sh/cpu-sh3/mmu_context.h44
-rw-r--r--include/asm-sh/cpu-sh3/rtc.h8
-rw-r--r--include/asm-sh/cpu-sh3/sigcontext.h17
-rw-r--r--include/asm-sh/cpu-sh3/timer.h67
-rw-r--r--include/asm-sh/cpu-sh3/ubc.h42
-rw-r--r--include/asm-sh/cpu-sh3/watchdog.h25
14 files changed, 0 insertions, 549 deletions
diff --git a/include/asm-sh/cpu-sh3/adc.h b/include/asm-sh/cpu-sh3/adc.h
deleted file mode 100644
index b289e3ca19a6..000000000000
--- a/include/asm-sh/cpu-sh3/adc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __ASM_CPU_SH3_ADC_H
-#define __ASM_CPU_SH3_ADC_H
-
-/*
- * Copyright (C) 2004 Andriy Skulysh
- */
-
-
-#define ADDRAH 0xa4000080
-#define ADDRAL 0xa4000082
-#define ADDRBH 0xa4000084
-#define ADDRBL 0xa4000086
-#define ADDRCH 0xa4000088
-#define ADDRCL 0xa400008a
-#define ADDRDH 0xa400008c
-#define ADDRDL 0xa400008e
-#define ADCSR 0xa4000090
-
-#define ADCSR_ADF 0x80
-#define ADCSR_ADIE 0x40
-#define ADCSR_ADST 0x20
-#define ADCSR_MULTI 0x10
-#define ADCSR_CKS 0x08
-#define ADCSR_CH_MASK 0x07
-
-#define ADCR 0xa4000092
-
-#endif /* __ASM_CPU_SH3_ADC_H */
diff --git a/include/asm-sh/cpu-sh3/addrspace.h b/include/asm-sh/cpu-sh3/addrspace.h
deleted file mode 100644
index 0f94726c7d62..000000000000
--- a/include/asm-sh/cpu-sh3/addrspace.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999 by Kaz Kojima
- *
- * Defitions for the address spaces of the SH-3 CPUs.
- */
-#ifndef __ASM_CPU_SH3_ADDRSPACE_H
-#define __ASM_CPU_SH3_ADDRSPACE_H
-
-#define P0SEG 0x00000000
-#define P1SEG 0x80000000
-#define P2SEG 0xa0000000
-#define P3SEG 0xc0000000
-#define P4SEG 0xe0000000
-
-#endif /* __ASM_CPU_SH3_ADDRSPACE_H */
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
deleted file mode 100644
index bee2d81c56bf..000000000000
--- a/include/asm-sh/cpu-sh3/cache.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * include/asm-sh/cpu-sh3/cache.h
- *
- * Copyright (C) 1999 Niibe Yutaka
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH3_CACHE_H
-#define __ASM_CPU_SH3_CACHE_H
-
-#define L1_CACHE_SHIFT 4
-
-#define SH_CACHE_VALID 1
-#define SH_CACHE_UPDATED 2
-#define SH_CACHE_COMBINED 4
-#define SH_CACHE_ASSOC 8
-
-#define CCR 0xffffffec /* Address of Cache Control Register */
-
-#define CCR_CACHE_CE 0x01 /* Cache Enable */
-#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
-#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
-#define CCR_CACHE_CF 0x08 /* Cache Flush */
-#define CCR_CACHE_ORA 0x20 /* RAM mode */
-
-#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
-#define CACHE_PHYSADDR_MASK 0x1ffffc00
-
-#define CCR_CACHE_ENABLE CCR_CACHE_CE
-#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
- defined(CONFIG_CPU_SUBTYPE_SH7710) || \
- defined(CONFIG_CPU_SUBTYPE_SH7720) || \
- defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define CCR3_REG 0xa40000b4
-#define CCR_CACHE_16KB 0x00010000
-#define CCR_CACHE_32KB 0x00020000
-#endif
-
-#endif /* __ASM_CPU_SH3_CACHE_H */
diff --git a/include/asm-sh/cpu-sh3/cacheflush.h b/include/asm-sh/cpu-sh3/cacheflush.h
deleted file mode 100644
index f70d8ef76a15..000000000000
--- a/include/asm-sh/cpu-sh3/cacheflush.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * include/asm-sh/cpu-sh3/cacheflush.h
- *
- * Copyright (C) 1999 Niibe Yutaka
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
-#define __ASM_CPU_SH3_CACHEFLUSH_H
-
-/*
- * Cache flushing:
- *
- * - flush_cache_all() flushes entire cache
- * - flush_cache_mm(mm) flushes the specified mm context's cache lines
- * - flush_cache_dup mm(mm) handles cache flushing when forking
- * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
- * - flush_cache_range(vma, start, end) flushes a range of pages
- *
- * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
- * - flush_icache_range(start, end) flushes(invalidates) a range for icache
- * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
- *
- * Caches are indexed (effectively) by physical address on SH-3, so
- * we don't need them.
- */
-
-#if defined(CONFIG_SH7705_CACHE_32KB)
-
-/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
- * SH4. Unlike the SH4 this is a unified cache so we need to do some work
- * in mmap when 'exec'ing a new binary
- */
- /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
-#define CACHE_ALIAS 0x00001000
-
-#define PG_mapped PG_arch_1
-
-void flush_cache_all(void);
-void flush_cache_mm(struct mm_struct *mm);
-#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
-void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
- unsigned long end);
-void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
-void flush_dcache_page(struct page *pg);
-void flush_icache_range(unsigned long start, unsigned long end);
-void flush_icache_page(struct vm_area_struct *vma, struct page *page);
-#else
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-#define flush_dcache_page(page) do { } while (0)
-#define flush_icache_range(start, end) do { } while (0)
-#define flush_icache_page(vma,pg) do { } while (0)
-#endif
-
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-
-/* SH3 has unified cache so no special action needed here */
-#define flush_cache_sigtramp(vaddr) do { } while (0)
-#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
-
-#define p3_cache_init() do { } while (0)
-
-#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
diff --git a/include/asm-sh/cpu-sh3/dac.h b/include/asm-sh/cpu-sh3/dac.h
deleted file mode 100644
index 05fda8316ebc..000000000000
--- a/include/asm-sh/cpu-sh3/dac.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef __ASM_CPU_SH3_DAC_H
-#define __ASM_CPU_SH3_DAC_H
-
-/*
- * Copyright (C) 2003 Andriy Skulysh
- */
-
-
-#define DADR0 0xa40000a0
-#define DADR1 0xa40000a2
-#define DACR 0xa40000a4
-#define DACR_DAOE1 0x80
-#define DACR_DAOE0 0x40
-#define DACR_DAE 0x20
-
-
-static __inline__ void sh_dac_enable(int channel)
-{
- unsigned char v;
- v = ctrl_inb(DACR);
- if(channel) v |= DACR_DAOE1;
- else v |= DACR_DAOE0;
- ctrl_outb(v,DACR);
-}
-
-static __inline__ void sh_dac_disable(int channel)
-{
- unsigned char v;
- v = ctrl_inb(DACR);
- if(channel) v &= ~DACR_DAOE1;
- else v &= ~DACR_DAOE0;
- ctrl_outb(v,DACR);
-}
-
-static __inline__ void sh_dac_output(u8 value, int channel)
-{
- if(channel) ctrl_outb(value,DADR1);
- else ctrl_outb(value,DADR0);
-}
-
-#endif /* __ASM_CPU_SH3_DAC_H */
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
deleted file mode 100644
index 6813c3220a1d..000000000000
--- a/include/asm-sh/cpu-sh3/dma.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef __ASM_CPU_SH3_DMA_H
-#define __ASM_CPU_SH3_DMA_H
-
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
- defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define SH_DMAC_BASE 0xa4010020
-#else
-#define SH_DMAC_BASE 0xa4000020
-#endif
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
-#define DMTE0_IRQ 48
-#define DMTE1_IRQ 49
-#define DMTE2_IRQ 50
-#define DMTE3_IRQ 51
-#define DMTE4_IRQ 76
-#define DMTE5_IRQ 77
-#endif
-
-/* Definitions for the SuperH DMAC */
-#define TM_BURST 0x00000020
-#define TS_8 0x00000000
-#define TS_16 0x00000008
-#define TS_32 0x00000010
-#define TS_128 0x00000018
-
-#define CHCR_TS_MASK 0x18
-#define CHCR_TS_SHIFT 3
-
-#define DMAOR_INIT DMAOR_DME
-
-/*
- * The SuperH DMAC supports a number of transmit sizes, we list them here,
- * with their respective values as they appear in the CHCR registers.
- */
-enum {
- XMIT_SZ_8BIT,
- XMIT_SZ_16BIT,
- XMIT_SZ_32BIT,
- XMIT_SZ_128BIT,
-};
-
-static unsigned int ts_shift[] __maybe_unused = {
- [XMIT_SZ_8BIT] = 0,
- [XMIT_SZ_16BIT] = 1,
- [XMIT_SZ_32BIT] = 2,
- [XMIT_SZ_128BIT] = 4,
-};
-
-#endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/include/asm-sh/cpu-sh3/freq.h b/include/asm-sh/cpu-sh3/freq.h
deleted file mode 100644
index 53c62302b2e3..000000000000
--- a/include/asm-sh/cpu-sh3/freq.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * include/asm-sh/cpu-sh3/freq.h
- *
- * Copyright (C) 2002, 2003 Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH3_FREQ_H
-#define __ASM_CPU_SH3_FREQ_H
-
-#ifdef CONFIG_CPU_SUBTYPE_SH7712
-#define FRQCR 0xA415FF80
-#else
-#define FRQCR 0xffffff80
-#endif
-
-#define MIN_DIVISOR_NR 0
-#define MAX_DIVISOR_NR 4
-
-#define FRQCR_CKOEN 0x0100
-#define FRQCR_PLLEN 0x0080
-#define FRQCR_PSTBY 0x0040
-
-#endif /* __ASM_CPU_SH3_FREQ_H */
-
diff --git a/include/asm-sh/cpu-sh3/gpio.h b/include/asm-sh/cpu-sh3/gpio.h
deleted file mode 100644
index 4e53eb314b8f..000000000000
--- a/include/asm-sh/cpu-sh3/gpio.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * include/asm-sh/cpu-sh3/gpio.h
- *
- * Copyright (C) 2007 Markus Brunner, Mark Jonas
- *
- * Addresses for the Pin Function Controller
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef _CPU_SH3_GPIO_H
-#define _CPU_SH3_GPIO_H
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
- defined(CONFIG_CPU_SUBTYPE_SH7721)
-
-/* Control registers */
-#define PORT_PACR 0xA4050100UL
-#define PORT_PBCR 0xA4050102UL
-#define PORT_PCCR 0xA4050104UL
-#define PORT_PDCR 0xA4050106UL
-#define PORT_PECR 0xA4050108UL
-#define PORT_PFCR 0xA405010AUL
-#define PORT_PGCR 0xA405010CUL
-#define PORT_PHCR 0xA405010EUL
-#define PORT_PJCR 0xA4050110UL
-#define PORT_PKCR 0xA4050112UL
-#define PORT_PLCR 0xA4050114UL
-#define PORT_PMCR 0xA4050116UL
-#define PORT_PPCR 0xA4050118UL
-#define PORT_PRCR 0xA405011AUL
-#define PORT_PSCR 0xA405011CUL
-#define PORT_PTCR 0xA405011EUL
-#define PORT_PUCR 0xA4050120UL
-#define PORT_PVCR 0xA4050122UL
-
-/* Data registers */
-#define PORT_PADR 0xA4050140UL
-/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
-#define PORT_PBDR 0xA4050142UL
-#define PORT_PCDR 0xA4050144UL
-#define PORT_PDDR 0xA4050146UL
-#define PORT_PEDR 0xA4050148UL
-#define PORT_PFDR 0xA405014AUL
-#define PORT_PGDR 0xA405014CUL
-#define PORT_PHDR 0xA405014EUL
-#define PORT_PJDR 0xA4050150UL
-#define PORT_PKDR 0xA4050152UL
-#define PORT_PLDR 0xA4050154UL
-#define PORT_PMDR 0xA4050156UL
-#define PORT_PPDR 0xA4050158UL
-#define PORT_PRDR 0xA405015AUL
-#define PORT_PSDR 0xA405015CUL
-#define PORT_PTDR 0xA405015EUL
-#define PORT_PUDR 0xA4050160UL
-#define PORT_PVDR 0xA4050162UL
-
-/* Pin Select Registers */
-#define PORT_PSELA 0xA4050124UL
-#define PORT_PSELB 0xA4050126UL
-#define PORT_PSELC 0xA4050128UL
-#define PORT_PSELD 0xA405012AUL
-
-#endif
-
-#endif
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
deleted file mode 100644
index ab09da73ce77..000000000000
--- a/include/asm-sh/cpu-sh3/mmu_context.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * include/asm-sh/cpu-sh3/mmu_context.h
- *
- * Copyright (C) 1999 Niibe Yutaka
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H
-#define __ASM_CPU_SH3_MMU_CONTEXT_H
-
-#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
-#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
-#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
-#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
-
-#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
-
-#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
-#define MMU_PAGE_ASSOC_BIT 0x80
-
-#define MMU_NTLB_ENTRIES 128 /* for 7708 */
-#define MMU_NTLB_WAYS 4
-#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
-
-#define TRA 0xffffffd0
-#define EXPEVT 0xffffffd4
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
- defined(CONFIG_CPU_SUBTYPE_SH7706) || \
- defined(CONFIG_CPU_SUBTYPE_SH7707) || \
- defined(CONFIG_CPU_SUBTYPE_SH7709) || \
- defined(CONFIG_CPU_SUBTYPE_SH7710) || \
- defined(CONFIG_CPU_SUBTYPE_SH7712) || \
- defined(CONFIG_CPU_SUBTYPE_SH7720) || \
- defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
-#else
-#define INTEVT 0xffffffd8
-#endif
-
-#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */
-
diff --git a/include/asm-sh/cpu-sh3/rtc.h b/include/asm-sh/cpu-sh3/rtc.h
deleted file mode 100644
index 319404aaee37..000000000000
--- a/include/asm-sh/cpu-sh3/rtc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __ASM_SH_CPU_SH3_RTC_H
-#define __ASM_SH_CPU_SH3_RTC_H
-
-#define rtc_reg_size sizeof(u16)
-#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
-#define RTC_DEF_CAPABILITIES 0UL
-
-#endif /* __ASM_SH_CPU_SH3_RTC_H */
diff --git a/include/asm-sh/cpu-sh3/sigcontext.h b/include/asm-sh/cpu-sh3/sigcontext.h
deleted file mode 100644
index 17310dc03dcd..000000000000
--- a/include/asm-sh/cpu-sh3/sigcontext.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __ASM_CPU_SH3_SIGCONTEXT_H
-#define __ASM_CPU_SH3_SIGCONTEXT_H
-
-struct sigcontext {
- unsigned long oldmask;
-
- /* CPU registers */
- unsigned long sc_regs[16];
- unsigned long sc_pc;
- unsigned long sc_pr;
- unsigned long sc_sr;
- unsigned long sc_gbr;
- unsigned long sc_mach;
- unsigned long sc_macl;
-};
-
-#endif /* __ASM_CPU_SH3_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
deleted file mode 100644
index 793acf12aa08..000000000000
--- a/include/asm-sh/cpu-sh3/timer.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * include/asm-sh/cpu-sh3/timer.h
- *
- * Copyright (C) 2004 Lineo Solutions, Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH3_TIMER_H
-#define __ASM_CPU_SH3_TIMER_H
-
-/*
- * ---------------------------------------------------------------------------
- * TMU Common definitions for SH3 processors
- * SH7706
- * SH7709S
- * SH7727
- * SH7729R
- * SH7710
- * SH7720
- * SH7710
- * ---------------------------------------------------------------------------
- */
-
-#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define TMU_TOCR 0xfffffe90 /* Byte access */
-#endif
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
- defined(CONFIG_CPU_SUBTYPE_SH7720) || \
- defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define TMU_012_TSTR 0xa412fe92 /* Byte access */
-
-#define TMU0_TCOR 0xa412fe94 /* Long access */
-#define TMU0_TCNT 0xa412fe98 /* Long access */
-#define TMU0_TCR 0xa412fe9c /* Word access */
-
-#define TMU1_TCOR 0xa412fea0 /* Long access */
-#define TMU1_TCNT 0xa412fea4 /* Long access */
-#define TMU1_TCR 0xa412fea8 /* Word access */
-
-#define TMU2_TCOR 0xa412feac /* Long access */
-#define TMU2_TCNT 0xa412feb0 /* Long access */
-#define TMU2_TCR 0xa412feb4 /* Word access */
-
-#else
-#define TMU_012_TSTR 0xfffffe92 /* Byte access */
-
-#define TMU0_TCOR 0xfffffe94 /* Long access */
-#define TMU0_TCNT 0xfffffe98 /* Long access */
-#define TMU0_TCR 0xfffffe9c /* Word access */
-
-#define TMU1_TCOR 0xfffffea0 /* Long access */
-#define TMU1_TCNT 0xfffffea4 /* Long access */
-#define TMU1_TCR 0xfffffea8 /* Word access */
-
-#define TMU2_TCOR 0xfffffeac /* Long access */
-#define TMU2_TCNT 0xfffffeb0 /* Long access */
-#define TMU2_TCR 0xfffffeb4 /* Word access */
-#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define TMU2_TCPR2 0xfffffeb8 /* Long access */
-#endif
-#endif
-
-#endif /* __ASM_CPU_SH3_TIMER_H */
-
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
deleted file mode 100644
index 4e6381d5ff7a..000000000000
--- a/include/asm-sh/cpu-sh3/ubc.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * include/asm-sh/cpu-sh3/ubc.h
- *
- * Copyright (C) 1999 Niibe Yutaka
- * Copyright (C) 2003 Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH3_UBC_H
-#define __ASM_CPU_SH3_UBC_H
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
- defined(CONFIG_CPU_SUBTYPE_SH7720) || \
- defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define UBC_BARA 0xa4ffffb0
-#define UBC_BAMRA 0xa4ffffb4
-#define UBC_BBRA 0xa4ffffb8
-#define UBC_BASRA 0xffffffe4
-#define UBC_BARB 0xa4ffffa0
-#define UBC_BAMRB 0xa4ffffa4
-#define UBC_BBRB 0xa4ffffa8
-#define UBC_BASRB 0xffffffe8
-#define UBC_BDRB 0xa4ffff90
-#define UBC_BDMRB 0xa4ffff94
-#define UBC_BRCR 0xa4ffff98
-#else
-#define UBC_BARA 0xffffffb0
-#define UBC_BAMRA 0xffffffb4
-#define UBC_BBRA 0xffffffb8
-#define UBC_BASRA 0xffffffe4
-#define UBC_BARB 0xffffffa0
-#define UBC_BAMRB 0xffffffa4
-#define UBC_BBRB 0xffffffa8
-#define UBC_BASRB 0xffffffe8
-#define UBC_BDRB 0xffffff90
-#define UBC_BDMRB 0xffffff94
-#define UBC_BRCR 0xffffff98
-#endif
-
-#endif /* __ASM_CPU_SH3_UBC_H */
diff --git a/include/asm-sh/cpu-sh3/watchdog.h b/include/asm-sh/cpu-sh3/watchdog.h
deleted file mode 100644
index 4ee0347298d8..000000000000
--- a/include/asm-sh/cpu-sh3/watchdog.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * include/asm-sh/cpu-sh3/watchdog.h
- *
- * Copyright (C) 2002, 2003 Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH3_WATCHDOG_H
-#define __ASM_CPU_SH3_WATCHDOG_H
-
-/* Register definitions */
-#define WTCNT 0xffffff84
-#define WTCSR 0xffffff86
-
-/* Bit definitions */
-#define WTCSR_TME 0x80
-#define WTCSR_WT 0x40
-#define WTCSR_RSTS 0x20
-#define WTCSR_WOVF 0x10
-#define WTCSR_IOVF 0x08
-
-#endif /* __ASM_CPU_SH3_WATCHDOG_H */
-