diff options
Diffstat (limited to 'sound/soc/meson/axg-frddr.c')
| -rw-r--r-- | sound/soc/meson/axg-frddr.c | 143 |
1 files changed, 140 insertions, 3 deletions
diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c index a6f6f6a2eca8..2b8807737b2b 100644 --- a/sound/soc/meson/axg-frddr.c +++ b/sound/soc/meson/axg-frddr.c @@ -3,7 +3,9 @@ // Copyright (c) 2018 BayLibre, SAS. // Author: Jerome Brunet <jbrunet@baylibre.com> -/* This driver implements the frontend playback DAI of AXG based SoCs */ +/* + * This driver implements the frontend playback DAI of AXG and G12A based SoCs + */ #include <linux/clk.h> #include <linux/regmap.h> @@ -14,7 +16,29 @@ #include "axg-fifo.h" -#define CTRL0_FRDDR_PP_MODE BIT(30) +#define CTRL0_FRDDR_PP_MODE BIT(30) +#define CTRL0_SEL1_EN_SHIFT 3 +#define CTRL0_SEL2_SHIFT 4 +#define CTRL0_SEL2_EN_SHIFT 7 +#define CTRL0_SEL3_SHIFT 8 +#define CTRL0_SEL3_EN_SHIFT 11 +#define CTRL1_FRDDR_FORCE_FINISH BIT(12) + +static int g12a_frddr_dai_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); + + /* Reset the read pointer to the FIFO_INIT_ADDR */ + regmap_update_bits(fifo->map, FIFO_CTRL1, + CTRL1_FRDDR_FORCE_FINISH, 0); + regmap_update_bits(fifo->map, FIFO_CTRL1, + CTRL1_FRDDR_FORCE_FINISH, CTRL1_FRDDR_FORCE_FINISH); + regmap_update_bits(fifo->map, FIFO_CTRL1, + CTRL1_FRDDR_FORCE_FINISH, 0); + + return 0; +} static int axg_frddr_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) @@ -119,10 +143,123 @@ static const struct axg_fifo_match_data axg_frddr_match_data = { .dai_drv = &axg_frddr_dai_drv }; +static const struct snd_soc_dai_ops g12a_frddr_ops = { + .prepare = g12a_frddr_dai_prepare, + .startup = axg_frddr_dai_startup, + .shutdown = axg_frddr_dai_shutdown, +}; + +static struct snd_soc_dai_driver g12a_frddr_dai_drv = { + .name = "FRDDR", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = AXG_FIFO_CH_MAX, + .rates = AXG_FIFO_RATES, + .formats = AXG_FIFO_FORMATS, + }, + .ops = &g12a_frddr_ops, + .pcm_new = axg_frddr_pcm_new, +}; + +static const char * const g12a_frddr_sel_texts[] = { + "OUT 0", "OUT 1", "OUT 2", "OUT 3", "OUT 4", +}; + +static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel1_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT, + g12a_frddr_sel_texts); +static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel2_enum, FIFO_CTRL0, CTRL0_SEL2_SHIFT, + g12a_frddr_sel_texts); +static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel3_enum, FIFO_CTRL0, CTRL0_SEL3_SHIFT, + g12a_frddr_sel_texts); + +static const struct snd_kcontrol_new g12a_frddr_out1_demux = + SOC_DAPM_ENUM("Output Src 1", g12a_frddr_sel1_enum); +static const struct snd_kcontrol_new g12a_frddr_out2_demux = + SOC_DAPM_ENUM("Output Src 2", g12a_frddr_sel2_enum); +static const struct snd_kcontrol_new g12a_frddr_out3_demux = + SOC_DAPM_ENUM("Output Src 3", g12a_frddr_sel3_enum); + +static const struct snd_kcontrol_new g12a_frddr_out1_enable = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0, + CTRL0_SEL1_EN_SHIFT, 1, 0); +static const struct snd_kcontrol_new g12a_frddr_out2_enable = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0, + CTRL0_SEL2_EN_SHIFT, 1, 0); +static const struct snd_kcontrol_new g12a_frddr_out3_enable = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0, + CTRL0_SEL3_EN_SHIFT, 1, 0); + +static const struct snd_soc_dapm_widget g12a_frddr_dapm_widgets[] = { + SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0, + &g12a_frddr_out1_enable), + SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0, + &g12a_frddr_out2_enable), + SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0, + &g12a_frddr_out3_enable), + SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0, + &g12a_frddr_out1_demux), + SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0, + &g12a_frddr_out2_demux), + SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0, + &g12a_frddr_out3_demux), + SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0), +}; + +static const struct snd_soc_dapm_route g12a_frddr_dapm_routes[] = { + { "SRC 1", NULL, "Playback" }, + { "SRC 2", NULL, "Playback" }, + { "SRC 3", NULL, "Playback" }, + { "SRC 1 EN", "Switch", "SRC 1" }, + { "SRC 2 EN", "Switch", "SRC 2" }, + { "SRC 3 EN", "Switch", "SRC 3" }, + { "SINK 1 SEL", NULL, "SRC 1 EN" }, + { "SINK 2 SEL", NULL, "SRC 2 EN" }, + { "SINK 3 SEL", NULL, "SRC 3 EN" }, + { "OUT 0", "OUT 0", "SINK 1 SEL" }, + { "OUT 1", "OUT 1", "SINK 1 SEL" }, + { "OUT 2", "OUT 2", "SINK 1 SEL" }, + { "OUT 3", "OUT 3", "SINK 1 SEL" }, + { "OUT 4", "OUT 4", "SINK 1 SEL" }, + { "OUT 0", "OUT 0", "SINK 2 SEL" }, + { "OUT 1", "OUT 1", "SINK 2 SEL" }, + { "OUT 2", "OUT 2", "SINK 2 SEL" }, + { "OUT 3", "OUT 3", "SINK 2 SEL" }, + { "OUT 4", "OUT 4", "SINK 2 SEL" }, + { "OUT 0", "OUT 0", "SINK 3 SEL" }, + { "OUT 1", "OUT 1", "SINK 3 SEL" }, + { "OUT 2", "OUT 2", "SINK 3 SEL" }, + { "OUT 3", "OUT 3", "SINK 3 SEL" }, + { "OUT 4", "OUT 4", "SINK 3 SEL" }, +}; + +static const struct snd_soc_component_driver g12a_frddr_component_drv = { + .dapm_widgets = g12a_frddr_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(g12a_frddr_dapm_widgets), + .dapm_routes = g12a_frddr_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(g12a_frddr_dapm_routes), + .ops = &g12a_fifo_pcm_ops +}; + +static const struct axg_fifo_match_data g12a_frddr_match_data = { + .component_drv = &g12a_frddr_component_drv, + .dai_drv = &g12a_frddr_dai_drv +}; + static const struct of_device_id axg_frddr_of_match[] = { { .compatible = "amlogic,axg-frddr", .data = &axg_frddr_match_data, + }, { + .compatible = "amlogic,g12a-frddr", + .data = &g12a_frddr_match_data, }, {} }; MODULE_DEVICE_TABLE(of, axg_frddr_of_match); @@ -136,6 +273,6 @@ static struct platform_driver axg_frddr_pdrv = { }; module_platform_driver(axg_frddr_pdrv); -MODULE_DESCRIPTION("Amlogic AXG playback fifo driver"); +MODULE_DESCRIPTION("Amlogic AXG/G12A playback fifo driver"); MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); MODULE_LICENSE("GPL v2"); |