summaryrefslogtreecommitdiffstats
path: root/.cocciconfig (unfollow)
Commit message (Expand)AuthorFilesLines
2018-05-18drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+Ville Syrjälä3-26/+26
2018-05-18drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW tooVille Syrjälä1-4/+4
2018-05-18drm/i915: Disable LVDS on Radiant P845Ondrej Zary1-0/+8
2018-05-18drm/i915: Pull the context->pin_count dec into the common intel_context_unpinChris Wilson4-21/+5
2018-05-18drm/i915: Store a pointer to intel_context in i915_requestChris Wilson20-296/+321
2018-05-18drm/i915: Move fiddling with engine->last_retired_contextChris Wilson3-10/+26
2018-05-18drm/i915: Move request->ctx asideChris Wilson13-55/+64
2018-05-18drm/i915: enable the pipe/transcoder/planes later on HSW+Paulo Zanoni1-5/+5
2018-05-18drm/i915/icl: Read the correct Gen11 interrupt registersOscar Mateo3-12/+34
2018-05-17drm/i915: Remove unused enable_cmd_parser modparamChris Wilson2-4/+0
2018-05-17drm/i915: Nul-terminate legacy debug stringChris Wilson1-1/+1
2018-05-17drm/i915/execlists: HWACK checking superseded checking port[0].countChris Wilson1-2/+0
2018-05-17drm/i915: Clean up DVO pipe select bitsVille Syrjälä2-10/+7
2018-05-17drm/i915: Clean up TV pipe select bitsVille Syrjälä2-15/+9
2018-05-17drm/i915: Clean up SDVO pipe select bitsVille Syrjälä5-69/+52
2018-05-17drm/i915: Clean up LVDS pipe select bitsVille Syrjälä4-54/+42
2018-05-17drm/i915: Clean up ADPA pipe select bitsVille Syrjälä4-44/+33
2018-05-16drm/i915: Stop parking the signaler around resetChris Wilson6-23/+42
2018-05-16drm/i915/execlists: Flush pending preemption events during resetChris Wilson1-1/+35
2018-05-16drm/i915/execlists: Split out CSB processingChris Wilson1-39/+52
2018-05-16drm/i915: Split execlists/guc reset preparationsChris Wilson2-10/+36
2018-05-16drm/i915: Move engine reset prepare/finish to backendsChris Wilson4-41/+76
2018-05-16drm/i915/execlists: Refactor out complete_preempt_context()Chris Wilson2-19/+30
2018-05-16drm/i915: Only sync tasklets once for recursive reset preparationChris Wilson2-1/+8
2018-05-16drm/i915: Remove tasklet flush before disableChris Wilson1-9/+0
2018-05-16drm/i915/dp: fix spelling mistakes: "seqeuncer" and "seqeuencer"Colin Ian King1-6/+6
2018-05-16drm/i915: Shrink search list for active timelinesChris Wilson1-11/+14
2018-05-14drm/i915: Update DRIVER_DATE to 20180514Jani Nikula1-2/+2
2018-05-14drm/i915: Mark up nested spinlocksChris Wilson1-1/+1
2018-05-14drm/i915/execlists: Relax CSB force-mmio for VT-dChris Wilson1-8/+0
2018-05-13Revert "drm/i915/gvt: set max priority for gvt context"Weinan Li1-3/+0
2018-05-13drm/i915/gvt: let force_to_nonpriv cmd handler only valid for LRI cmdZhao Yan1-3/+11
2018-05-13drm/i915/gvt: do not return error on handling force_to_nonpriv registersZhao Yan2-2/+3
2018-05-13drm/i915/gvt: let NOPID be the default value of force_to_nonpriv registersZhao Yan2-9/+22
2018-05-13drm/i915/gvt: Remove disable_warn_untrack and print untracked mmio with debug...Changbin Du3-11/+3
2018-05-13drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glkMichel Thierry2-0/+7
2018-05-13drm/i915/selftests: scrub 64KMatthew Auld3-0/+25
2018-05-11drm/i915/oa: Check that OA is disabled before unpinningChris Wilson1-0/+8
2018-05-11Revert "drm/i915/cnl: Use mmio access to context status buffer"Chris Wilson1-3/+0
2018-05-11drm/i915/execlists: Use rmb() to order CSB readsChris Wilson1-0/+1
2018-05-11drm/i915/icl: WaForwardProgressSoftResetOscar Mateo2-0/+12
2018-05-11drm/i915/icl: Wa_1406838659Oscar Mateo2-0/+9
2018-05-11drm/i915/icl: Wa_1604302699Oscar Mateo2-1/+8
2018-05-11drm/i915/icl: Wa_1406680159Oscar Mateo1-0/+5
2018-05-11drm/i915/icl: Wa_1405779004Oscar Mateo2-0/+7
2018-05-11drm/i915/icl: WaDisCtxReloadOscar Mateo2-0/+9
2018-05-11drm/i915/icl: WaCL2SFHalfMaxAllocOscar Mateo2-0/+11
2018-05-11drm/i915/icl: WaDisableCleanEvictsOscar Mateo2-2/+9
2018-05-11drm/i915/icl: WaModifyGamTlbPartitioningOscar Mateo2-0/+10
2018-05-11drm/i915/icl: WaL3BankAddressHashingOscar Mateo2-0/+16
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-22 18:40:33 +0100