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* drm/i915/execlists: Refactor common engine setupChris Wilson2016-05-091-83/+93
* drm/i915: Small display interrupt handlers tidyTvrtko Ursulin2016-05-098-271/+237
* drm/i915: Determine DP++ type 1 DVI adaptor presence based on VBTVille Syrjälä2016-05-094-4/+75
* drm/i915: Enable/disable TMDS output buffers in DP++ adaptor as neededVille Syrjälä2016-05-093-0/+33
* drm/i915: Respect DP++ adaptor TMDS clock limitVille Syrjälä2016-05-092-8/+55
* drm: Add helper for DP++ adaptorsVille Syrjälä2016-05-094-1/+465
* drm/i915: Dump pipe config when intel_modeset_pipe_config fails.Maarten Lankhorst2016-05-091-1/+4
* Revert "mfd: intel_soc_pmic_core: Terminate panel control GPIO lookup table c...Daniel Vetter2016-05-091-1/+0
* drm/i915: Allow MI_LOAD_REGISTER_REG between whitelisted registers.Kenneth Graunke2016-05-091-2/+15
* drm/i915: Update DRIVER_DATE to 20160508Daniel Vetter2016-05-081-1/+1
* drm/i915/kbl: Introduce the first official DMC for Kabylake.Rodrigo Vivi2016-05-061-11/+19
* drm/i915: Unexport i915_ppgtt_init()Chris Wilson2016-05-052-2/+1
* drm/i915: Report command parser version 0 if disabledChris Wilson2016-05-053-3/+16
* drm/i915: Bail out of pipe config compute loop on LPTDaniel Vetter2016-05-041-1/+7
* drm/i915: remove i915_gem_object_ggtt_unbindMatthew Auld2016-05-042-7/+1
* drm/i915: Simplify intel_mark_busy/idleTvrtko Ursulin2016-05-043-13/+9
* Revert "drm/i915: start adding dp mst audio"Lyude2016-05-035-65/+8
* mfd: intel_soc_pmic_core: Terminate panel control GPIO lookup table correctlyVille Syrjälä2016-05-031-0/+1
* drm/i915/chv: Tune L3 SQC credits based on actual latenciesImre Deak2016-05-032-16/+38
* drm/i915: Clean up L3 SQC register field definitionsImre Deak2016-05-033-4/+6
* drm/i915/bdw: Add missing delay during L3 SQC credit programmingImre Deak2016-05-031-0/+6
* drm/i915: Parse LFP brightness control field in VBTDeepak M2016-05-024-0/+24
* drm/i915: Add rpm get/put in oom and vmap notifierPraveen Paneri2016-05-021-0/+4
* drm/i915: Unbind objects in shrinker only if device is runtime activePraveen Paneri2016-05-021-0/+12
* drm/i915/lvds: separate border enable readout from panel fitterJani Nikula2016-05-022-3/+4
* drm/i915: Enable semaphores for legacy submission on gen8Chris Wilson2016-04-291-4/+0
* drm/i915: Reload PD tables after semaphore wait on gen8Chris Wilson2016-04-291-0/+10
* drm/i915: Fix serialisation of pipecontrol write vs semaphore signalChris Wilson2016-04-291-2/+1
* drm/i915: Fix gen8 semaphores id for legacy modeChris Wilson2016-04-292-3/+9
* drm/i915: Fix ordering of sanitize ppgtt and sanitize execlistsChris Wilson2016-04-295-16/+20
* drm/i915: Apply strongly ordered RCS breadcrumb to gen8/legacyChris Wilson2016-04-293-9/+38
* drm/i915: Trim the flush for the execlists request emissionChris Wilson2016-04-291-2/+5
* drm/i915: Trim the flush for the legacy request emissionChris Wilson2016-04-291-2/+7
* drm/i915: Bump reserved size for legacy gen8 semaphore emissionChris Wilson2016-04-291-4/+4
* drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.cAnder Conselvan de Oliveira2016-04-293-11/+17
* drm/i915: Unduplicate pre encoder enabling phy codeAnder Conselvan de Oliveira2016-04-294-41/+33
* drm/i915: Unduplicate VLV phy pre pll enabling codeAnder Conselvan de Oliveira2016-04-294-51/+31
* drm/i915: Unduplicate VLV signal level codeAnder Conselvan de Oliveira2016-04-294-27/+37
* drm/i915: Unduplicate CHV encoders' post pll disable codeAnder Conselvan de Oliveira2016-04-294-58/+36
* drm/i915: Unduplicate CHV pre-encoder enabling phy logicAnder Conselvan de Oliveira2016-04-294-146/+98
* drm/i915: Unduplicate CHV phy-releated pre pll enabling codeAnder Conselvan de Oliveira2016-04-295-155/+89
* drm/i915: Unduplicate chv_data_lane_soft_reset()Ander Conselvan de Oliveira2016-04-294-88/+45
* drm/i915: Unduplicate CHV signal level codeAnder Conselvan de Oliveira2016-04-295-165/+136
* drm/i915: Set crtc_state->lane_count for HDMIAnder Conselvan de Oliveira2016-04-292-1/+7
* drm/i915: Fix comments about GMBUSFREQ registerVille Syrjälä2016-04-281-10/+5
* drm/i915: Use cached cdclk value in i915_audio_component_get_cdclk_freq()Ville Syrjälä2016-04-281-7/+1
* drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequencyVille Syrjälä2016-04-282-0/+4
* drm/i915/bxt: Adjusting the error in horizontal timings retrievalRamalingam C2016-04-281-9/+88
* drm/i915/BXT: Retrieving the horizontal timing for DSIRamalingam C2016-04-281-7/+37
* drm/i915: Unify GPU resets upon shutdownChris Wilson2016-04-283-25/+38
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