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* next/soc: (50 commits)
ARM: OMAP: AM33xx hwmod: fixup SPI after platform_data move
MAINTAINERS: add an entry for the BCM2835 ARM sub-architecture
ARM: bcm2835: instantiate console UART
ARM: bcm2835: add stub clock driver
ARM: bcm2835: add system timer
ARM: bcm2835: add interrupt controller driver
ARM: add infra-structure for BCM2835 and Raspberry Pi
ARM: tegra20: add CPU hotplug support
ARM: tegra30: add CPU hotplug support
ARM: tegra: clean up the common assembly macros into sleep.h
ARM: tegra: replace the CPU CAR access code by tegra_cpu_car_ops
ARM: tegra: introduce tegra_cpu_car_ops structures
ARM: Tegra: Add smp_twd clock for Tegra20
ARM: AM33XX: clock: Add dcan clock aliases for device-tree
ARM: OMAP2+: dpll: Add missing soc_is_am33xx() check for common functions
ARM: OMAP: omap_device: idle devices with no driver bound
ARM: OMAP: omap_device: don't attempt late suspend if no driver bound
ARM: OMAP: omap_device: keep track of driver bound status
ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
ARM: OMAP2+: hwmod: Hook-up am33xx support in omap_hwmod framework
...
Change/remove conflict in arch/arm/mach-ux500/clock.c resolved.
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/soc
ARM: add basic BCM2835 SoC and Raspberry Pi board support
The BCM2835 is an ARM SoC from Broadcom. This patch adds very basic
support for this SoC; enough to boot the system into an initrd with
UART console, interrupt controller, timers, and a stub clock driver.
Also provided is a similarly basic device tree for the Raspberry Pi
Model B board.
This series was written by Simon Arlott, Chris Boot, and Dom Cobley
downstream, with reference to a Broadcom tree, and modified for upstream
and submitted by Stephen Warren.
* tag 'rpi-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
MAINTAINERS: add an entry for the BCM2835 ARM sub-architecture
ARM: bcm2835: instantiate console UART
ARM: bcm2835: add stub clock driver
ARM: bcm2835: add system timer
ARM: bcm2835: add interrupt controller driver
ARM: add infra-structure for BCM2835 and Raspberry Pi
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Add myself as the maintainer for the BCM2835 ARM support, and related
drivers. This is mainly so that the MAINTAINERS file contains some
relevant entry, and the rpi/ARM mailing lists; I'd be quite happy if
anyone else came along and wanted to maintain/co-maintain this.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
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This patch was extracted from git://github.com/lp0/linux.git branch
rpi-split as of 2012/09/08, and modified as follows:
* s/bcm2708/bcm2835/.
* Modified device tree vendor prefix.
* Modified UART DT node to use a unit-address to create unique UART node
names, rather than using non-type names "uart0" and "uart1".
Note that UART 1 (the Broadcom "mini UART") is not yet present, but
I'm naming the DT node in anticipation that it will be added.
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dom Cobley <dc4@broadcom.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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This patch adds a minimal stub clock driver for the BCM2835. Its sole
purpose is to allow the PL011 AMBA clk_get() API calls to provide
something that looks enough like a clock that the driver probes and
operates correctly.
This patch was extracted from git://github.com/lp0/linux.git branch
rpi-split as of 2012/09/08, and modified as follows:
* Reworked to call clk_register_fixed_rate(), and clk_register_clkdev()
rather than using static data to represent the clocks.
* Moved implementation to drivers/clk/.
* Modified .dev_id for UART clocks to match UART DT node names.
* s/bcm2708/bcm2835/.
* Modified device tree vendor prefix.
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dom Cobley <dc4@broadcom.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
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The System Timer peripheral provides four 32-bit timer channels and a
single 64-bit free running counter. Each channel has an output compare
register, which is compared against the 32 least significant bits of the
free running counter values, and generates an interrupt.
Timer 3 is used as the Linux timer.
The BCM2835 also contains an SP804-based timer module. However, it
apparently has significant differences from the standard SP804 IP block,
and Broadcom's documentation recommends using the system timer instead.
This patch was extracted from git://github.com/lp0/linux.git branch
rpi-split as of 2012/09/08, and modified as follows:
* s/bcm2708/bcm2835/.
* Modified device tree vendor prefix.
* Moved to drivers/clocksource/. This looks like the desired location for
such code now.
* Added DT binding docs.
* Moved struct sys_timer bcm2835_timer into time.c to encapsulate it more.
* Simplified bcm2835_time_init() to find one matching node and operate on
it, rather than looping over all matching nodes. This seems more
consistent with other clocksource code.
* Simplified bcm2835_time_init() using of_iomap().
* Renamed struct bcm2835_timer.index to match_mask to better represent its
purpose.
* s/printk(PR_INFO/pr_info(/
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dom Cobley <dc4@broadcom.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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The BCM2835 contains a custom interrupt controller, which supports 72
interrupt sources using a 2-level register scheme. The interrupt
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence the symbol naming in the
code.
This patch was extracted from git://github.com/lp0/linux.git branch
rpi-split as of 2012/09/08, and modified as follows:
* s/bcm2708/bcm2835/.
* Modified device tree vendor prefix.
* Moved implementation to drivers/irchip/.
* Added devicetree documentation, and hence removed list of IRQs from
bcm2835.dtsi.
* Changed shift in MAKE_HWIRQ() and HWIRQ_BANK() from 8 to 5 to reduce
the size of the hwirq space, and pass the total size of the hwirq space
to irq_domain_add_linear(), rather than just the number of valid hwirqs;
the two are different due to the hwirq space being sparse.
* Added the interrupt controller DT node to the top-level of the DT,
rather than nesting it inside a /axi node. Hence, changed the reg value
since /axi had a ranges property. This seems simpler to me, but I'm not
sure if everyone will like this change or not.
* Don't set struct irq_domain_ops.map = irq_domain_simple_map, hence
removing the need to patch include/linux/irqdomain.h or
kernel/irq/irqdomain.c.
* Simplified armctrl_of_init() using of_iomap().
* Removed unused IS_VALID_BANK()/IS_VALID_IRQ() macros.
* Renamed armctrl_handle_irq() to prevent possible symbol clashes.
* Made armctrl_of_init() static.
* Removed comment "Each bank is registered as a separate interrupt
controller" since this is no longer true.
* Removed FSF address from license header.
* Added my name to copyright header.
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dom Cobley <dc4@broadcom.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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The BCM2835 is an ARM SoC from Broadcom. This patch adds very basic
support for this SoC.
http://www.broadcom.com/products/BCM2835
http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Note that the documentation in the latter .pdf assumes the MMU setup
that's used on the "VideoCore" companion processor, and does not document
physical peripheral addresses. Subtract 0x5e000000 to obtain the physical
addresses. This is accounted for by the ranges property in the /soc node
in the device tree.
The BCM2835 SoC is used in the Raspberry Pi. This patch also adds a
minimal device tree for this board; enough to see some very early kernel
boot messages through earlyprintk. However, this patch does not yet
provide a useful booting system.
http://www.raspberrypi.org/.
This patch was extracted from git://github.com/lp0/linux.git branch
rpi-split from 3-4 months ago, and significantly stripped down and
modified since.
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dom Cobley <dc4@broadcom.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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AM33xx hwmod data includes "mcspi.h" which has now been moved after
the platform_data move. Fix it.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
From Paul Walmsley <paul@pwsan.com>:
AM33xx hwmod data and miscellaneous clock and hwmod fixes. AM33xx
should now boot on mainline after this is applied, according to
Vaibhav.
(The shortlog makes no sense here since it contains mostly the dependent
cleanups that are part of the preceding branches).
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-am33xx
AM33xx hwmod data and miscellaneous clock and hwmod fixes. AM33xx
should now boot on mainline after this is applied, according to
Vaibhav.
This second version includes trailing commas at the end of structure
records at Tony's request. It also adds a OMAP_INTC_START macro
expansion to each IRQ number to make the sparseirq conversion easier.
Basic build, boot, and PM test transcripts are here:
http://www.pwsan.com/omap/testlogs/am33xx_hwmod_clock_devel_3.7/20120912165952/
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Currently, the device names for the dcan module follows the
format "dcan.X", where 'X' is the dcan instance number.
On other side, driver may request for clock with/without con_id
and dev_id, and it is expected that platform should respect this
request and return the requested clock handle.
Now, when using device tree, the format of the device name created
by OF layer is different, "<reg-address>.<device-name>",
assuming that the device-tree "reg" property is specified.
This causes the look-up failure for clock node in dcan driver
To fix this add new dcan clock alias for using device-tree.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <robherring2@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Add missing soc_is_am33xx() check for DPLL common control & clock
related functions, without this dpll programmability would be broken
for am33xx family of devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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This patch adds HWMOD data for all the peripherals of
AM335X device and also hooks up to the existing OMAP framework.
hwmod data has been already been cleaned up for the recent
changes in clocktree, where all leaf nodes have been removed,
since with modulemode based control, both clock and hwmod
interface does same thing. This reduces the code size to large
extent and also avoids duplication of same control.
So instead of specifying module's leaf node as a main_clk,
now we are relying on parent clock of module's functional clock.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: removed period in hwmod device names; changed mmc2 main_clk
to mmc_clk at Vaibhav's request; added trailing commas to structure
records at Tony's request to deal with some rmk parsing issues; added
OMAP_INTC_START to facilitate sparse-IRQ conversion]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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AM33XX PRCM architecture is different that any OMAP family
of devices, so it is required to have separate implementation
to handle AM33XX module enable/disable, reset assert/deassert
functionality.
This patch adds wrapper api's in omap_hwmod framework to
access prm/cm for AM33XX family of devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
[paul@pwsan.com: fixed checkpatch messages]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Kevin Hilman <khilman@ti.com>:
Updates for omap_device layer for v3.7.
Allows omap_device layer to keep track of driver bound status in order
to make more intelligent decisions about idling unused devices.
* tag 'devel-omap-device-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP: omap_device: idle devices with no driver bound
ARM: OMAP: omap_device: don't attempt late suspend if no driver bound
ARM: OMAP: omap_device: keep track of driver bound status
+ sync to 3.6-rc5
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git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into devel-omap-device
Updates for omap_device layer for v3.7.
Allows omap_device layer to keep track of driver bound status in order
to make more intelligent decisions about idling unused devices.
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Under some circumstances, drivers may leave an omap_device enabled due
to driver programming errors, or due to a failure in the drivers
probe method.
Using the recently added omap_device driver_status field, we can
detect conditions where an omap_device is enabled but has no driver
bound and then ensure that the device is properly idled until it can
be probed again.
The goal of this feature is not only to detect and warn on these error
conditions, but also to ensure that devices are properly put in
low-power states so they do not prevent SoC-wide low-power states.
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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Currently, the omap_device PM domain layer uses the late suspend and
early resume callbacks to ensure devices are in their low power
states.
However, this is attempted even in cases where a driver probe has
failed. If a driver's ->probe() method fails, the driver is likely in
a state where it is not expecting its runtime PM callbacks to be
called, yet currently the omap_device PM domain code attempts to call
the drivers callbacks.
To fix, use the omap_device driver_status field to check whether a
driver is bound to the omap_device before attempting to trigger driver
callbacks.
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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Use the bus notifier to keep track of driver bound status by adding a
new internal field to struct omap_device: _driver_status.
This will be useful for follow-up patches which need to know whether
or not a driver is bound in order to make intelligent omap_device
enable/idle decisions.
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: implement CPU hotplug
This branch implements CPU hot-plugging support for both Tegra20 and
Tegra30. Portions of the implementation are contained in the clock
driver, hence this branch is based on the common clock conversion in
order to avoid duplicating work.
By Joseph Lo
via Stephen Warren
* tag 'tegra-for-3.7-cpu-hotplug' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra20: add CPU hotplug support
ARM: tegra30: add CPU hotplug support
ARM: tegra: clean up the common assembly macros into sleep.h
ARM: tegra: replace the CPU CAR access code by tegra_cpu_car_ops
ARM: tegra: introduce tegra_cpu_car_ops structures
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Hotplug function put CPU in offline or online mode at runtime.
When the CPU been put into offline, it was been clock gated. The
offline CPU can be power gated, when the remaining CPU goes into
LP2.
Based on the worked by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Hotplug function put CPUs in offline or online state at runtime.
When the CPU been put in the offline state, it was been clock and
power gated. Except primary CPU other CPUs can be hotplugged.
Based on the work by:
Scott Williams <scwilliams@nvidia.com>
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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There are some common macros for Tegra low-level assembly code. Clean
up them into one header file and move the definitions that will be
re-used into it as well.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Replacing the code that directly access to CAR registers with
tegra_cpu_car_ops. This ops hides CPU CAR access inside and
provides control interface for it.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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The tegra_cpu_car_ops provide the interface for CPU to control
it's clock gating and reset status. The other drivers should use
this for CPU control. And should not directly access CAR registers
to control CPU.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: switch to the common clock framework
This branch contains a few bug-fixes, followed by a conversion of Tegra's
clock driver to the common clock framework, followed by various bug fixes
found after the conversion.
* tag 'tegra-for-3.7-common-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: Tegra: Add smp_twd clock for Tegra20
ARM: tegra: cpu-tegra: explicitly manage re-parenting
ARM: tegra: fix overflow in tegra20_pll_clk_round_rate()
ARM: tegra: Fix data type for io address
ARM: tegra: remove tegra_timer from tegra_list_clks
ARM: tegra30: clocks: fix the wrong tegra_audio_sync_clk_ops name
ARM: tegra: clocks: separate tegra_clk_32k_ops from Tegra20 and Tegra30
ARM: tegra: Remove duplicate code
ARM: tegra: Port tegra to generic clock framework
ARM: tegra: Add clk_tegra structure and helper functions
ARM: tegra: Rename tegra20 clock file
ARM: tegra20: Separate out clk ops and clk data
ARM: tegra30: Separate out clk ops and clk data
ARM: tegra: fix U16 divider range check
ARM: tegra: turn on UART A clock at boot
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Clockevent's frequency is changed upon cpufreq change
notification. It fetches local timer's rate to update the
clockevent frequency. This patch adds local timer clock
for Tegra20.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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When changing a PLL's rate, it must have no active children. The CPU
clock cannot be stopped, and CPU clock's divider is not used. The old
clock driver used to handle this by internally reparenting the CPU clock
onto a different PLL when changing the CPU clock rate. However, the new
common-clock based clock driver does not do this, and probably cannot do
this due to the locking issues it would cause.
To solve this, have the Tegra cpufreq driver explicitly perform the
reparenting operations itself. This is probably reasonable anyway,
since such reparenting is somewhat a matter of policy (e.g. which
alternate clock source to use, whether to leave the CPU clock a child
of the alternate clock source if it's running at the desired rate),
and hence is something more appropriate for the cpufreq driver than
the core clock driver anyway.
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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32-bit math isn't enough when e.g. *prate=12000000, and sel->n=1000.
Use 64-bit math to prevent this.
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Warnings were generated because following commit changed data type for
address pointer
195bbca ARM: 7500/1: io: avoid writeback addressing modes for __raw_ accessors
arch/arm/mach-tegra/tegra30_clocks.c: In function 'clk_measure_input_freq':
arch/arm/mach-tegra/tegra30_clocks.c:418:2: warning: passing argument 2 of '__raw_writel' makes pointer from integer without a cast
.../arch/arm/include/asm/io.h:88:20: note: expected 'volatile void *' but argument is of type 'unsigned int
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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tegra_time is a struct sys_timer, not a struct clk, so can't be included
in an array of struct clk *.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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It should use tegra30_audio_sync_clk_ops for tegra30. It will cause
the tegra30 use the wrong audio_sync_clk_ops when build a kernel with
a tegra20 and tegra30 both supported kernel. And building error when
a tegra30-only kernel.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Currently the tegra20 and tegra30 share the same symbol for
tegra_clk_32k_ops. This will cause a compile error when building
a tegra20-only kernel image. Add tegra_clk_32k_ops for tegra20 and
modify tegra30_clk_32k_ops for tegra30.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Remove Tegra legacy clock framework code.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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This patch converts tegra clock code to generic clock framework in following way:
- Implement clk_ops as required by generic clk framework. (tegraXX_clocks.c)
- Use platform specific struct clk_tegra in clk_ops implementation instead of struct clk.
- Initialize all clock data statically. (tegraXX_clocks_data.c)
Legacy framework did not have recalc_rate and is_enabled functions. Implemented these functions.
Removed init function. It's functionality is splitted into recalc_rate and is_enabled.
Static initialization is used since slab is not up in .init_early and clock
is needed to be initialized before clockevent/clocksource initialization.
Macros redefined for clk_tegra.
Also, single struct clk_tegra is used for all type of clocks (PLL, peripheral etc.). This
is to move quickly to generic common clock framework so that other dependent features will
not be blocked (such as DT binding).
Enabling COMMON_CLOCK config moved to ARCH_TEGRA since it is enabled for both Tegra20
and Tegra30.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Add Tegra platform specific clock structure clk_tegra and
some helper functions for generic clock framework.
struct clk_tegra is the single strcture used for all types of
clocks. reset and cfg_ex ops moved to clk_tegra from clk_ops.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Make the name consistent with other files.
s/tegra2/tegra20
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Move clock initialization data to separate file. This is
required for migrating to generic clock framework if static
initialization is used.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Move clock initialization data to separate file. This is
required for migrating to generic clock framework if static
initialization is used.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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A U16 divider can divide a clock by 1..64K. However, the range-check
in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's
downstream kernels already have the fixed range-check.
In practice this is a problem on Whistler's I2C bus, which uses a bus
clock rate of 100KHz (rather than the more common 400KHz on Tegra boards),
which requires a HW module clock of 8*100KHz. The parent clock is 216MHz,
leading to a desired divider of 270. Prior to conversion to the common
clock framework, this range error was somehow ignored/irrelevant and
caused no problems. However, the common clock framework evidently has
more rigorous error-checking, so this failure causes the I2C bus to fail
to operate correctly.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Some boards use UART D for the main serial console, and some use UART A.
UART D's clock is listed in board-dt-tegra20.c's clock table, whereas
UART A's clock is not. This causes the clock code to think UART A's
clock is unsed. The common clock framework turns off unused clocks at
boot time. This makes the kernel appear to hang. Add UART A's clock into
the clock table to prevent this. Eventually, this requirement should be
handled by the UART driver, and/or properties in a board-specific device
tree file.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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ARM i.MX SoC updates
* tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6:
ARM: i.MX35: Implement camera and keypad clocks
ARM: mxc: ssi-fiq: Make ssi-fiq.S Thumb-2 compatible
ARM i.MX53: register CAN clocks
arm imx31: add a few pinmux settings the tt01 needs
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This patch also adds mux and divider for camera clock.
Tested on i.MX35-pdk.
Signed-off-by: Alex Gershgorin <alexg@meprolight.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Because FIQ handlers get copied straight into the vectors page to
the FIQ vector entry point, FIQ handlers in a Thumb-2 kernel must
start in Thumb-2. A Thumb-2 kernel enters all exception vectors in
Thumb-2.
This patch adapts the mxc SSI FIQ code suitable for a Thumb-2
kernel.
The code contained use of r13 (sp) which isn't allowed in Thumb-2.
r11 and r13 have been swapped throughout the file to work around
this.
Currently, the way that the function to be copied is located using
labels is a bit ugly: we cannot annotate the FIQ handler properly
as a Thumb-2 function, because this would set bit 0 of the label
address seen by the linker, causing off-by-one errors when copying
the function. Ideally, the copy would be done with fncpy(), but
this would require changes to the common set_fiq_handler()
function. For now, we don't touch this.
References to locally-defined global symbols with adr and ldr may
not be accepted by the assembler in Thumb-2. Local shadow symbols
are added to work around this.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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From: Sascha Hauer <s.hauer@pengutronix.de>
This adds the clocks for the flexcans on the imx53.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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These are the Pinmux Settings for the PP4 SSI Port multiplexible
onto the first UART Pins.
Signed-off-by: Torben Hohn <torbenh@linutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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* renesas/pmu:
ARM: shmobile: emev2: enable PMU(Performance Monitoring Unit)
ARM: shmobile: sh73a0: enable PMU(Performance Monitoring Unit)
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This patch enables PMU(Performance Monitoring Unit) for emev2.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Simon Horman <horms@verge.net.au>
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This patch enables PMU(Performance Monitoring Unit) for sh73a0.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Simon Horman <horms@verge.net.au>
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