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* Merge remote branch 'airlied/drm-core-next' into drm-intel-nextChris Wilson2010-12-16114-5145/+10988
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| * drm/radeon/kms: properly print ontario chip idAlex Deucher2010-12-161-0/+1
| | | | | | | | | | Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: fix vram start calculation on ontario (v2)Alex Deucher2010-12-164-13/+8
| | | | | | | | | | Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * Merge remote branch 'nouveau/drm-nouveau-next' of ../drm-nouveau-next into ↵Dave Airlie2010-12-1663-4018/+6600
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drm-core-next * 'nouveau/drm-nouveau-next' of ../drm-nouveau-next: (93 commits) drm/nv50: fix a couple of vm init issues drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation. drm/nouveau: kick vram functions out into an "engine" drm/nouveau: allow gpuobj vinst to be a virtual address when necessary drm/nv50: tidy up PCIEGART implementation drm/nv50: enable non-contig vram allocations where requested drm/nv50: enable 4KiB pages for small vram allocations drm/nv50: implement global channel address space on new VM code drm/nv50: implement BAR1/BAR3 management on top of new VM code drm/nv50: import new vm code drm/nv50: implement custom vram mm drm/nouveau: Avoid potential race between nouveau_fence_update() and context takedown. drm/nouveau: fix use of drm_mm_node in semaphore object drm/nouveau: wrap calls to ttm_bo_validate() drm/nouveau: no need to zero dma objects, we fill them completely anyway drm/nouveau: introduce a util function to wait on reg != val drm/nouveau: implicitly insert non-DMA objects into RAMHT drm/nouveau: make fifo.create_context() responsible for mapping control regs drm/nouveau: Spin for a bit in nouveau_fence_wait() before yielding the CPU. drm/nouveau: Use WC memory on the AGP GART. ...
| | * drm/nv50: fix a couple of vm init issuesFrancisco Jerez2010-12-161-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes overwriting the first page table entry when testing that the PRAMIN BAR can be correctly read/written, and adds an additional bar flush after poking the BAR3 control regs. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation.Francisco Jerez2010-12-083-18/+10
| | | | | | | | | | | | | | | Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: kick vram functions out into an "engine"Ben Skeggs2010-12-087-51/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | NVC0 will be able to share some of nv50's paths this way. This also makes it the card-specific vram code responsible for deciding if a given set of tile_flags is valid, rather than duplicating the allowed types in nv50_vram.c and nouveau_gem.c Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: allow gpuobj vinst to be a virtual address when necessaryBen Skeggs2010-12-082-2/+24
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: tidy up PCIEGART implementationBen Skeggs2010-12-085-95/+79
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: enable non-contig vram allocations where requestedBen Skeggs2010-12-081-1/+5
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: enable 4KiB pages for small vram allocationsBen Skeggs2010-12-082-19/+25
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: implement global channel address space on new VM codeBen Skeggs2010-12-0813-216/+86
| | | | | | | | | | | | | | | | | | | | | As of this commit, it's guaranteed that if an object is in VRAM that its GPU virtual address will be constant. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: implement BAR1/BAR3 management on top of new VM codeBen Skeggs2010-12-084-153/+162
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: import new vm codeBen Skeggs2010-12-0811-22/+714
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: implement custom vram mmBen Skeggs2010-12-088-122/+650
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required on nv50 as we need to be able to have more precise control over physical VRAM allocations to avoid buffer corruption when using buffers of mixed memory types. This removes some nasty overallocation/alignment that we were previously using to "control" this problem. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: Avoid potential race between nouveau_fence_update() and context ↵Francisco Jerez2010-12-081-8/+11
| | | | | | | | | | | | | | | | | | | | | takedown. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: fix use of drm_mm_node in semaphore objectBen Skeggs2010-12-081-3/+2
| | | | | | | | | | | | | | | | | | | | | At some point in the future, this bo won't necessarily be backed by a drm_mm_node, so use the start/size fields of the ttm_mem_reg instead. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: wrap calls to ttm_bo_validate()Ben Skeggs2010-12-083-5/+20
| | | | | | | | | | | | | | | | | | | | | This will be used later to fixup bo.offset with a buffer's fixed GPU virtual address. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: no need to zero dma objects, we fill them completely anywayBen Skeggs2010-12-081-5/+2
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: introduce a util function to wait on reg != valBen Skeggs2010-12-084-13/+35
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: implicitly insert non-DMA objects into RAMHTBen Skeggs2010-12-086-80/+43
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: make fifo.create_context() responsible for mapping control regsBen Skeggs2010-12-085-21/+29
| | | | | | | | | | | | | | | | | | | | | | | | The regs belong to PFIFO, they're different for pretty much the same generations we need different PFIFO control for, and NVC0 is going to be even more different than the rest. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: Spin for a bit in nouveau_fence_wait() before yielding the CPU.Francisco Jerez2010-12-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Sleeping doesn't pay off for very short delays in comparison with the minimum granularity of schedule_timeout(). Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: Use WC memory on the AGP GART.Francisco Jerez2010-12-081-2/+3
| | | | | | | | | | | | | | | Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: Synchronize with the user channel before GPU object destruction.Francisco Jerez2010-12-084-28/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There have been reports of PFIFO cache errors during context take down (fdo bug 31637). They are caused by some GPU objects being taken out while the channel is still potentially processing commands. Make sure that all the previous rendering has landed before releasing a GPU object. Reported-by: Grzesiek Sójka <pld@pfu.pl> Reported-by: Patrice Mandin <patmandin@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Acked-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv04-nv10: Don't re-enable FIFO access multiple times after IRQ dispatch.Francisco Jerez2010-12-082-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | nvxx_graph_isr is already taking care of it. In some cases this could've made you miss PGRAPH interrupts (e.g. when you were supposed to get several IRQs of the same kind in a row). Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv04-nv40: Give "gpuobj->cinst" the same meaning as on nv50.Francisco Jerez2010-12-083-13/+3
| | | | | | | | | | | | | | | | | | | | | No functional changes, just simplify some code paths a bit. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: fabricate DCB encoder table for iMac G4Francisco Jerez2010-12-031-64/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | In typical Apple fashion there's no standard information about what encoders are present on this machine, this patch adds a quirk to provide it. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: tidy up and extend dma object creation interfacesBen Skeggs2010-12-038-160/+184
| | | | | | | | | | | | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: remove some useless GETPARAMsBen Skeggs2010-12-032-19/+1
| | | | | | | | | | | | | | | | | | | | | These have been unused since UMS support was ripped out, so lets remove them completely. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv84: fix minor issues in PCRYPT implementationBen Skeggs2010-12-032-1/+2
| | | | | | | | | | | | | | | | | | | | | Fix running of destroy_context() when create_context() has never been called for the channel, and fill in engine's tlb_flush() function pointer. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: remove dummy page use from PCI(E)GART, use PTE present insteadBen Skeggs2010-12-032-37/+3
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: fix 0x100c90 init for NVAFBen Skeggs2010-12-031-3/+6
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: allocate page for unknown PFB object in nv50_fb.cBen Skeggs2010-12-032-1/+56
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: rework gpu-specific instmem interfacesBen Skeggs2010-12-036-243/+270
| | | | | | | | | | | | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: simplify gpuobj suspend/resumeBen Skeggs2010-12-034-73/+21
| | | | | | | | | | | | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: rework PGPIO IRQ handling and hotplug detectionBen Skeggs2010-12-037-104/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allows callers to install their own handlers for when a GPIO line changes state (such as for hotplug detect). This also fixes a bug where we weren't acknowledging the GPIO IRQ until after the bottom half had run, causing a severe IRQ storm in some cases. Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv04-nv40: unregister irq handler on destroyBen Skeggs2010-12-031-0/+3
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: tidy+move PGRAPH ISRs to their respective *_graph.c filesBen Skeggs2010-12-038-894/+809
| | | | | | | | | | | | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: move PFIFO ISR into nv04_fifo.cBen Skeggs2010-12-037-208/+219
| | | | | | | | | | | | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv04-nv40: register vblank isrBen Skeggs2010-12-032-19/+18
| | | | | | | | | | | | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: move bitfield/enum helpers to nouveau_util.cBen Skeggs2010-12-033-68/+63
| | | | | | | | | | | | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: use register/unregister functionality for PDISPLAY ISRBen Skeggs2010-12-034-18/+13
| | | | | | | | | | | | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: move GPIO ISR to nv50_gpio.cBen Skeggs2010-12-035-24/+40
| | | | | | | | | | | | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv84: move PCRYPT ISR out of nouveau_irq.cBen Skeggs2010-12-035-25/+98
| | | | | | | | | | | | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: allow irq handlers to be installed by engine-specific codeBen Skeggs2010-12-032-1/+37
| | | | | | | | | | | | | | | | | | | | | Lets start to clean up this mess! Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: 0x50c0 apparently works on NVA3+ too, so lets allow itBen Skeggs2010-12-031-5/+4
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv50: fix compute object classBen Skeggs2010-12-031-2/+8
| | | | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nouveau: Fix sleep while atomic in nouveau_bo_fence().Francisco Jerez2010-12-031-3/+7
| | | | | | | | | | | | | | | | | | Reported-by: Pekka Paalanen <pq@iki.fi> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * drm/nv20: Add Z compression support.Francisco Jerez2010-12-034-14/+106
| | | | | | | | | | | | | | | | | | Signed-off-by: Francisco Jerez <currojerez@riseup.net> Tested-by: Xavier Chantry <chantry.xavier@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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