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* PCI ASPM: remove get_root_port_linkKenji Kaneshige2009-06-181-13/+11
| | | | | | | | | By having a pointer to the root port link, we can remove loops in get_root_port_link() to search the root port link. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: cleanup pcie_aspm_sanity_checkKenji Kaneshige2009-06-181-12/+9
| | | | | | | | Minor cleanup for pcie_aspm_sanity_check(). Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: remove has_switch fieldKenji Kaneshige2009-06-181-4/+1
| | | | | | | | We don't need the 'has_switch' field in the struct pcie_link_state. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: cleanup calc_Lx_latencyKenji Kaneshige2009-06-181-39/+34
| | | | | | | | | | | Cleanup for calc_L0S_latency() and calc_L1_latency(). - Separate exit latency and acceptable latency calculation. - Some minor cleanups. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: cleanup pcie_aspm_get_cap_deviceKenji Kaneshige2009-06-181-5/+4
| | | | | | | | Minor cleanup for pcie_aspm_get_cap_device(). Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: cleanup clkpm checksKenji Kaneshige2009-06-181-14/+20
| | | | | | | | | | | | | | | | | In the current ASPM implementation, callers of pcie_set_clock_pm() check Clock PM capability of the link or current Clock PM state of the link. This check should be done in pcie_set_clock_pm() itself. This patch moves those checks into pcie_set_clock_pm(). It also introduces pcie_set_clkpm_nocheck() that is equivalent to old pcie_set_clock_pm(), for the caller who wants to change Clocl PM state regardless of the Clock PM capability or current Clock PM state. In addition, this patch changes the function name from pcie_set_clock_pm() to pcie_set_clkpm() for consistency. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: cleanup __pcie_aspm_check_state_oneKenji Kaneshige2009-06-181-42/+25
| | | | | | | | Clean up and simplify __pcie_aspm_check_state_one(). Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: cleanup initializationKenji Kaneshige2009-06-181-67/+75
| | | | | | | | | Clean up ASPM initialization by refactoring some functionality, renaming functions, and moving things around. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: cleanup change input argument of aspm functionsKenji Kaneshige2009-06-181-199/+173
| | | | | | | | | | | | | | | In the current ASPM implementation, there are many functions that take a pointer to struct pci_dev corresponding to the upstream component of the link as a parameter. But, since those functions handle PCI express link state, a pointer to struct pcie_link_state is more suitable than a pointer to struct pci_dev. Changing a parameter to a pointer to struct pcie_link_state makes ASPM code much simpler and easier to read. This patch also contains some minor cleanups. This patch doesn't have any functional change. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: cleanup misc in struct pcie_link_stateKenji Kaneshige2009-06-181-9/+9
| | | | | | | | | | | Cleanup for some fields in pcie_link_state. - Add comments. - make "downstream_has_switch" field 1-bit. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: cleanup clkpm state in struct pcie_link_stateKenji Kaneshige2009-06-181-19/+18
| | | | | | | | | | | The "clk_pm_capable", "clk_pm_enable" and "bios_clk_state" fields in the struct pcie_link_state only take 1-bit value. So those fields don't need to be defined as unsigned int. This patch makes those fields 1-bit, and cleans up some related code. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: cleanup latency field in struct pcie_link_stateKenji Kaneshige2009-06-181-38/+28
| | | | | | | | | | | | | | | Clean up latency related data structures for ASPM. - Introduce struct acpi_latency for exit latency and acceptable latency management. With this change, struct endpoint_state is no longer needed. - We don't need to hold both upstream latency and downstream latency in the current implementation. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: cleanup aspm state field in struct pcie_link_stateKenji Kaneshige2009-06-181-33/+38
| | | | | | | | | | | The "support_state", "enabled_state" and "bios_aspm_state" fields in the struct pcie_link_state take 2-bit value. So those fields don't need to be defined as unsigned int. This patch makes those fields 2-bit, and cleans up some related code. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: fix typo in struct pcie_link_stateKenji Kaneshige2009-06-181-7/+7
| | | | | | | | | | | Fix a typo in struct pcie_link_state. The "sibiling" field in the struct pcie_link_state should be "sibling". Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: drivers/pci/slot.c should depend on CONFIG_SYSFSAlex Chiang2009-06-183-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is no way to interact with a physical PCI slot without sysfs, so encode the dependency and prevent this build error: drivers/pci/slot.c: In function 'pci_hp_create_module_link': drivers/pci/slot.c:327: error: 'module_kset' undeclared This patch _should_ make pci-sysfs.o depend on CONFIG_SYSFS too, but we cannot (yet) because the PCI core merrily assumes the existence of sysfs: drivers/built-in.o: In function `pci_bus_add_device': drivers/pci/bus.c:89: undefined reference to `pci_create_sysfs_dev_files' drivers/built-in.o: In function `pci_stop_dev': drivers/pci/remove.c:24: undefined reference to `pci_remove_sysfs_dev_files' So do the minimal bit for now and figure out how to untangle it later. Reported-by: Randy Dunlap <randy.dunlap@oracle.com> Acked-by: Randy Dunlap <randy.dunlap@oracle.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Fix-suggested-by: Matthew Wilcox <matthew@wil.cx> Signed-off-by: Alex Chiang <achiang@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: remove redundant __msi_set_enable()Matthew Wilcox2009-06-181-20/+18
| | | | | | | | | | We have the 'pos' of the MSI capability at all locations which call msi_set_enable(), so pass it to msi_set_enable() instead of making it find the capability every time. Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI PM: consistently use type bool for wake enable variableFrans Pop2009-06-172-2/+2
| | | | | | | Other functions use type bool, so use that for pci_enable_wake as well. Signed-off-by: Frans Pop <elendil@planet.nl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* x86/ACPI: Correct maximum allowed _CRS returned resources and warn if exceededGary Hade2009-06-161-6/+27
| | | | | | | | | | | | | | | | | Issue a warning if _CRS returns too many resource descriptors to be accommodated by the fixed size resource array instances. If there is no transparent bridge on the root bus "too many" is the PCI_BUS_NUM_RESOURCES size of the resource array. Otherwise, the last 3 slots of the resource array must be excluded making the maximum (PCI_BUS_NUM_RESOURCES - 3). The current code: - is silent when _CRS returns too many resource descriptors and - incorrectly allows use of the last 3 slots of the resource array for a root bus with a transparent bridge Signed-off-by: Gary Hade <garyhade@us.ibm.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: remove invalid comment of msi_mask_irq()Kenji Kaneshige2009-06-161-3/+0
| | | | | | | | Remove invalid comment of msi_mask_irq(). Reviewed-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI PM: Fix handling of devices without PM support by pci_target_state()Rafael J. Wysocki2009-06-161-3/+2
| | | | | | | | | | | | | | | | | If a PCI device is not power-manageable either by the platform, or with the help of the native PCI PM interface, pci_target_state() will return either PCI_D3hot, or PCI_POWER_ERROR for it, depending on whether or not the device is configured to wake up the system. Alas, none of these return values is correct, because each of them causes pci_prepare_to_sleep() to return error code, although it should complete successfully in such a case. Fix this problem by making pci_target_state() always return PCI_D0 for devices that cannot be power managed. Cc: stable@kernel.org Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: support Secondary Bus ResetYu Zhao2009-06-161-0/+31
| | | | | | | | | | | | PCI-to-PCI Bridge 1.2 specifies that the Secondary Bus Reset bit can force the assertion of RST# on the secondary interface, which can be used to reset all devices including subordinates under this bus. This can be used to reset a function if this function is the only device under this bus. Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: support PM D0hot->D3 transition resetYu Zhao2009-06-161-0/+34
| | | | | | | | | | | PCI PM 1.2 specifies that the device will perform an internal reset upon transitioning from D3hot to D0 when the NO_SOFT_RESET bit is clear. This method can be used to reset a function if neither PCIe FLR nor PCI AF FLR are supported. Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: cleanup Function Level ResetYu Zhao2009-06-163-85/+87
| | | | | | | | | | | | | | | | This patch enhances the FLR functions: 1) remove disable_irq() so the shared IRQ won't be disabled. 2) replace the 1s wait with 100, 200 and 400ms wait intervals for the Pending Transaction. 3) replace mdelay() with msleep(). 4) add might_sleep(). 5) lock the device to prevent PM suspend from accessing the CSRs during the reset. 6) coding style fixes. Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI AER: software error injectionHuang Ying2009-06-165-1/+495
| | | | | | | | | | | | | | | | Debugging PCIE AER code can be very difficult because it is hard to trigger various real hardware errors. This patch provide a software based error injection tool, which can fake various PCIE errors with a user space helper tool named "aer-inject". Which can be gotten from: http://www.kernel.org/pub/linux/kernel/people/yhuang/ The patch fakes AER error by faking some PCIE AER related registers and an AER interrupt for specified the PCIE device. Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI AER: multiple error supportZhang, Yanmin2009-06-162-23/+69
| | | | | | | | | | | | | | When a root port receives the same errors more than once before the kernel process them, the Multiple Error Messages Received flags are set by hardware. Because the root port could only save one kind of correctable error source id and another uncorrectable error source id at the same time, the second message sender id is lost if the 2 messages are sent from 2 different devices. This patch makes the kernel search all devices under the root port when multiple messages are received. Reviewed-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Zhang Yanmin <yanmin_zhang@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI AER: support invalid error source IDsZhang, Yanmin2009-06-163-60/+122
| | | | | | | | | | When the bus id part of error source id is equal to 0 or nosourceid=1, make the kernel probe the AER status registers of all devices under the root port to find the initial error reporter. Reviewed-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Zhang Yanmin <yanmin_zhang@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI AER: support Multiple Error Received and no error source idZhang, Yanmin2009-06-164-31/+50
| | | | | | | | | | | | | | | | | | | | Based on PCI Express AER specs, a root port might receive multiple TLP errors while it could only save a correctable error source id and an uncorrectable error source id at the same time. In addition, some root port hardware might be unable to provide a correct source id, i.e., the source id, or the bus id part of the source id provided by root port might be equal to 0. The patchset implements the support in kernel by searching the device tree under the root port. Patch 1 changes parameter cb of function pci_walk_bus to return a value. When cb return non-zero, pci_walk_bus stops more searching on the device tree. Reviewed-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Zhang Yanmin <yanmin_zhang@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI hotplug: remove redundant .owner initializationsKenji Kaneshige2009-06-169-9/+0
| | | | | | | | | | The "owner" field in struct hotplug_slot_ops is initialized by PCI hotplug core. So each hotplug controller driver doesn't need to initialize it. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Reviewed-by: Alex Chiang <achiang@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI hotplug: create symlink to hotplug driver moduleKenji Kaneshige2009-06-165-9/+80
| | | | | | | | | | | | | Create symbolic link to hotplug driver module in the PCI slot directory (/sys/bus/pci/slots/<SLOT#>). In the past, we need to load hotplug drivers one by one to identify the hotplug driver that handles the slot, and it was very inconvenient especially for trouble shooting. With this change, we can easily identify the hotplug driver. Signed-off-by: Taku Izumi <izumi.taku@jp.fujitsu.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Reviewed-by: Alex Chiang <achiang@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI hotplug: fix return value of has_foo() functionsKenji Kaneshige2009-06-161-64/+68
| | | | | | | | | | | | Current has_foo() functions in pci_hotplug_core.c returns 0 if the "foo" property is true. It would cause misunderstanding. In addition, the error code of those functions is never checked, so this patch changes those functions' error code to 'bool' and return true if the property "foo" is true. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Reviewed-by: Alex Chiang <achiang@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: Remove untested Electromechanical Interlock (EMI) support in pciehp.Kenji Kaneshige2009-06-164-152/+1
| | | | | | | | | | | | | | | | | The EMI support in pciehp is obviously broken. It is implemented using struct hotplug_slot_attribute, but sysfs_ops for pci_slot_ktype is NOT for struct hotplug_slot_attribute, but for struct pci_slot_attribute. This bug had been there for a long time, maybe it was introduced when PCI slot framework was introduced. The reason why this bug didn't cause any problem is maybe the EMI support is not tested at all because of lack of test environment. As described above, the EMI support in pciehp seems not to be tested at all. So this patch removes EMI support from pciehp, instead of fixing the bug. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* x86/PCI: add description for check_enable_amd_mmconf boot parameterAndreas Herrmann2009-06-161-0/+3
| | | | | | | Describe check_enable_amd_mmconf. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: PCIE AER: Document for PCIE AER software error injectionHuang Ying2009-06-161-0/+21
| | | | | | | | This patch adds a minimal HOWTO for PCIE AER software error injection in Documentation/PCI/pcieaer-howto.txt. Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: PCIE AER: export aer_irqHuang Ying2009-06-162-1/+4
| | | | | | | This is used by PCIE AER error injection to fake an PCI AER interrupt. Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: Add pci_bus_set_opsHuang Ying2009-06-162-0/+20
| | | | | | | | | | pci_bus_set_ops changes pci_ops associated with a pci_bus. This can be used by debug tools such as PCIE AER error injection to fake some PCI configuration registers. Acked-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: use pci_is_root_bus() in pci_common_swizzle()Kenji Kaneshige2009-06-161-1/+1
| | | | | | | | | | Use pci_is_root_bus() in pci_common_swizzle() for checking if the pci bus is root, for code consistency. Reviewed-by: Alex Chiang <achiang@hp.com> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: use pci_is_root_bus() in pci_get_interrupt_pin()Kenji Kaneshige2009-06-161-1/+1
| | | | | | | | | | Use pci_is_root_bus() in pci_get_interrupt_pin() for checking if the pci bus is root, for code consistency. Reviewed-by: Alex Chiang <achiang@hp.com> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: use pci_is_root_bus() in pci_read_bridge_bases()Kenji Kaneshige2009-06-161-1/+1
| | | | | | | | | | Use pci_is_root_bus() in pci_read_bridge_bases() to check if the pci bus is root, for code consistency. Reviewed-by: Alex Chiang <achiang@hp.com> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: use pci_is_root_bus() in pci_find_upstream_pcie_bridge()Kenji Kaneshige2009-06-161-1/+1
| | | | | | | | | | Use pci_is_root_bus() in pci_find_upstream_pcie_bridge() to check if the pci bus is root, for code consistency. Reviewed-by: Alex Chiang <achiang@hp.com> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: use pci_is_root_bus() in acpi_find_root_bridge_handle()Kenji Kaneshige2009-06-161-1/+1
| | | | | | | | | | Use pci_is_root_bus() in acpi_find_root_bridge_handle() to check if the pci bus is root, for code consistency. Reviewed-by: Alex Chiang <achiang@hp.com> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: use pci_is_root_bus() in acpi_pci_get_bridge_handle()Kenji Kaneshige2009-06-161-1/+1
| | | | | | | | | | Use pci_is_root_bus() in acpi_pci_get_bridge_handle() to check if the pci bus is root, for code consistency. Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Reviewed-by: Alex Chiang <achiang@hp.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI quirk: HP hides SMBus controller in Compaq nx9500 laptopsMichal Miroslaw2009-06-161-0/+1
| | | | | | | | | I found no references to SMBus in ACPI DSDT disassembly on my laptop so this should be safe. Signed-off-by: Michal Miroslaw <mirq-linux@rere.qmqm.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI quirk: unhide 'Overflow' device on i828{6,7}5P/PE chipsetsMichal Miroslaw2009-06-161-0/+22
| | | | | | | | | | | | | | | | | Some BIOSes hide 'overflow' device (dev #6) for i82875P/PE chipsets. The same happens for i82865P/PE. Add a quirk to enable this device. This allows i82875 EDAC driver to bind to chipset's dev #6 and not dev #0 as the latter is used by AGP driver. On my laptop (i82865P based) ACPI code is disabling this device again in \_SB.PCI0._CRS method (called at least at PNP init time). This can be easily worked around by patching DSDT. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Michal Miroslaw <mirq-linux@rere.qmqm.pl> Acked-by: Doug Thompson <norsk5@yahoo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: expose SMBus on Asus notebook A6LMats Erik Andersson2009-06-111-0/+1
| | | | | | | | | Addition of one unknown subsystem identifier to the quirks handler for chipset i82855GM_HB on notebook Asus A6L. This exposes the otherwise hidden SMBus controller within the south bridge ICH4-M. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: Add support for turning PCIe ECRC on or offAndrew Patterson2009-06-117-7/+174
| | | | | | | | | | | | | | | | | | | | | Adds support for PCI Express transaction layer end-to-end CRC checking (ECRC). This patch will enable/disable ECRC checking by setting/clearing the ECRC Check Enable and/or ECRC Generation Enable bits for devices that support ECRC. The ECRC setting is controlled by the "pci=ecrc=<policy>" command-line option. If this option is not set or is set to 'bios", the enable and generation bits are left in whatever state that firmware/BIOS set them to. The "off" setting turns them off, and the "on" option turns them on (if the device supports it). Turning ECRC on or off can be a data integrity versus performance tradeoff. In theory, turning it on will catch more data errors, turning it off means possibly better performance since CRC does not need to be calculated by the PCIe hardware and packet sizes are reduced. Signed-off-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI PM: Follow PCI_PM_CTRL_NO_SOFT_RESET during transitions from D3Rafael J. Wysocki2009-06-111-0/+2
| | | | | | | | | | | | | | | | | | | | According to the PCI PM specification (PCI Bus Power Management Interface Specification, Rev. 1.2, Section 5.4.1) we are supposed to reinitialize devices that have PCI_PM_CTRL_NO_SOFT_RESET clear during all transitions from PCI_D3hot to PCI_D0, but we only do it if the device's current_state field is equal to PCI_UNKNOWN. This may lead to problems if a device with PCI_PM_CTRL_NO_SOFT_RESET unset is put into PCI_D3hot at run time by its driver and pci_set_power_state() is used to put it back into PCI_D0, because in that case the device will remain uninitialized after pci_set_power_state() has returned. Prevent that from happening by modifying pci_raw_set_power_state() to reinitialize devices with PCI_PM_CTRL_NO_SOFT_RESET unset during all transitions from D3 to D0. Cc: stable@kernel.org Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: fix SR-IOV function dependency link problemYu Zhao2009-06-111-0/+2
| | | | | | | | | | | | | | PCIe root complex integrated endpoint does not implement ARI, so this kind of endpoint uses 3-bit function number. The function dependency link of the integrated endpoint should be calculated using the device number plus the value from function dependency link register. Normal endpoint always implements ARI and the function dependency link register contains 8-bit function number (i.e. `devfn' from software's perspective). Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: eliminate redundant pci_stop_dev() call from pci_destroy_dev()Alex Chiang2009-06-111-2/+0
| | | | | | | | | | We always call pci_stop_bus_device before calling pci_destroy_dev. Since pci_stop_bus_device calls pci_stop_dev, there is no need for pci_destroy_dev to repeat the call. Signed-off-by: Alex Chiang <achiang@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI MSI: let drivers retry when not enough vectorsMichael S. Tsirkin2009-06-111-3/+3
| | | | | | | | | | | | | pci_enable_msix currently returns -EINVAL if you ask for more vectors than supported by the device, which would typically cause fallback to regular interrupts. It's better to return the table size, making the driver retry MSI-X with less vectors. Reviewed-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: disable ASPM on VIA root-port-under-bridge configurationsShaohua Li2009-06-111-0/+4
| | | | | | | | | | VIA has a strange chipset, it has root port under a bridge. Disable ASPM for such strange chipset. Cc: stable@kernel.org Tested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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