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* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-08-07156-3036/+5486
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "This is the main pull request for 3.17. It contains: - misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy updates - MIPS ptrace updates and cleanups - various fixes that will also go to -stable - a number of cleanups and small non-critical fixes. - NUMA support for the Loongson 3. - more support for MSA - support for MAAR - various FP enhancements and fixes" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) MIPS: jz4740: remove unnecessary null test before debugfs_remove MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive MIPS: ZBOOT: implement stack protector in compressed boot phase MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT MIPS: Bonito64: remove a duplicate define MIPS: Malta: initialise MAARs MIPS: Initialise MAARs MIPS: detect presence of MAARs MIPS: define MAAR register accessors & bits MIPS: mark MSA experimental MIPS: Don't build MSA support unless it can be used MIPS: consistently clear MSA flags when starting & copying threads MIPS: 16 byte align MSA vector context MIPS: disable preemption whilst initialising MSA MIPS: ensure MSA gets disabled during boot MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains MIPS: fix MSA context for tasks which don't use FP first MIPS: init upper 64b of vector registers when MSA is first used MIPS: save/disable MSA in lose_fpu MIPS: preserve scalar FP CSR when switching vector context ...
| * Merge branch '3.16-fixes' into mips-for-linux-nextRalf Baechle2014-08-0215-28/+116
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| | * MIPS: bugfix: missed cache flush of TLB refill handlerLeonid Yegoshin2014-08-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit Commit 1d40cfcd3442a53e98468cdb3e6d4d9a568d76cf Author: Ralf Baechle <ralf@linux-mips.org> Date: Fri Jul 15 15:23:23 2005 +0000 Avoid SMP cacheflushes. This is a minor optimization of startup but will also avoid smp_call_function from doing stupid things when called from a CPU that is not yet marked online. missed an appropriate cache flush of TLB refill handler because that time it was at fixed location CAC_BASE. After years the refill handler in EBASE vector is not at that location and can be allocated in some another memory and needs I-cache sync as other TLB exception vectors. Besides that, the new function - local_flash_icache_range() was introduced to avoid SMP cacheflushes. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: paul.gortmaker@windriver.com Cc: jchandra@broadcom.com Cc: linux-kernel@vger.kernel.org Cc: david.daney@cavium.com Patchwork: https://patchwork.linux-mips.org/patch/7312/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: Jz4740: Rename usb_nop_xceiv to usb_phy_genericApelete Seketeli2014-08-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename usb_nop_xceiv to usb_phy_generic in platform data to match the name change of the nop transceiver driver in commit 4525bee (usb: phy: rename usb_nop_xceiv to usb_phy_generic). The name change induced a kernel panic due to an unhandled kernel unaligned access while trying to dereference musb->xceiv->io_ops in musb_init_controller(). Signed-off-by: Apelete Seketeli <apelete@seketeli.net> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Cc: John Crispin <blogic@openwrt.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7263/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: smp-mt: Fix link error when PROC_FS=nJames Hogan2014-08-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d6d3c9afaab4 (MIPS: MT: proc: Add support for printing VPE and TC ids) causes a link error when CONFIG_PROC_FS=n: arch/mips/built-in.o: In function `proc_cpuinfo_notifier_init': smp-mt.c: undefined reference to `register_proc_cpuinfo_notifier' This is fixed by adding an ifdef around the procfs handling code in smp-mt.c. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reported-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # >= 3.15 Patchwork: https://patchwork.linux-mips.org/patch/7244/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: N32: Use compat getsockopt syscallSorin Dumitru2014-08-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IP_PKTOPTIONS sockopt puts control messages in option_values, these need to be handled differently in the compat case. This is already done through the MSG_CMSG_COMPAT flag, we just need to use compat_sys_getsockopt which sets that flag. Signed-off-by: Sorin Dumitru <sdumitru@ixiacom.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7115/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: APRP: Fix an issue when device_create() fails.Sebastien Bourdelin2014-08-012-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a call to device_create() fails for a channel during the initialize loop, we need to clean the devices entries already created before leaving. Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: Qais Yousef <Qais.Yousef@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: Jerome Oufella <jerome.oufella@savoirfairelinux.com> Patchwork: https://patchwork.linux-mips.org/patch/7111/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: GIC: Prevent array overrunJeffrey Deans2014-07-311-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A GIC interrupt which is declared as having a GIC_MAP_TO_NMI_MSK mapping causes the cpu parameter to gic_setup_intr() to be increased to 32, causing memory corruption when pcpu_masks[] is written to again later in the function. Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7375/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: Remove BUG_ON(!is_fpu_owner()) in do_ade()Huacai Chen2014-07-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In do_ade(), is_fpu_owner() isn't preempt-safe. For example, when an unaligned ldc1 is executed, do_cpu() is called and then FPU will be enabled (and TIF_USEDFPU will be set for the current process). Then, do_ade() is called because the access is unaligned. If the current process is preempted at this time, TIF_USEDFPU will be cleard. So when the process is scheduled again, BUG_ON(!is_fpu_owner()) is triggered. This small program can trigger this BUG in a preemptible kernel: int main (int argc, char *argv[]) { double u64[2]; while (1) { asm volatile ( ".set push \n\t" ".set noreorder \n\t" "ldc1 $f3, 4(%0) \n\t" ".set pop \n\t" ::"r"(u64): ); } return 0; } V2: Remove the BUG_ON() unconditionally due to Paul's suggestion. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jie Chen <chenj@lemote.com> Signed-off-by: Rui Wang <wangr@lemote.com> Cc: <stable@vger.kernel.org> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ftrace: Fix dynamic tracing of kernel modulesPetri Gynther2014-07-302-9/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dynamic tracing of kernel modules is broken on 32-bit MIPS. When modules are loaded, the kernel crashes when dynamic tracing is enabled with: cd /sys/kernel/debug/tracing echo > set_ftrace_filter echo function > current_tracer 1) arch/mips/kernel/ftrace.c When the kernel boots, or when a module is initialized, ftrace_make_nop() modifies every _mcount call site to eliminate the ftrace overhead. However, when ftrace is later enabled for a call site, ftrace_make_call() does not currently restore the _mcount call correctly for module call sites. Added ftrace_modify_code_2r() and modified ftrace_make_call() to fix this. 2) arch/mips/kernel/mcount.S _mcount assembly routine is supposed to have the caller's _mcount call site address in register a0. However, a0 is currently not calculated correctly for module call sites. a0 should be (ra - 20) or (ra - 24), depending on whether the kernel was built with KBUILD_MCOUNT_RA_ADDRESS or not. This fix has been tested on Broadcom BMIPS5000 processor. Dynamic tracing now works for both built-in functions and module functions. Signed-off-by: Petri Gynther <pgynther@google.com> Cc: linux-mips@linux-mips.org Cc: rostedt@goodmis.org Cc: alcooperx@gmail.com Cc: cminyard@mvista.com Patchwork: https://patchwork.linux-mips.org/patch/7476/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: Prevent user from setting FCSR cause bitsPaul Burton2014-07-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If one or more matching FCSR cause & enable bits are set in saved thread context then when that context is restored the kernel will take an FP exception. This is of course undesirable and considered an oops, leading to the kernel writing a backtrace to the console and potentially rebooting depending upon the configuration. Thus the kernel avoids this situation by clearing the cause bits of the FCSR register when handling FP exceptions and after emulating FP instructions. However the kernel does not prevent userland from setting arbitrary FCSR cause & enable bits via ptrace, using either the PTRACE_POKEUSR or PTRACE_SETFPREGS requests. This means userland can trivially cause the kernel to oops on any system with an FPU. Prevent this from happening by clearing the cause bits when writing to the saved FCSR context via ptrace. This problem appears to exist at least back to the beginning of the git era in the PTRACE_POKEUSR case. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7438/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: math-emu: Fix instruction decoding.Rob Kendrick2014-07-301-1/+1
| | | | | | | | | | | | | | | | | | Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: tlbex: Fix a missing statement for HUGETLBHuacai Chen2014-07-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 2c8c53e28f1 (MIPS: Optimize TLB handlers for Octeon CPUs) build_r4000_tlb_refill_handler() is modified. But it doesn't compatible with the original code in HUGETLB case. Because there is a copy & paste error and one line of code is missing. It is very easy to produce a bug with LTP's hugemmap05 test. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Binbin Zhou <zhoubb@lemote.com> Cc: <stable@vger.kernel.org> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7496/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: RB532: Fix reregistering of serial consoleWaldemar Brodkorb2014-07-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Runtime tested on Mikrotik RB532 board. Thanks goes to Geert Uytterhoeven for the explanation of the problem. "I'm afraid this is not gonna help. When the port is unregistered, its type will be reset to PORT_UNKNOWN. So before registering it again, its type must be set again the actual serial driver, cfr. the change to of_serial.c." Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> Reviewed-by: Florian Fainelli <florian@openwrt.org> Cc: Linux MIPS Mailing List <linux-mips@linux-mips.org> Cc: geert@linux-m68k.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7241/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: IP22: Add missing put_device callLevente Kurusa2014-07-301-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required so that we give up the last reference to the device. Also, create a gio_bus_release() that calls kfree on the device argument to properly kfree() the memory allocated for the device. [ralf@linux-mips.org: Reformat to Linux coding style and make gio_bus_release static.] Signed-off-by: Levente Kurusa <levex@linux.com> Cc: LKML <linux-kernel@vger.kernel.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6261/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: TXx9: 7segled: add missing put_device callLevente Kurusa2014-07-301-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required so that we give up the last reference to the device. Also, add a new tx_7segled_release function which will be called after the put_device to ensure that device is kfree'd. [ralf@linux-mips.org: Reformat to Linux coding style and make tx_7segled_release static.] Signed-off-by: Levente Kurusa <levex@linux.com> Cc: LKML <linux-kernel@vger.kernel.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6260/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: TXx9: Add missing put_device callLevente Kurusa2014-07-301-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required so that we give up the last reference to the device. Also, rework error path so that it is easier to read. [ralf@linux-mips.org: Reformat to Linux coding style and make txx9_device_release static; folded in build fix by Levente for the original patch.] Signed-off-by: Levente Kurusa <levex@linux.com> Cc: LKML <linux-kernel@vger.kernel.org> Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6259/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: jz4740: remove unnecessary null test before debugfs_removeFabian Frederick2014-08-021-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix checkpatch warning: WARNING: debugfs_remove(NULL) is safe this check is probably not required Signed-off-by: Fabian Frederick <fabf@skynet.be> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7225/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursiveFabian Frederick2014-08-021-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix checkpatch warning: WARNING: debugfs_remove_recursive(NULL) is safe this check is probably not required Signed-off-by: Fabian Frederick <fabf@skynet.be> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7224/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ZBOOT: implement stack protector in compressed boot phaseBen Chan2014-08-021-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the stack protector code in MIPS compressed boot phase based on the same code added to arm in commit 8779657d29c0ebcc0c94ede4df2f497baf1b563f "stackprotector: Introduce CONFIG_CC_STACKPROTECTOR_STRONG" by Kees Cook <keescook@chromium.org> Signed-off-by: Ben Chan <benchan@chromium.org> Cc: Kees Cook <keescook@chromium.org> Cc: Olof Johansson <olofj@chromium.org> Reviewed-by: Kees Cook <keescook@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7175/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFTDan Carpenter2014-08-021-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS_CONF4_FTLBSETS_SHIFT define is cut and pasted twice so we can remove the second define. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: kernel-janitors@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7063/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Bonito64: remove a duplicate defineDan Carpenter2014-08-021-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BONITO_PCIMEMBASECFG_ADDRMASK was cut and pasted twice so we can delete the second define. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Cc: kernel-janitors@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7062/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Malta: initialise MAARsPaul Burton2014-08-021-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialise the MAARs such that speculation is enabled for all physical addresses outside of the I/O region. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7333/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Initialise MAARsPaul Burton2014-08-022-0/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initialisation for Memory Accessibility Attribute Registers. Generic code cannot know the platform-specific requirements with regards to speculative accesses, so it simply calls a platform_maar_init function which platforms with MAARs are expected to implement by calling the provided write_maar_pair function & returning the number of MAAR pairs used. A weak default implementation will simply use no MAAR pairs. Any present but unused MAAR pairs are then marked invalid, effectively disabling them. The end result of this patch is that MAARs are all marked invalid, until platforms implement the platform_maar_init function. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7331/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: detect presence of MAARsPaul Burton2014-08-023-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Detect the presence of MAAR using the MRP bit in Config5, and record that presence using a CPU option bit. A cpu_has_maar macro will then allow code to conditionalise upon the presence of MAARs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7330/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: define MAAR register accessors & bitsPaul Burton2014-08-021-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add accessor macros for the Memory Accessibility Attribute Registers (MAARs), the bits contained within the MAARs & the Config5.MRP bit indicating their presence. The only current use of the MAARs is to enable speculative accesses to regions of memory. Besides the potential performance benefits of speculative accesses, they are a requirement for the P5600 core to handle non-128b-aligned MSA vector loads & stores rather than generating an address error. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7329/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: mark MSA experimentalPaul Burton2014-08-021-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In light of the commit 16f77de82f2d (Revert "MIPS: Save/restore MSA context around signals") the MSA support in the kernel is incomplete. Until the replacement for the former sigcontext changes is agreed upon and in tree, mark MSA experimental & disable it by default. MSA is only implemented by one CPU supported by the kernel, the P5600. The P5600 is a 32 bit core, and thus MSA can only be used when the experimental CONFIG_MIPS_O32_FP64_SUPPORT option is enabled. Therefore MSA is only being used in experimental settings anyway and this change doesn't actually make any difference beyond clarifying the state of MSA support. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7311/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Don't build MSA support unless it can be usedPaul Burton2014-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MSA requires that Status.FR == 1, so for MIPS32 tasks MSA can only be used if CONFIG_MIPS_O32_FP64_SUPPORT is enabled. If it is not & the kernel is 32bit, there's no point including support for MSA. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7310/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: consistently clear MSA flags when starting & copying threadsPaul Burton2014-08-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TIF_MSA_CTX_LIVE flag (indicating that a task has MSA context which needs to be preserved) was being cleared in start_thread, but the TIF_USEDMSA flag (indicating that a task has used MSA in this timeslice) was not. In copy_thread neither flag was cleared, but both need to be. Without clearing these flags the kernel will proceed to attempt to save MSA context when the task is context switched out, and if the task had not used MSA in the meantime then it will fail because MSA or the FPU are disabled. The end result is typically: do_cpu invoked from kernel context![#1]: CPU: 0 PID: 99 Comm: sh Not tainted 3.16.0-rc4-00025-g6dc9476-dirty #88 task: 8f23dc60 ti: 8f1d8000 task.ti: 8f1d8000 ... Call Trace: [<8010edbc>] resume+0x5c/0x280 [<80481e0c>] __schedule+0x370/0x800 [<80104838>] work_resched+0x8/0x2c Fix by consistently clearing both flags in both functions. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7309/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: 16 byte align MSA vector contextPaul Burton2014-08-021-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MSA specification upon first read appears to suggest that it is safe to perform vector loads & stores with arbitrary alignment. However it leaves provision for "address-dependent exceptions"... Align the vector context to a 16 byte boundary to ensure that the kernel cannot cause any such exceptions. Note that the fpu field of struct thread_struct was already at a 16 byte boundary within the struct, the introduction of FPU_ALIGN simply makes the requirement explicit. The only part of this impacting the generated kernel binary is ARCH_MIN_TASKALIGN. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7308/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: disable preemption whilst initialising MSAPaul Burton2014-08-022-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Preemption must be disabled throughout the process of enabling the FPU, enabling MSA & initialising the vector registers. Without doing so it is possible to lose the FPU or MSA whilst initialising them causing that initialisation to fail. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7307/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ensure MSA gets disabled during bootPaul Burton2014-08-021-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel relies upon MSA being disabled when a task begins running, so that it can initialise or restore context in response to the resulting MSA disabled exception. Previously the state of MSA following boot was left as it was before the kernel ran, where MSA could potentially have been enabled. Explicitly disable it during boot to prevent any problems. As a nice side effect the code reads a little better too. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7306/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchainsPaul Burton2014-08-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d96cc3d1ec5d "MIPS: Add microMIPS MSA support." attempted to use the value of a macro within an inline asm statement but instead emitted a comment leading to the cfcmsa & ctcmsa instructions being omitted. Fix that by passing CFC_MSA_INSN & CTC_MSA_INSN as arguments to the asm statements. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7305/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: fix MSA context for tasks which don't use FP firstPaul Burton2014-08-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a task does not execute scalar FP instructions prior to using MSA then the flags indicating that the task has live MSA context were not being set. The upper 64b of each vector register would then be lost upon the tasks first context switch after using MSA. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: init upper 64b of vector registers when MSA is first usedPaul Burton2014-08-024-9/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: save/disable MSA in lose_fpuPaul Burton2014-08-021-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel depends upon MSA never being enabled when the FPU is not, a condition which is currently violated in a few places (whilst saving sigcontext, following mips_cpu_save). Catch all the problem cases by disabling MSA in lose_fpu, after saving context if necessary. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7302/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: preserve scalar FP CSR when switching vector contextPaul Burton2014-08-022-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switching the vector context implicitly saves & restores the state of the aliased scalar FP data registers, however the scalar FP control & status register is distinct from the MSA control & status register. In order to allow scalar FP to function correctly in programs using MSA, the scalar CSR needs to be saved & restored along with the MSA vector context. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7301/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: save/restore MSACSR register on context switchPaul Burton2014-08-022-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I added a field for the MSACSR register in struct mips_fpu_struct, but never actually made use of it... This is a clear bug. Save and restore the MSACSR register along with the vector registers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7300/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: allow msa.h to be included in assembly filesPaul Burton2014-08-021-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just #ifdef away the C functions when included from an assembly file, as will be done in a following commit. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7299/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: OCTEON: add interface & port definitions for D-Link DSR-1000NAaro Koskinen2014-08-021-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add interface & port definitions for D-Link DSR-1000N. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <ddaney.cavm@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7219/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: OCTEON: add USB clock type for D-Link DSR-1000NAaro Koskinen2014-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add USB clock type for D-Link DSR-1000N. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <ddaney.cavm@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7218/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: OCTEON: cvmx-bootinfo: add D-Link DSR-1000NAaro Koskinen2014-08-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a definition for D-Link DSR-1000N router. The bootloader on this board supplies 20006 in the bootinfo; the enum CVMX_BOARD_TYPE_CUST_DSR1000N comes from the GPL sources of the board. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <ddaney.cavm@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7217/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: OCTEON: disable HOTPLUG_CPU if the bootloader version is incorrectAaro Koskinen2014-08-021-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable HOTPLUG_CPU functionality if the bootloader version is incorrect. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7200/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: OCTEON: support disabling HOTPLUG_CPU run-timeAaro Koskinen2014-08-021-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If nosmp kernel option given, we can assume HOTPLUG_CPU is disabled. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7202/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: OCTEON: watchdog: don't jump to bootloader without entry addressAaro Koskinen2014-08-021-28/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_HOTPLUG_CPU is set, the driver thinks bootloader entry address is configured and we should jump there. However, this is not necessarily true if the kernel is booted on a system with older/incompatible bootloader. Add dynamic checks for the bootloader entry address. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-watchdog@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7201/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: OCTEON: SMP: delete redundant checkAaro Koskinen2014-08-021-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The same check is already done earlier in octeon_smp_hotplug_setup(). Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Patchwork: https://patchwork.linux-mips.org/patch/7199/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Document the cca= command-line parameterFlorian Fainelli2014-08-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 ("[MIPS] Allow setting of the cache attribute at run time") introduced the 'cca=' kernel command-line parameter which allows overriding the kernel pages cacheable attributes, document that parameter. [ralf@linux-mips.org: replace @mips.com email addresses with it's imgtec.com equivalent in this commit message. Rephrase slightly for a bit more pedantic correctness.] Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: anemo@mba.ocn.ne.jp Cc: chris.dearman@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/7182/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: GIC: Fix GICBIS macroJeffrey Deans2014-08-021-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICBIS macro could update the GIC registers incorrectly, depending on the data value passed in: * Bits were only OR'd into the register data, so register fields could not be cleared. * Bits were OR'd into the register data without masking the data to the correct field width, corrupting adjacent bits. Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7378/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Malta: Fix dispatching of GIC interruptsJeffrey Deans2014-08-021-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Malta malta_ipi_irqdispatch() routine now checks only IPI interrupts when handling IPIs. It could previously call do_IRQ() for non-IPIs, and also call do_IRQ() with an invalid IRQ number if there were no pending GIC interrupts when gic_get_int() was called. Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: GIC: Generalise check for pending interruptsJeffrey Deans2014-08-022-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move most of the functionality of gic_get_int() into a new function gic_get_int_mask() which takes a bitmask of interrupts in which the caller is interested, and returns the subset which are pending for the current CPU. This allows CP0 IRQ dispatch routines to check only the GIC interrupts which are routed to a particular CPU interrupt input. gic_get_int() is reimplemented using gic_get_int_mask() and is retained for use by any platforms for which gic_get_int() is sufficient. Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7376/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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