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* mmc: sdhci: add DDR50 1.8V mode support for BayTrail eMMC ControllerMaurice Petallo2014-07-102-2/+3
| | | | | | | | | This is to enable DDR50 bus speed mode with 1.8V signaling capability for BayTrail ACPI and PCI mode eMMC Controller. Signed-off-by: Maurice Petallo <mauricex.r.petallo@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Preset value not supported in Baytrail eMMCMaurice Petallo2014-07-102-0/+2
| | | | | | | | | "SDHCI_QUIRK2_PRESET_VALUE_BROKEN" quirk is added to prohibit preset value enabling for Baytrail eMMC controller. Signed-off-by: Maurice Petallo <mauricex.r.petallo@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: MMC_USDHI6ROL0 should depend on HAS_DMAGeert Uytterhoeven2014-07-101-0/+1
| | | | | | | | | | | | If NO_DMA=y: drivers/built-in.o: In function `usdhi6_dma_setup': usdhi6rol0.c:(.text+0x5c35fc): undefined reference to `dma_map_sg' drivers/built-in.o: In function `usdhi6_dma_stop_unmap': usdhi6rol0.c:(.text+0x5c3738): undefined reference to `dma_unmap_sg' Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: MMC_SH_MMCIF should depend on HAS_DMAGeert Uytterhoeven2014-07-101-1/+1
| | | | | | | | | | | | | | | If NO_DMA=y: drivers/built-in.o: In function `sh_mmcif_start_dma_tx': sh_mmcif.c:(.text+0x5a3286): undefined reference to `dma_map_sg' drivers/built-in.o: In function `sh_mmcif_start_dma_rx': sh_mmcif.c:(.text+0x5a33fc): undefined reference to `dma_map_sg' drivers/built-in.o: In function `sh_mmcif_end_cmd': sh_mmcif.c:(.text+0x5a3668): undefined reference to `dma_unmap_sg' Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: MMC_OMAP_HS should depend on HAS_DMAGeert Uytterhoeven2014-07-101-0/+1
| | | | | | | | | | | | | | | | | If NO_DMA=y: drivers/built-in.o: In function `omap_hsmmc_pre_dma_transfer': omap_hsmmc.c:(.text+0x5a0928): undefined reference to `dma_map_sg' drivers/built-in.o: In function `omap_hsmmc_dma_cleanup': omap_hsmmc.c:(.text+0x5a0e8e): undefined reference to `dma_unmap_sg' drivers/built-in.o: In function `omap_hsmmc_dma_callback': omap_hsmmc.c:(.text+0x5a1f58): undefined reference to `dma_unmap_sg' drivers/built-in.o: In function `omap_hsmmc_post_req': omap_hsmmc.c:(.text+0x5a2082): undefined reference to `dma_unmap_sg' Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-st: ST Microelectronics SDHCI binding documentation.Peter Griffin2014-07-101-0/+33
| | | | | | | | | | | | This patch adds the device tree binding documentation for the ST SDHCI driver. It documents the differences between the core properties described by mmc.txt and the properties used by the sdhci-st driver. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-st: Intial support for ST SDHCI controllerPeter Griffin2014-07-103-0/+189
| | | | | | | | | | | | | This platform driver adds initial support for the SDHCI host controller found on STMicroelectronics SoCs. It has been tested on STiH41x b2020 platforms currently. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio-mmc: Add renesas, sdhi-r8a7791 to binding documentationGeert Uytterhoeven2014-07-091-0/+1
| | | | | | | | | | | The driver already supports the r8a7791 SoC, and "renesas,sdhi-r8a7791" is already in use. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Ian Molton <ian.molton@codethink.co.uk> Cc: Chris Ball <chris@printf.net> Cc: linux-mmc@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: s3cmci: port DMA code to dmaengine APIVasily Khoruzhick2014-07-093-142/+52
| | | | | | | | Utilise new s3c24xx-dma dmaengine driver for DMA ops. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tegra: Do not include asm/gpio.hThierry Reding2014-07-091-2/+0
| | | | | | | | This doesn't seem to be used any longer and removing the include fixes 64-bit ARM builds. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mxs: fix card detection in case of 'broken-cd' flag setRoman Peniaev2014-07-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of reboot my olinuxino imx23 board does not see mmc card any more. mmc_rescan is being called by delayed work in loop, but mxs_mmc_get_cd always returns 0, so we will never pass the card detection check and will not do further card inition. This patch is just an attempt to partially revert the patch a91fe279ae of Sascha Hauer, where it is claimed that upper layer will handle broken card detection using the polling logic and MMC_CAP_NEEDS_POLL capability, but seems it is not true, because upper logic still expects 1 from 'get_cd'. So, here we always return 1 (card present) in case of MMC_CAP_NEEDS_POLL capability set. Signed-off-by: Roman Pen <r.peniaev@gmail.com> CC: Chris Ball <chris@printf.net> CC: Sascha Hauer <s.hauer@pengutronix.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Shawn Guo <shawn.guo@linaro.org> CC: Ulf Hansson <ulf.hansson@linaro.org> CC: linux-mmc@vger.kernel.org CC: linux-kernel@vger.kernel.org Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: s3cmci: Move to clk_prepare_enable/clk_disable_unprepareVasily Khoruzhick2014-07-091-3/+3
| | | | | | | | Use clk_prepare_enable/clk_disable_unprepare to make the driver work properly with common clock framework. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: Allow forward compatibility for eMMCRomain Izard2014-07-091-6/+5
| | | | | | | | | | | | As stated by the eMMC 5.0 specification, a chip should not be rejected only because of the revision stated in the EXT_CSD_REV field of the EXT_CSD register. Remove the control on this value, the control of the CSD_STRUCTURE field should be sufficient to reject future incompatible changes. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Replace host->mmc with mmc where possibleMarkus Mayer2014-07-091-15/+15
| | | | | | | | | | After the switch to the MMC core regulator infrastucture, we already have a local "mmc" pointer in various functions. There is no longer a need to access the data structure via host->mmc. Signed-off-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: avoid double-delay while transitioning to 1.8VRussell King2014-07-091-3/+0
| | | | | | | | | The MMC core in mmc_set_signal_voltage() already provides for the delay required to switch to 1.8V, so there is no need for drivers to perform this wait themselves. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-pci: SDIO host controller support for Intel Quark X1000Derek Browne2014-07-092-0/+13
| | | | | | | | This patch is to enable SDIO host controller for Intel Quark X1000. Signed-off-by: Derek Browne <Derek.Browne@intel.com> Signed-off-by: Alvin (Weike) Chen <alvin.chen@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Remove blank lineUlf Hansson2014-07-091-1/+0
| | | | | | | | | While merging the sdhci patchset from Russell King, somehow a blank line was left behind. Let's correct the formatting. Cc: Chris Ball <chris@printf.net> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Improve external VDD regulator supportTim Kryger2014-07-091-7/+9
| | | | | | | | | | | | | | | | | | | | | | A standard compliant SDHCI can itself supply VDD at 1.8, 3.0, or 3.3v. Several vendors ignore this and instead rely upon external regulators to supply VDD. While the external regulators typically can supply one of the standard SDHCI voltage levels, there is no real reason for this to be a hard requirement. This patch alters the SDHCI driver such that external VDD regulators that provide voltages other than the three mentioned above may be used so long as they can supply a voltage that meets the needs of the card. In the case that an external VDD regulator is provided, it is reasonable to ignore the voltage capabilities of the host controller and allow the external regulator to set the OCR mask. Additionally, there is no need to convert a VDD voltage request into one of the standard SDHCI voltage levels or program it in the host controller's power control register. Signed-off-by: Tim Kryger <tim.kryger@gmail.com> Tested-by: Sachin Kamat <spk.linux@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core: Fix DT documentation of eMMC high-speed DDR 1.8/1.2V bindingsPeter Griffin2014-07-091-2/+2
| | | | | | | | Currently the documentation doesn't match the code in mmc_of_parse. This patch rectifies this. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: wmt-sdmmc: Remove deprecated IRQF_DISABLEDAxel Lin2014-07-091-1/+1
| | | | | | | | | It's a NOOP since 2.6.35 and it will be removed one day. This is not trivial because current code uses hard coded 32 instead of IRQF_DISABLED in the request_irq call. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: wmt-sdmmc: Fix settting BM_EIGHTBIT_MODE bit in wmt_mci_set_ios()Axel Lin2014-07-091-16/+15
| | | | | | | | | | | | | | | | | | | | | | | For MMC_BUS_WIDTH_8 case, current code missed setting BM_EIGHTBIT_MODE bit. Also has a small refactor to make the code looks better in readability. So the bit settings witch below logic: SDMMC_BUSMODE register: Set EIGHTBIT_MODE bit for 8 bit mode, Set FOURBIT_MODE bit for 4 bit mode. Clear both EIGHTBIT_MODE and FOURBIT_MODE bits for 1 bit mode. SDMMC_EXTCTRL register: Set EXT_EIGHTBIT bit for 8 bit mode, Clear EXT_EIGHTBIT bit for 1/4 bit mode. Add define for EXT_EIGHTBIT to avoid using magic number. BM_ONEBIT_MASK is no longer used, thus remove it. This patch is untested due to lack of platform with 8-bit hardware. However since the code is there, it's good to make the code match the document. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sd: warn if card stays busy during initJohan Rudholm2014-07-091-0/+3
| | | | | | | | | The initialization of some SD-cards fails because the card never leaves the busy state. Aid trouble shooting by indicating this in the kernel log. Signed-off-by: Johan Rudholm <johanru@axis.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: moxart: Remove unneeded version.h inclusionSachin Kamat2014-07-091-1/+0
| | | | | | | | version.h inclusion is not needed as suggested by versioncheck. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: omap_hsmmc: Pin remux workaround to support SDIO interrupt on AM335xAndreas Fenkart2014-07-092-3/+74
| | | | | | | | | | | | | | | | The am335x can't detect pending cirq in PM runtime suspend. This patch reconfigures dat1 as a GPIO before going to suspend. SDIO interrupts are detected with the GPIO, the GPIO will only wake the module from suspend, SDIO irq detection will still happen through the IP block. Idea of remuxing the pins by Tony Lindgren. Code contributions from Tony Lindgren and Balaji T K <balajitk@ti.com> Signed-off-by: Andreas Fenkart <afenkart@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Acked-by: Balaji T K <balajitk@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: omap_hsmmc: switch default/idle pinctrl states in runtime hooksAndreas Fenkart2014-07-091-6/+10
| | | | | | | | | | | | | | | These are predefined states of the driver model. When not present, as if not set in the device tree, they become no-ops. Explicitly selecting the default state is not needed since the device core layer sets pin mux to "default" state before probe. This is not the simplest implementation, on AM335x at least, we could switch to idle at any point in the suspend hook, only the default state needs to be set before writing to the irq registers or an IRQ might get lost. Acked-by: Balaji T K <balajitk@ti.com> Signed-off-by: Andreas Fenkart <afenkart@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: omap_hsmmc: abort runtime suspend if pending sdio irq detectedAndreas Fenkart2014-07-091-2/+21
| | | | | | | | | | | | On multicores, an sdio irq handler could be running in parallel to runtime suspend. In the worst case it could be waiting for the spinlock held by the runtime suspend. When runtime suspend is complete and the functional clock (fclk) turned off, the irq handler will continue and cause a SIGBUS on the first register access. Acked-by: Balaji T K <balajitk@ti.com> Signed-off-by: Andreas Fenkart <afenkart@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: omap_hsmmc: enable wakeup event for sdio OMAP4Balaji T K2014-07-091-1/+13
| | | | | | | | | To detect sdio irqs properly without spurious events, OMAP4 needs IWE in CON and CTPL, CLKEXTFREE in HCTL to be set Tested-by: Andreas Fenkart <afenkart@gmail.com> Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: omap_hsmmc: Extend debugfs by SDIO IRQ handling, runtime stateAndreas Fenkart2014-07-091-3/+14
| | | | | | | | | Add SDIO IRQ entries to debugfs entry. Note that PSTATE shows current state of data lines, incl. SDIO IRQ pending Signed-off-by: Andreas Fenkart <afenkart@gmail.com> Acked-by: Balaji T K <balajitk@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: omap_hsmmc: Enable SDIO interruptAndreas Fenkart2014-07-093-12/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There have been various patches floating around for enabling the SDIO IRQ for hsmmc, but none of them ever got merged. Probably the reason for not merging the SDIO interrupt patches has been the lack of wake-up path for SDIO on some omaps that has also needed remuxing the SDIO DAT1 line to a GPIO making the patches complex. This patch adds the minimal SDIO IRQ support to hsmmc for omaps that do have the wake-up path. For those omaps, the DAT1 line need to have the wake-up enable bit set, and the wake-up interrupt is the same as for the MMC controller. This patch has been tested on am3730 es1.2 with mwifiex connected to MMC3 with mwifiex waking to Ethernet traffic from off-idle mode. Note that for omaps that do not have the SDIO wake-up path, this patch will not work for idle modes and further patches for remuxing DAT1 to GPIO are needed. Based on earlier patches [1][2] by David Vrabel <david.vrabel@csr.com>, Steve Sakoman <steve@sakoman.com> For now, only support SDIO interrupt if we are booted with a separate wake-irq configued via device tree. This is because omaps need the wake-irq for idle states, and some omaps need special quirks. And we don't want to add new legacy mux platform init code callbacks any longer as we are moving to DT based booting anyways. To use it, you need to specify the wake-irq using the interrupts-extended property. [1] http://www.sakoman.com/cgi-bin/gitweb.cgi?p=linux.git;a=commitdiff_plain;h=010810d22f6f49ac03da4ba384969432e0320453 [2] http://comments.gmane.org/gmane.linux.kernel.mmc/20446 Acked-by: Balaji T K <balajitk@ti.com> Signed-off-by: Andreas Fenkart <afenkart@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: quirks: Fixup debug messageAlexander Stein2014-07-091-1/+1
| | | | | | | | | | There is no need for an output like this: > mmcblk mmc1:0001: calling add_quirk_mmc+0x0/0x20 Instead use this one: > mmcblk mmc1:0001: calling add_quirk_mmc Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sh-mmcif: final error path cleanupBen Dooks2014-07-091-4/+2
| | | | | | | | | Remove the error path items that are no longer needed. The mmc card-detect code cleans up after itself (and registers with devm) and the host error is the same as the clock disable. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sh-mmcif: no need to call pm_runtime_suspend on errorBen Dooks2014-07-091-4/+2
| | | | | | | | | | The pm_runtime call should implicitly disable the device once the probe is over if there is no explicit reference gained. There is no need to call pm_runtime_suspend() before the pm_runtime_disable() call. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sh-mmcif: use devm_ for irq managementBen Dooks2014-07-091-18/+8
| | | | | | | | | Use devm_request_threaded_irq() for the host interrupt handlers so we do not have to worry about freeing them on exit or error. Tidies up the exit path code for the driver. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sh-mmcif: use devm_ for clock managementBen Dooks2014-07-091-10/+8
| | | | | | | | Use the devm_clk_get() code to get the clock and allow it to be freed automatically on release. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sh-mmcif: use devm_ for ioremapBen Dooks2014-07-091-18/+6
| | | | | | | | Start tidying the probe/release code by using devm_ioremap_resource() to map the IO registers. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sh-mmcif: update to print version and bus clock rate on probeBen Dooks2014-07-091-4/+5
| | | | | | | | | Change the initial print to show chip version and the bus rate it is working at instead of the driver version. This is more useful information as we already know which driver version from the kernel it is in. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Remove unused ret variablesMarkus Pargmann2014-07-091-4/+3
| | | | | | | | Remove those unused ret variables to make it obvious that these function will not return any errors in the current implementation. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Use mmc core regulator infrastuctureTim Kryger2014-07-092-64/+36
| | | | | | | | | | | | | | | | Switch the common SDHCI code over to use mmc_host's regulator pointers and remove the ones in the sdhci_host structure. Additionally, use the common mmc_regulator_get_supply function to get the regulators and set the ocr_avail mask. This change sets the ocr_avail directly based upon the voltage ranges supported which ensures ocr_avail is set correctly while allowing the use of regulators that can't provide exactly 1.8v, 3.0v, or 3.3v. Signed-off-by: Tim Kryger <tim.kryger@gmail.com> Signed-off-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core: Remove redundant runtime_idle callbackUlf Hansson2014-07-091-9/+1
| | | | | | | | The runtime PM core handles a runtime_idle callback set to NULL as one returning 0. So, let's just set it to NULL instead. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: mmci: Add Qualcomm Id to amba id tableSrinivas Kandagatla2014-07-091-0/+23
| | | | | | | | | | | This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm SDCC controller is pl180, but amba id registers read 0x0's. The plan is to remove SDCC driver totally and use mmci as the main SD controller driver for Qualcomm SOCs. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: Add Qcom specific rx_fifocnt logic.Srinivas Kandagatla2014-07-092-2/+29
| | | | | | | | | | | | | | | | | | | | | MCIFIFOCNT register behaviour on Qcom chips is very different than the other pl180 integrations. MCIFIFOCNT register contains the number of words that are still waiting to be transferred through the FIFO. It keeps decrementing once the host CPU reads the MCIFIFO. With the existing logic and the MCIFIFOCNT behaviour, mmci_pio_read will loop forever, as the FIFOCNT register will always return transfer size before reading the FIFO. Also the data sheet states that "This register is only useful for debug purposes and should not be used for normal operation since it does not reflect data which may or may not be in the pipeline". This patch implements a qcom specific get_rx_fifocnt function which is implemented based on status register flags. Based on qcom_fifo flag in variant data structure, the corresponding get_rx_fifocnt function is selected. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: add explicit clk controlSrinivas Kandagatla2014-07-092-3/+28
| | | | | | | | | | | | | | On Controllers like Qcom SD card controller where cclk is mclk and mclk should be directly controlled by the driver. This patch adds support to control mclk directly in the driver, and also adds explicit_mclk_control flag in variant structure giving more flexibility to the driver. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> [Ulf Hansson] Fixed checkpatch warning Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: add f_max to variant structureSrinivas Kandagatla2014-07-091-2/+11
| | | | | | | | | | | Some of the controller have maximum supported frequency, This patch adds support in variant data structure to specify such restrictions. This gives more flexibility in calculating the f_max before passing it to mmc-core. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: Add support to data commands via variant structure.Srinivas Kandagatla2014-07-091-0/+5
| | | | | | | | | | | On some SOCs like Qcom there are explicit bits in the command register to specify if its a data transfer command or not. So this patch adds support to such bits in variant data, giving more flexibility to the driver. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: add edge support to data and command out in variant data.Srinivas Kandagatla2014-07-091-1/+5
| | | | | | | | | | | | | | This patch adds edge support for data and command out to variant structure giving more flexibility to the driver to support more SOCs which have different clock register layout. Without this patch other new SOCs like Qcom will have to add more code to special case them Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> [Ulf Hansson] Resolved conflict Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: add 8bit bus support in variant dataSrinivas Kandagatla2014-07-091-1/+6
| | | | | | | | | | | | | This patch adds 8bit bus enable to variant structure giving more flexibility to the driver to support more SOCs which have different clock register layout. Without this patch other new SOCs like Qcom will have to add more code to special case them. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> [Ulf Hansson] Resolved conflict Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: add ddrmode mask to variant dataSrinivas Kandagatla2014-07-091-1/+4
| | | | | | | | | | | | | | This patch adds ddrmode mask to variant structure giving more flexibility to the driver to support more SOCs which have different datactrl register layout. Without this patch datactrl register is updated with incorrect ddrmode mask, resulting in failures on Qualcomm SD Card Controller. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> [Ulf Hansson] Resolved conflict Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: Add Qcom datactrl register variantSrinivas Kandagatla2014-07-091-0/+5
| | | | | | | | | | Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl register. Bit position datactrl[16:4] hold the true block size instead of power of 2. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: Add enough delay between writes to CMD register.Srinivas Kandagatla2014-07-091-1/+1
| | | | | | | | | | | | | | | | | | | On Qcom SD Card controller POWER, CLKCTRL, DATACTRL and COMMAND registers should be updated in MCLK domain, and writes to these registers must be separated by three MCLK cycles. This resitriction is not applicable for other registers. Any subsequent writes to these register will be ignored until 3 MCLK have passed. One usec delay between two CMD register writes is not sufficient in the card identification phase where the CCLK is very low. This patch replaces a static 1 usec delay to use mmci_reg_delay function which can provide correct delay depending on the cclk frequency. Without this patch the card is not detected. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: Add Qualcomm specific register defines.Srinivas Kandagatla2014-07-091-0/+17
| | | | | | | | | | This patch adds a Qualcomm SD Card controller specific register variations to header file. Qualcomm SDCC controller is pl180, with slight changes in the register layout from standard pl180 register set. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 13:20:31 +0100