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* powerpc/powernv: Return to cpu offline loop when finished in KVM guestPaul Mackerras2014-12-085-25/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a secondary hardware thread has finished running a KVM guest, we currently put that thread into nap mode using a nap instruction in the KVM code. This changes the code so that instead of doing a nap instruction directly, we instead cause the call to power7_nap() that put the thread into nap mode to return. The reason for doing this is to avoid having the KVM code having to know what low-power mode to put the thread into. In the case of a secondary thread used to run a KVM guest, the thread will be offline from the point of view of the host kernel, and the relevant power7_nap() call is the one in pnv_smp_cpu_disable(). In this case we don't want to clear pending IPIs in the offline loop in that function, since that might cause us to miss the wakeup for the next time the thread needs to run a guest. To tell whether or not to clear the interrupt, we use the SRR1 value returned from power7_nap(), and check if it indicates an external interrupt. We arrange that the return from power7_nap() when we have finished running a guest returns 0, so pending interrupts don't get flushed in that case. Note that it is important a secondary thread that has finished executing in the guest, or that didn't have a guest to run, should not return to power7_nap's caller while the kvm_hstate.hwthread_req flag in the PACA is non-zero, because the return from power7_nap will reenable the MMU, and the MMU might still be in guest context. In this situation we spin at low priority in real mode waiting for hwthread_req to become zero. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/book3s: Fix partial invalidation of TLBs in MCE code.Mahesh Salgaonkar2014-12-051-2/+2
| | | | | | | | | | | The existing MCE code calls flush_tlb hook with IS=0 (single page) resulting in partial invalidation of TLBs which is not right. This patch fixes that by passing IS=0xc00 to invalidate whole TLB for successful recovery from TLB and ERAT errors. Cc: stable@vger.kernel.org Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/mm: don't do tlbie for updatepp request with NO HPTE faultAneesh Kumar K.V2014-12-0516-57/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | upatepp can get called for a nohpte fault when we find from the linux page table that the translation was hashed before. In that case we are sure that there is no existing translation, hence we could avoid doing tlbie. We could possibly race with a parallel fault filling the TLB. But that should be ok because updatepp is only ever relaxing permissions. We also look at linux pte permission bits when filling hash pte permission bits. We also hold the linux pte busy bits while inserting/updating a hashpte entry, hence a paralle update of linux pte is not possible. On the other hand mprotect involves ptep_modify_prot_start which cause a hpte invalidate and not updatepp. Performance number: We use randbox_access_bench written by Anton. Kernel with THP disabled and smaller hash page table size. 86.60% random_access_b [kernel.kallsyms] [k] .native_hpte_updatepp 2.10% random_access_b random_access_bench [.] doit 1.99% random_access_b [kernel.kallsyms] [k] .do_raw_spin_lock 1.85% random_access_b [kernel.kallsyms] [k] .native_hpte_insert 1.26% random_access_b [kernel.kallsyms] [k] .native_flush_hash_range 1.18% random_access_b [kernel.kallsyms] [k] .__delay 0.69% random_access_b [kernel.kallsyms] [k] .native_hpte_remove 0.37% random_access_b [kernel.kallsyms] [k] .clear_user_page 0.34% random_access_b [kernel.kallsyms] [k] .__hash_page_64K 0.32% random_access_b [kernel.kallsyms] [k] fast_exception_return 0.30% random_access_b [kernel.kallsyms] [k] .hash_page_mm With Fix: 27.54% random_access_b random_access_bench [.] doit 22.90% random_access_b [kernel.kallsyms] [k] .native_hpte_insert 5.76% random_access_b [kernel.kallsyms] [k] .native_hpte_remove 5.20% random_access_b [kernel.kallsyms] [k] fast_exception_return 5.12% random_access_b [kernel.kallsyms] [k] .__hash_page_64K 4.80% random_access_b [kernel.kallsyms] [k] .hash_page_mm 3.31% random_access_b [kernel.kallsyms] [k] data_access_common 1.84% random_access_b [kernel.kallsyms] [k] .trace_hardirqs_on_caller Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/xmon: Cleanup the breakpoint flagsMichael Ellerman2014-12-021-10/+9
| | | | | | | Drop BP_IABR_TE, which though used, does not do anything useful. Rename BP_IABR to BP_CIABR. Renumber the flags. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/xmon: Enable HW instruction breakpoint on POWER8Anshuman Khandual2014-12-021-7/+51
| | | | | | | | | | | | | | | | | | | | | | | | This patch enables support for hardware instruction breakpoint in xmon on POWER8 platform with the help of a new register called the CIABR (Completed Instruction Address Breakpoint Register). With this patch, a single hardware instruction breakpoint can be added and cleared during any active xmon debug session. The hardware based instruction breakpoint mechanism works correctly with the existing TRAP based instruction breakpoint available on xmon. There are no powerpc CPU with CPU_FTR_IABR feature any more. This patch has re-purposed all the existing IABR related code to work with CIABR register based HW instruction breakpoint. This has one odd feature, which is that when we hit a breakpoint xmon doesn't tell us we have hit the breakpoint. This is because xmon is expecting bp->address == regs->nip. Because CIABR fires on completition regs->nip points to the instruction after the breakpoint. We could fix that, but it would then confuse other parts of the xmon code which think we need to emulate the instruction. [mpe] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
* Merge remote-tracking branch 'benh/next' into nextMichael Ellerman2014-12-0218-284/+162
|\ | | | | | | | | Merge updates collected & acked by Ben. A few EEH patches from Gavin, some mm updates from Aneesh and a few odds and ends.
| * powerpc/mm/thp: Use tlbiel if possibleAneesh Kumar K.V2014-12-027-13/+37
| | | | | | | | | | | | | | | | If we know that user address space has never executed on other cpus we could use tlbiel. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/mm/thp: Remove code duplicationAneesh Kumar K.V2014-12-024-108/+65
| | | | | | | | | | | | | | | | Rename invalidate_old_hpte to flush_hash_hugepage and use that in other places. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/mm/hugetlb: Sanity check gigantic hugepage countJames Yang2014-12-021-0/+7
| | | | | | | | | | | | | | | | Limit the number of gigantic hugepages specified by the hugepages= parameter to MAX_NUMBER_GPAGES. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/oprofile: Disable pagefaults during user stack readJiang Lu2014-12-021-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A page fault occurred during reading user stack in oprofile backtrace would lead following calltrace: WARNING: at linux/kernel/smp.c:210 Modules linked in: CPU: 5 PID: 736 Comm: sh Tainted: G W 3.14.23-WR7.0.0.0_standard #1 task: c0000000f6208bc0 ti: c00000007c72c000 task.ti: c00000007c72c000 NIP: c0000000000ed6e4 LR: c0000000000ed5b8 CTR: 0000000000000000 REGS: c00000007c72f050 TRAP: 0700 Tainted: G W (3.14.23-WR7.0.0 tandard) MSR: 0000000080021000 <CE,ME> CR: 48222482 XER: 00000000 SOFTE: 0 GPR00: c0000000000ed5b8 c00000007c72f2d0 c0000000010aa048 0000000000000005 GPR04: c000000000fdb820 c00000007c72f410 0000000000000001 0000000000000005 GPR08: c0000000010b5768 c000000000f8a048 0000000000000001 0000000000000000 GPR12: 0000000048222482 c00000000fffe580 0000000022222222 0000000010129664 GPR16: 0000000010143cc0 0000000000000000 0000000044444444 0000000000000000 GPR20: c00000007c7221d8 c0000000f638e3c8 000003f15a20120d 0000000000000001 GPR24: 000000005a20120d c00000007c722000 c00000007cdedda8 00003fffef23b160 GPR28: 0000000000000001 c00000007c72f410 c000000000fdb820 0000000000000006 NIP [c0000000000ed6e4] .smp_call_function_single+0x18c/0x248 LR [c0000000000ed5b8] .smp_call_function_single+0x60/0x248 Call Trace: [c00000007c72f2d0] [c0000000000ed5b8] .smp_call_function_single+0x60/0x248 (unreliable) [c00000007c72f3a0] [c000000000030810] .__flush_tlb_page+0x164/0x1b0 [c00000007c72f460] [c00000000002e054] .ptep_set_access_flags+0xb8/0x168 [c00000007c72f500] [c0000000001ad3d8] .handle_mm_fault+0x4a8/0xbac [c00000007c72f5e0] [c000000000bb3238] .do_page_fault+0x3b8/0x868 [c00000007c72f810] [c00000000001e1d0] storage_fault_common+0x20/0x44 Exception: 301 at .__copy_tofrom_user_base+0x54/0x5b0 LR = .op_powerpc_backtrace+0x190/0x20c [c00000007c72fb00] [c000000000a2ec34] .op_powerpc_backtrace+0x204/0x20c (unreliable) [c00000007c72fbc0] [c000000000a2b5fc] .oprofile_add_ext_sample+0xe8/0x118 [c00000007c72fc70] [c000000000a2eee0] .fsl_emb_handle_interrupt+0x20c/0x27c [c00000007c72fd30] [c000000000a2e440] .op_handle_interrupt+0x44/0x58 [c00000007c72fdb0] [c000000000016d68] .performance_monitor_exception+0x74/0x90 [c00000007c72fe30] [c00000000001d8b4] exc_0x260_common+0xfc/0x100 performance_monitor_exception() is executed in a context with interrupt disabled and preemption enabled. When there is a user space page fault happened, do_page_fault() invoke in_atomic() to decide whether kernel should handle such page fault. in_atomic() only check preempt_count. So need call pagefault_disable() to disable preemption before reading user stack. Signed-off-by: Jiang Lu <lu.jiang@windriver.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/mm: Check for matching hpte without taking hpte lockAneesh Kumar K.V2014-12-021-9/+15
| | | | | | | | | | | | | | | | | | | | | | With smaller hash page table config, we would end up in situation where we would be replacing hash page table slot frequently. In such config, we will find the hpte to be not matching, and we can do that check without holding the hpte lock. We need to recheck the hpte again after holding lock. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc: Drop useless warning in eeh_init()Greg Kurz2014-12-021-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is what we get in dmesg when booting a pseries guest and the hypervisor doesn't provide EEH support. [ 0.166655] EEH functionality not supported [ 0.166778] eeh_init: Failed to call platform init function (-22) Since both powernv_eeh_init() and pseries_eeh_init() already complain when hitting an error, it is not needed to print more (especially such an uninformative message). Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/powernv: Cleanup unused MCE definitions/declarations.Mahesh Salgaonkar2014-12-025-136/+0
| | | | | | | | | | | | | | | | | | Cleanup OpalMCE_* definitions/declarations and other related code which is not used anymore. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Acked-by: Benjamin Herrrenschmidt <benh@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/eeh: Dump PHB diag-data earlyGavin Shan2014-12-023-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On PowerNV platform, PHB diag-data is dumped after stopping device drivers. In case of recursive EEH errors, the kernel is usually crashed before dumping PHB diag-data for the second EEH error. It's hard to locate the root cause of the second EEH error without PHB diag-data. The patch adds one more EEH option "eeh=early_log", which helps dumping PHB diag-data immediately once frozen PE is detected, in order to get the PHB diag-data for the second EEH error. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/eeh: Recover EEH error on ownership change for BCM5719Gavin Shan2014-12-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | In PCI passthrou scenario, we need simulate EEH recovery for Emulex adapters when their ownership changes, as we did in commit 5cfb20b96 ("powerpc/eeh: Emulate EEH recovery for VFIO devices"). Broadcom BCM5719 adpaters are facing same problem and needs same cure. Reported-by: Rajeshkumar Subramanian <rajeshkumars@in.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/eeh: Set EEH_PE_RESET on PE resetGavin Shan2014-12-024-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch introduces additional flag EEH_PE_RESET to indicate the corresponding PE is under reset. In turn, the PE retrieval bakcend on PowerNV platform can return unfrozen state for the EEH core to moving forward. Flag EEH_PE_CFG_BLOCKED isn't the correct one for the purpose. In PCI passthrou case, the problem is more worse: Guest doesn't recover 6th EEH error. The PE is left in isolated (frozen) and config blocked state on Broadcom adapters. We can't retrieve the PE's state correctly any more, even from the host side via sysfs /sys/bus/pci/devices/xxx/eeh_pe_state. Reported-by: Rajeshkumar Subramanian <rajeshkumars@in.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/eeh: Refactor eeh_reset_pe()Gavin Shan2014-12-021-11/+18
| | | | | | | | | | | | | | | | | | | | | | The patch refactors eeh_reset_pe() in order for: * Varied return values for different failure cases. * Replace pr_err() with pr_warn() and print function name. * Coding style cleanup. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Remove more traces of bootmemMichael Ellerman2014-11-1912-49/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although we are now selecting NO_BOOTMEM, we still have some traces of bootmem lying around. That is because even with NO_BOOTMEM there is still a shim that converts bootmem calls into memblock calls, but ultimately we want to remove all traces of bootmem. Most of the patch is conversions from alloc_bootmem() to memblock_virt_alloc(). In general a call such as: p = (struct foo *)alloc_bootmem(x); Becomes: p = memblock_virt_alloc(x, 0); We don't need the cast because memblock_virt_alloc() returns a void *. The alignment value of zero tells memblock to use the default alignment, which is SMP_CACHE_BYTES, the same value alloc_bootmem() uses. We remove a number of NULL checks on the result of memblock_virt_alloc(). That is because memblock_virt_alloc() will panic if it can't allocate, in exactly the same way as alloc_bootmem(), so the NULL checks are and always have been redundant. The memory returned by memblock_virt_alloc() is already zeroed, so we remove several memsets of the result of memblock_virt_alloc(). Finally we convert a few uses of __alloc_bootmem(x, y, MAX_DMA_ADDRESS) to just plain memblock_virt_alloc(). We don't use memblock_alloc_base() because MAX_DMA_ADDRESS is ~0ul on powerpc, so limiting the allocation to that is pointless, 16XB ought to be enough for anyone. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | powerpc/pseries: Initialise nvram_pstore_info's buf_lockLi Zhong2014-11-191-0/+2
|/ | | | | | | | | | | | | | | | | | nvram_pstore_info's buf_lock is not initialized before registering, which is clearly incorrect. It causes some strange behavior when trying to obtain the lock during kdump process. On a UP configuration, the console stopped for a couple of seconds, then "lockup suspected" warning printed out, but then it continued to run. So try lock fails, and lockup reported, but then arch_spin_lock() passes. Signed-off-by: Li Zhong <zhong@linux.vnet.ibm.com> [mpe: Edited changelog] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* Merge remote-tracking branch 'scottwood/next' into nextMichael Ellerman2014-11-1841-543/+1599
|\ | | | | | | | | | | | | | | Scott says: "Highlights include a bunch of 8xx optimizations, device tree bindings for Freescale BMan, QMan, and FMan datapath components, misc device tree updates, and inbound rio window support."
| * powerpc/config: Enable memory driverPrabhakar Kushwaha2014-11-184-0/+4
| | | | | | | | | | | | | | | | | | As Freescale IFC controller has been moved to driver to driver/memory. So enable memory driver in powerpc config Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl-rio: add support for mapping inbound windowsMartijn de Gouw2014-11-132-0/+117
| | | | | | | | | | | | | | | | | | | | | | Add support for mapping and unmapping of inbound rapidio windows. This allows for drivers to open up a part of local memory on the rapidio network. Also applications can use this and tranfer blocks of data over the network. Signed-off-by: Martijn de Gouw <martijn.de.gouw@prodrive-technologies.com> [scottwood@freescale.com: updated commit message based on review] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl: Update fman dt binding with clock name and qbman linkScott Wood2014-11-131-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | The clock name "fmanclk" was given in the example, but not specified in the binding itself. Made clock-names mandatory as otherwise there's not much point having it. Added a reference to the fsl,qman and fsl,bman properties proposed in http://patchwork.ozlabs.org/patch/407034/ and http://patchwork.ozlabs.org/patch/407035/ Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl: Frame Manager Device Tree binding documentIgal Liberman2014-11-131-0/+529
| | | | | | | | | | | | | | | | | | | | | | | | | | The Frame Manager (FMan) combines the Ethernet network interfaces with packet distribution logic to provide intelligent distribution and queuing decisions for incoming traffic at line rate. This binding document describes Freescale's Frame Manager hardware attributes that are used by the Frame Manager driver for its basic initialization and configuration. Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * dt/bindings: Introduce the FSL QorIQ DPAA QMan portal(s)Emil Medve2014-11-131-0/+154
| | | | | | | | | | | | | | | | | | | | Portals are memory mapped interfaces to QMan that allow low-latency, lock-less interaction by software running on processor cores, accelerators and network interfaces with the QMan Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I29764fa8093b5ce65460abc879446795c50d7185 Signed-off-by: Scott Wood <scottwood@freescale.com>
| * dt/bindings: Introduce the FSL QorIQ DPAA QManEmil Medve2014-11-131-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan supports queuing and QoS scheduling of frames to CPUs, network interfaces and DPAA logic modules, maintains packet ordering within flows. Besides providing flow-level queuing, is also responsible for congestion management functions such as RED/WRED, congestion notifications and tail discards. This binding covers the CCSR space programming model Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I3acb223893e42003d6c9dc061db568ec0b10d29b Signed-off-by: Scott Wood <scottwood@freescale.com>
| * dt/bindings: Introduce the FSL QorIQ DPAA BMan portal(s)Emil Medve2014-11-131-0/+56
| | | | | | | | | | | | | | | | | | | | Portals are memory mapped interfaces to BMan that allow low-latency, lock-less interaction by software running on processor cores, accelerators and network interfaces with the BMan Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I6d245ffc14ba3d0e91d403ac7c3b91b75a9e6a95 Signed-off-by: Scott Wood <scottwood@freescale.com>
| * dt/bindings: Introduce the FSL QorIQ DPAA BManEmil Medve2014-11-131-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA). BMan supports hardware allocation and deallocation of buffers belonging to pools originally created by software with configurable depletion thresholds. This binding covers the CCSR space programming model Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I3ec479bfb3c91951e96902f091f5d7d2adbef3b2 Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/dts: Add node(s) for the platform PLLEmil Medve2014-11-082-0/+14
| | | | | | | | | | | | Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: If76cd705a01813abe53396c1486bc13c4289ee92 Signed-off-by: Scott Wood <scottwood@freescale.com>
| * dt/bindings: qoriq-clock: Add binding for the platform PLLEmil Medve2014-11-081-2/+12
| | | | | | | | | | | | Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I7950afa9650d15ec7ce2cca89bb2a1e38586d4a5 Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/dts: Factorize the clock control nodeEmil Medve2014-11-0814-368/+163
| | | | | | | | | | | | Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I25ce24a25862b4ca460164159867abefe00ccdd1 Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc: Add INA220 to device tree for supported boardsHongtao Jia2014-11-084-0/+72
| | | | | | | | | | | | | | Including: P3041DS P5020DS P5040DS B4QDS Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc: Add ADT7461 to device tree for supported boardsHongtao Jia2014-11-083-0/+29
| | | | | | | | | | | | | | Including: T104xRDB T208xQDS B4QDS Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl: Added rcw registers to global utility registersIgal Liberman2014-11-081-1/+4
| | | | | | | | | | | | | | | | The RCW registers are required for the future clock binding implementation. Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> Change-Id: Ic36dd8bc2959aa7f97fb6fd7bbb8420822fef0a9 Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/mpc85xx: Remove SPI and NAND partition from bsc9131rdb.dtsiAshish Kumar2014-11-081-50/+0
| | | | | | | | | | | | | | | | | | | | | | * Run "mtdparts default" on u-boot to create dynamic partitions * Or use dynamic mtd partition with the help of bootargs in u-boot Append bootargs with: "mtdparts=ff800000.flash:1m(nand_uboot),512K(nand_dtb),8m(nand_kernel),-(fs);\ spiff707000.0:1m(spi_uboot),4m(spi_kernel),512k(spi_dtb),-(fs)'" Signed-off-by: Ashish Kumar <Ashish.Kumar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Remove Kconfig symbol FADSPaul Bolle2014-11-081-4/+0
| | | | | | | | | | | | | | | | | | Commit 39eb56da2b53 ("pcmcia: Remove m8xx_pcmcia driver") removed the only driver that used CONFIG_FADS. Setting the Kconfig symbol FADS is pointless since that commit. Remove it. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Invalidate non present TLB as early as possibleLEROY Christophe2014-11-082-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 8xx sometimes need to load a invalid/non-present TLBs in it DTLB asm handler. These must be invalidated separaly as linux mm doesn't. Commit 5efab4a02c89c252fb4cce097aafde5f8208dbfe was invalidating them in arch/powerpc/mm/fault.c. This patch does the invalidation earlier in order to free the TLB as soon as possible. This also has the advantage of removing some 8xx specific code from fault.c Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Use DAR to save r3 for CPU6 ERRATALEROY Christophe2014-11-081-18/+15
| | | | | | | | | | | | | | | | | | As we are not using anymore DAR to save registers, it is now available for saving the r3 register used for CPU6 ERRATA handling. Therefore we can remove the major hack which was to use memory location 0 to save r3. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Don't restore regs to save them again.LEROY Christophe2014-11-081-3/+5
| | | | | | | | | | | | | | | | | | There is not need to restore r10, r11 and cr registers at this end of ITLBmiss handler as they are saved again to the same place in ITLBError handler we are jumping to. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: _PMD_PRESENT already set in level 1 entriesLEROY Christophe2014-11-081-2/+0
| | | | | | | | | | | | | | | | When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit during TLB loading is useless. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: set PTE bit 22 off TLBmissLEROY Christophe2014-11-083-10/+27
| | | | | | | | | | | | | | No need to re-set this bit at each TLB miss. Let's set it in the PTE. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Better readibility of ERRATA CPU6 handlingLEROY Christophe2014-11-081-13/+16
| | | | | | | | | | | | | | | | This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro. Then we don't have to worry about this address directly in the code. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Implement 16k pagesLEROY Christophe2014-11-083-1/+7
| | | | | | | | | | | | | | This patch activates the handling of 16k pages on the MPC8xx. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Const for TLB RPN forced valueLEROY Christophe2014-11-081-6/+13
| | | | | | | | | | | | | | | | | | Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked to the page size and will vary when we change the page size. Lets define a const for it in order to have it at only one place. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Use PAGE size related constsLEROY Christophe2014-11-081-12/+18
| | | | | | | | | | | | | | | | For PAGE size related operations, use PAGE size consts in order to be able to use different page size in the futur. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Don't use MD_TWC for walkLEROY Christophe2014-11-081-16/+12
| | | | | | | | | | | | | | | | MD_TWC can only be used properly with 4k pages. So lets calculate level 2 table index by ourselves. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Use M_TW instead of M_TWBLEROY Christophe2014-11-081-22/+26
| | | | | | | | | | | | | | | | | | Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires 4k aligned tables, which is only the case with 4k pages. Consequently, we have to calculate the level 1 table index by ourselves. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: No need to restore registers and save them again.LEROY Christophe2014-11-081-2/+2
| | | | | | | | | | | | | | | | In DTLBError handler there is not need to restore r10, r11 and cr registers after fixing DAR as they are saved again to the same place just after. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: DataAccess exception not generated by MPC8xxLEROY Christophe2014-11-081-11/+10
| | | | | | | | | | | | | | | | DataAccess exception is never generated by MPC8xx so do the job directly where it is used to avoid an unnecessary branching. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: exception InstructionAccess does not exist on MPC8xxLEROY Christophe2014-11-081-8/+7
| | | | | | | | | | | | | | | | Exception InstructionAccess does not exist on MPC8xx. No need to branch there from somewhere else. Handling can be done directly in InstructionTLBError Exception. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-09 11:03:40 +0100