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* drm/i915: Do fbdev fini first during unloadVille Syrjälä2015-11-111-2/+2
* drm/i915: Kill intel_runtime_pm_disable()Ville Syrjälä2015-11-111-17/+0
* drm/i915: Setup DDI clk for MST on SKLVille Syrjälä2015-11-103-27/+32
* drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on()Ville Syrjälä2015-11-101-26/+19
* drm/i915: Use intel_dp->DP in eDP PLL setupVille Syrjälä2015-11-101-27/+14
* drm/i915: Clean up eDP PLL state assertsVille Syrjälä2015-11-101-15/+39
* drm/i915: Remove ILK-A eDP PLL workaround notesVille Syrjälä2015-11-101-4/+0
* drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/Ville Syrjälä2015-11-102-6/+6
* drm/i915: Hide underruns from eDP PLL and port enable on ILKVille Syrjälä2015-11-101-3/+31
* drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaroundVille Syrjälä2015-11-104-0/+42
* drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder()Ville Syrjälä2015-11-101-1/+1
* drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPTVille Syrjälä2015-11-103-31/+103
* drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabledVille Syrjälä2015-11-101-0/+13
* drm/i915: Enable PCH FIFO underruns later on HSW+Ville Syrjälä2015-11-101-7/+9
* drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVBVille Syrjälä2015-11-101-4/+8
* drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTLVille Syrjälä2015-11-101-2/+4
* drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config...Ville Syrjälä2015-11-101-5/+2
* drm/i915: remove in_dbg_master check from intel_fbc.cPaulo Zanoni2015-11-101-6/+0
* drm/i915: clarify that checking the FB stride for CFB is intentionalPaulo Zanoni2015-11-101-0/+1
* drm/i915: remove too-frequent FBC debug messagePaulo Zanoni2015-11-101-2/+0
* drm/i915: refactor FBC deactivation at initPaulo Zanoni2015-11-102-5/+6
* drm/i915: don't disable_fbc() if FBC is already disabledPaulo Zanoni2015-11-101-1/+2
* drm/i915: fix the __intel_fbc_update() commentsPaulo Zanoni2015-11-101-24/+2
* drm/i915: use struct intel_crtc *crtc at __intel_fbc_update()Paulo Zanoni2015-11-101-15/+15
* drm/i915: extract crtc_is_valid() on the FBC codePaulo Zanoni2015-11-101-5/+17
* drm/i915: remove unnecessary check for crtc->primary->fbPaulo Zanoni2015-11-101-1/+1
* drm/i915: extract fbc_on_pipe_a_only()Paulo Zanoni2015-11-101-6/+7
* drm/i915: rename intel_fbc_nuke to intel_fbc_recompressPaulo Zanoni2015-11-101-3/+4
* drm/i915: remove newline from a no_fbc_reason messagePaulo Zanoni2015-11-101-1/+1
* drm/i915/bxt: Force port A DDI to use 4 lanesMatt Roper2015-11-091-0/+14
* drm/i915: Print a debug message when exceeding dotclock limit on pre-gen4Ville Syrjälä2015-11-091-8/+18
* drm/i915: Avoid pointer arithmetic in calculating plane surface offsetMika Kuoppala2015-11-093-11/+13
* drm/i915: Add dmc firmware load state and version to error stateMika Kuoppala2015-11-091-0/+11
* drm/i915: Add csr programming registers to dmc debugfs entryMika Kuoppala2015-11-093-16/+18
* drm/i915/bxt: Expose DC5 entry countMika Kuoppala2015-11-092-0/+4
* drm/i915/skl: Expose DC5/DC6 entry countsDamien Lespiau2015-11-092-0/+15
* drm/i915/skl: Print the DMC firmware status in debugfsDamien Lespiau2015-11-091-0/+27
* drm/i915/skl: Refuse to load outdated dmc firmwareMika Kuoppala2015-11-091-10/+24
* drm/i915/skl: Store and print the DMC firmware version we loadDamien Lespiau2015-11-092-1/+13
* drm/i915: Fix failure paths around initial fbdev allocationTvrtko Ursulin2015-11-091-8/+12
* drm/i915: Fix double unref in intelfb_alloc failure pathLukas Wunner2015-11-091-3/+2
* drm/i915: On fb alloc failure, unref gem object where it gets refedLukas Wunner2015-11-091-7/+14
* drm/i915: Make intel_dp_source_supports_hbr2() take an intel_dp pointerAnder Conselvan de Oliveira2015-11-053-12/+13
* drm/i915: Create intel_dp->prepare_link_retrain() hookAnder Conselvan de Oliveira2015-11-054-9/+14
* drm/i915: Move generic link training code to a separate fileAnder Conselvan de Oliveira2015-11-054-312/+353
* drm/i915: Move register write into intel_dp_set_signal_levels()Ander Conselvan de Oliveira2015-11-051-7/+4
* drm/i915 Call get_adjust_train() from clock recovery and channel eqAnder Conselvan de Oliveira2015-11-051-5/+5
* drm/i915: Split write of pattern to DP reg from intel_dp_set_link_trainAnder Conselvan de Oliveira2015-11-051-5/+13
* drm/i915: Don't pass *DP around to link training functionsAnder Conselvan de Oliveira2015-11-051-27/+20
* drm/i915/kbl: Kabylake uses the same GMS values as SkylakeDeepak S2015-11-051-0/+1
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