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* MIPS: JZ4740: Don't select HAVE_PWMJingoo Han2014-03-261-1/+0
| | | | | | | | | | | | | | The HAVE_PWM symbol is only for legacy platforms that provide the PWM API without using the generic framework. The jz4740 platform uses the generic PWM framework, after the commit "f6b8a57 pwm: Add Ingenic JZ4740 support". Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6525/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Restore init.h usage to arch/mips/ar7/time.cPaul Gortmaker2014-03-261-0/+1
| | | | | | | | | | | | | | | Commit 0046be10e0c502705fc74d91408eba13a73bc201 ("mips: delete non-required instances of include <linux/init.h>") inadvertently removed an include that was actually correct. Restore it. Note that it gets init.h implicitly anyway, so this is largely a cosmetic fixup; no build regressions were caused by this. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6416/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47XX: Add Belkin F7Dxxxx board detectionCody P Schafer2014-03-264-0/+16
| | | | | | | | | | | | | | | Add a few Belkin F7Dxxxx entries, with F7D4401 sourced from online documentation and the "F7D7302" being observed. F7D3301, F7D3302, and F7D4302 are reasonable guesses which are unlikely to cause mis-detection. Signed-off-by: Cody P Schafer <devel@codyps.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: zajec5@gmail.com Cc: Cody P Schafer <devel@codyps.com> Patchwork: https://patchwork.linux-mips.org/patch/6594/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47XX: Add detection and GPIO config for Siemens SE505v2Hauke Mehrtens2014-03-263-0/+31
| | | | | | | | | | | | This adds board detection for the Siemens SE505v2 and the led gpio configuration. This board does not have any buttons. This is based on OpenWrt broadcom-diag and Manuel Munz's nvram dump. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: zajec5@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6593/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47XX: Add button and led configuration for some Linksys devicesHauke Mehrtens2014-03-262-0/+60
| | | | | | | | | | | This adds led and button GPIO configuration for Linksys wrt54g3gv2, wrt54gsv1 and wrtsl54gs. This is based on OpenWrt broadcom-diag code. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: zajec5@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6592/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47XX: Detect some more Linksys devicesHauke Mehrtens2014-03-262-2/+4
| | | | | | | | | | | | | | The Linksys WRT54G/GS/GL family uses the same boardtype numbers, and the same gpio configuration. The boardtype numbers are changing with the hardware versions, but these hardware numbers are different or each model. Detect them all as one device, this also worked in OpenWrt. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: zajec5@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6591/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cpu-probe: Add support for probing M5150 coresLeonid Yegoshin2014-03-261-0/+4
| | | | | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6597/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add support for the M5150 processorLeonid Yegoshin2014-03-267-1/+10
| | | | | | | | | | | | | | The M5150 core is a 32-bit MIPS RISC which implements the MIPS Architecture Release-5 in a 5-stage pipeline. In addition, it includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6596/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add processor identifier for the M5150 processorLeonid Yegoshin2014-03-261-0/+1
| | | | | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6595/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add defconfig for Malta SMVP with EVAMarkos Chandras2014-03-261-0/+200
| | | | | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6581/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Default NR_CPUS=8 for malta SMP defconfigsPaul Burton2014-03-263-3/+3
| | | | | | | | | | | | | | | | | | The previous NR_CPUS=2 default is not an optimal default for current Malta setups where it is common to have more than 2 CPUs available. It makes sense to increase this to a number which covers all common setups currently in use, such that all of those cores are usable. 8 seems to fit that description. If the user has less than 8 CPUs & they wish to have a more optimal kernel they can simply reduce this in their config. It makes sense for the default to work on as many systems as possible. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6580/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Set page size to 16KB for malta SMP defconfigsPaul Burton2014-03-263-0/+3
| | | | | | | | | | | | | For Malta defconfigs which may run on an SMP configuration without hardware cache anti-aliasing, a 16KB page size is a safer default. Most notably at the moment it will avoid cache aliasing issues for multicore proAptiv systems. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6579/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Enable DEVTMPFSMarkos Chandras2014-03-267-0/+7
| | | | | | | | | | | | Recent versions of udev and systemd require the kernel to be compiled with CONFIG_DEVTMPFS in order to populate the /dev directory. Most MIPS platforms have it enabled by default, so enable it for Malta configs as well. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6582/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Regenerate malta defconfigsPaul Burton2014-03-267-26/+3
| | | | | | | | | | | | | | | | | | This patch simply regenerates the malta defconfigs such that they don't change after being used & saved as a defconfig again. ie. it is the result of running the following: for cfg in arch/mips/configs/malta*; do ARCH=mips make `basename ${cfg}` ARCH=mips make savedefconfig mv -v defconfig ${cfg} done Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6578/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: pata_platform for DB1200Manuel Lauss2014-03-262-10/+14
| | | | | | | | | | | | | The au1xxx-ide driver isn't any faster than pata_platform since it spends a lot of time busy waiting for DMA to finish; faster PIO/DMA modes only work on the db1200 with a certain cpu speed, UDMA is broken, and finally the old IDE layer is on death row, so time to switch to the newer ATA layer. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6662/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: fold mach-db1xxx/db1x00 headers into board codeManuel Lauss2014-03-264-133/+80
| | | | | | | | | Merge the db1200.h and db1300.h headers into their only users. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6660/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Unify Devboard support.Manuel Lauss2014-03-2612-863/+339
| | | | | | | | | | | | | | This patch merges support for all DB1xxx and PB1xxx boards into a single image, along with a new single defconfig for them. Run-tested on DB1300 and DB1500. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6577/ Patchwork: https://patchwork.linux-mips.org/patch/6659/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Determine cohereny at runtime based on cpu typeManuel Lauss2014-03-264-8/+13
| | | | | | | | | | | | All Alchemy chips have coherent DMA, but for example the USB or AC97 peripherals on the Au1000/1500/1100 are not. This patch uses DMA_MAYBE_COHERENT on Alchemy and sets coherentio based on CPU type. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6576/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Extend DMA_MAYBE_COHERENT logic to DMA_NONCOHERENT useManuel Lauss2014-03-263-7/+7
| | | | | | | | | | Setting DMA_MAYBE_COHERENT gives a platform the opportunity to select use of cache ops at boot. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6575/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable MIPS 3.5 features on MaltaMarkos Chandras2014-03-261-0/+1
| | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: Add support for SMP EVAMarkos Chandras2014-03-262-1/+7
| | | | | | | | Allow secondary cores to program their segment control registers during smp bootstrap code. This enables EVA on Malta SMP configurations Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: malta-init: Fix System Controller memory mapping for EVALeonid Yegoshin2014-03-261-0/+13
| | | | | | | Shift System Controller memory mapping to 0x80000000 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: malta-memory: Add free_init_pages_eva() callbackMarkos Chandras2014-03-261-0/+8
| | | | | | | | | Use a Malta specific function to free the init section once the kernel has booted. When operating in EVA mode, the physical memory is shifted to 0x80000000. Kernel is loaded into 0x80000000 (virtual) so the offset between physical and virtual addresses is 0. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: malta-memory: Use the PHYS_OFFSET to build the memory mapMarkos Chandras2014-03-261-7/+7
| | | | | | | | | PHYS_OFFSET is used to denote the physical start address of the first bank of RAM. When the Malta board is in EVA mode, the physical start address of RAM is shifted to 0x80000000 so it's necessary to use this macro in order to make the code EVA agnostic. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: malta-memory: Add support for the 'ememsize' variableMarkos Chandras2014-03-262-10/+28
| | | | | | | | | | | The 'ememsize' variable is used to denote the real RAM which is present on the Malta board. This is different compared to 'memsize' which is capped to 256MB. The 'ememsize' is used to get the actual physical memory when setting up the Malta memory layout. This only makes sense in case the core operates in the EVA mode, and it's ignored otherwise. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: spaces.h: Add spaces.h file for Malta (EVA)Markos Chandras2014-03-261-0/+46
| | | | | | | Add a spaces.h file for Malta to override certain memory macros when operating in EVA mode. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: Configure Segment Control registers for EVA bootMarkos Chandras2014-03-262-1/+112
| | | | | | | | | | | | | | | | | | | | | | The Malta board aliases 0x80000000 - 0xffffffff to 0x00000000 - 0x7fffffff ignoring the 256 MB IO hole in 0x10000000. The physical memory is shifted to 0x80000000 so up to 2GB can be used. Kuseg is expanded to 3GB (due to board limitations only 2GB can be accessed) and lowmem (kernel space) is expanded to 2GB. The Segment Control registers are programmed as follows: Virtual memory Physical memory Mapping 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg) 0x80000000 - 0x9fffffff 0x00000000 - 0x1ffffffff MUSUK (kseg0) 0xa0000000 - 0xbf000000 0x00000000 - 0x1ffffffff MUSUK (kseg1) 0xc0000000 - 0xdfffffff - MK (kseg2) 0xe0000000 - 0xffffffff - MK (kseg3) The location of exception vectors remain the same since 0xbfc00000 (traditional exception base) still maps to 0x1fc00000 physical. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: c-r4k: Flush scache to avoid cache aliasesLeonid Yegoshin2014-03-261-0/+11
| | | | | | | | | | | | There is a chance for the secondary cache to have memory aliases. This can happen if the bootloader is in a non-EVA mode (or even in EVA mode but with different mapping from the kernel) and the kernel switching to EVA afterwards. It's best to flush the icache to avoid having the secondary CPUs fetching stale data from it. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: c-r4k: Add support for flushing user pages from cacheMarkos Chandras2014-03-261-2/+4
| | | | | | | Use the userspace cache flushing functions if the interrupted process is a userspace one. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functionsLeonid Yegoshin2014-03-261-0/+47
| | | | | | | | Build EVA specific cache flushing functions (ie cachee). They will be used by a subsequent patch. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: init: Add free_init_pages() callback for EVAMarkos Chandras2014-03-262-1/+13
| | | | | | | | A core in EVA mode can have any possible segment mapping, so the default free_initmem_default() function may not always work as expected. Therefore, add a callback that platforms can use to free up the init section. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: kernel: proc: Add EVA to the list of CPU featuresMarkos Chandras2014-03-261-0/+1
| | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: kernel: cpu-probe: Enable EVA option on supported coresMarkos Chandras2014-03-261-0/+3
| | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: cpu: Add cpu flag for Enhanced Virtual AddressingMarkos Chandras2014-03-262-1/+4
| | | | | | | The MIPS *Aptiv family uses bit 28 in Config5 CP0 register to indicate whether the core supports EVA or not. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: page: Allow __pa_symbol overridesLeonid Yegoshin2014-03-261-0/+2
| | | | | | | | This will allow platforms to use an alternative way to get the physical address of a symbol. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: kernel: {ftrace,kgdb}: Set correct address limit for cache flushesLeonid Yegoshin2014-03-262-1/+21
| | | | | | | | | | When flushing the icache, make sure the address limit is correct so the appropriate 'cache' instruction will be used. This has no impact on cores operating in non-eva mode. However, when EVA is enabled, we ensure that 'cache' will be used instead of 'cachee'. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: r4kcache: Add EVA cache flushing functionsLeonid Yegoshin2014-03-261-1/+151
| | | | | | | | | | Add EVA cache flushing functions similar to non-EVA configurations. Because the cache may or may not contain user virtual addresses, we need to use the 'cache' or 'cachee' instruction based on whether we flush the cache on behalf of kernel or user respectively. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: r4kcache: Add protected cache operation for EVALeonid Yegoshin2014-03-261-0/+18
| | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: r4kcache: Build flushing code for instruction cacheLeonid Yegoshin2014-03-261-0/+1
| | | | | | | | Build code to invalidate an address range in the instruction cache using the Hit Invalidate cache operation. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: kernel: signal: Prevent save/restore FPU context in user memoryLeonid Yegoshin2014-03-261-0/+32
| | | | | | | | EVA does not have FPU specific instructions for reading or writing FPU registers from userspace memory. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: checksum: Add MIPS specific csum_and_copy_from_user functionLeonid Yegoshin2014-03-261-0/+14
| | | | | | | | | | A MIPS specific csum_and_copy_from_user function is necessary because the generic one from include/net/checksum.h will not work for EVA. This is because the generic one will link to symbols from lib/checksum.c which are not EVA aware. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: checksum: Split kernel and user copy operationsLeonid Yegoshin2014-03-261-6/+16
| | | | | | | | | | In EVA mode, different instructions need to be used to read/write from kernel and userland. In non-EVA mode, there is no functional difference. The current address limit is checked to decide the type of operation that will be performed. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: lib: csum_partial: Add EVA supportMarkos Chandras2014-03-261-0/+25
| | | | | | | Use EVA specific functions to read and write data to user address space. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: lib: csum_partial: Add macro to build csum_partial symbolsMarkos Chandras2014-03-261-92/+108
| | | | | | | | | | In preparation for EVA support, we use a macro to build the __csum_partial_copy_user main code so it can be shared across multiple implementations. EVA uses the same code but it replaces the load/store/prefetch instructions with the EVA specific ones therefore using a macro avoids unnecessary code duplications. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: lib: csum_partial: Merge EXC and load/store macrosMarkos Chandras2014-03-261-69/+91
| | | | | | | | | | | | | Each load/store macro always adds an entry to the __ex_table using the EXC macro. There are cases where a load instruction may never fail such as when we are sure the load happens in the kernel address space. Therefore, we merge these the EXC and LOADX/STOREX macros into a single one. We also expand the argument list in the EXC macro to make the macro more flexible. The extra 'type' argument is not used by this commit, but it will be used when EVA support is added to memcpy. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: checksum: Split the 'copy_user' symbolMarkos Chandras2014-03-263-10/+21
| | | | | | | | | | | | The 'copy_user' symbol can be used to copy from or to userland so we will use two different symbols for these operations. This makes no difference in the existing code, but when the core is operating in EVA mode, different instructions need to be used to read and write to userland address space. The old function has also been renamed to 'copy_kernel' to denote that it is suitable for copy data to and from kernel space. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: kernel: unaligned: Handle unaligned accesses for EVALeonid Yegoshin2014-03-261-1/+85
| | | | | | | | Handle unaligned accesses when we access userspace memory EVA mode. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: kernel: unaligned: Add EVA instruction wrappersMarkos Chandras2014-03-261-24/+25
| | | | | | | Use the load/store instruction wrappers from asm/asm.h to perform such operations when operating in EVA mode. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: uaccess: Add EVA support for str*_user operationsMarkos Chandras2014-03-261-53/+119
| | | | | | | | | | | The str*_user functions are used to securely access NULL terminated strings from userland. Therefore, it's necessary to use the appropriate EVA function. However, if the string is in kernel space, then the normal instructions are being used to access it. The __str*_kernel_asm and __str*_user_asm symbols are the same for non-EVA mode so there is no functional change for the non-EVA kernels. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: uaccess: Add EVA support to copy_{in, to,from}_userMarkos Chandras2014-03-261-20/+171
| | | | | | | | | | | Use the EVA specific functions from memcpy.S to perform userspace operations. When get_fs() == get_ds() the usual load/store instructions are used because the destination address is located in the kernel address space region. Otherwise, the EVA specifc load/store instructions are used which will go through th TLB to perform the virtual to physical translation for the userspace address. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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