summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* kvm: vmx: Reinstate support for CPUs without virtual NMIPaolo Bonzini2017-11-171-44/+106
| | | | | | | | | | | | | | | | | | | | | | | | | This is more or less a revert of commit 2c82878b0cb3 ("KVM: VMX: require virtual NMI support", 2017-03-27); it turns out that Core 2 Duo machines only had virtual NMIs in some SKUs. The revert is not trivial because in the meanwhile there have been several fixes to nested NMI injection. Therefore, the entire vNMI state is moved to struct loaded_vmcs. Another change compared to before the patch is a simplification here: if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked && !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis( get_vmcs12(vcpu))))) { The final condition here is always true (because nested_cpu_has_virtual_nmis is always false) and is removed. Fixes: 2c82878b0cb38fd516fd612c67852a6bbf282003 Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1490803 Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
* KVM: SVM: obey guest PATPaolo Bonzini2017-11-171-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | For many years some users of assigned devices have reported worse performance on AMD processors with NPT than on AMD without NPT, Intel or bare metal. The reason turned out to be that SVM is discarding the guest PAT setting and uses the default (PA0=PA4=WB, PA1=PA5=WT, PA2=PA6=UC-, PA3=UC). The guest might be using a different setting, and especially might want write combining but isn't getting it (instead getting slow UC or UC- accesses). Thanks a lot to geoff@hostfission.com for noticing the relation to the g_pat setting. The patch has been tested also by a bunch of people on VFIO users forums. Fixes: 709ddebf81cb40e3c36c6109a7892e8b93a09464 Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=196409 Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Tested-by: Nick Sarnie <commendsarnex@gmail.com> Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
* Merge tag 'kvm-arm-gicv4-for-v4.15' of ↵Paolo Bonzini2017-11-1717-114/+695
|\ | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD GICv4 Support for KVM/ARM for v4.15
| * KVM: arm/arm64: Don't queue VLPIs on INV/INVALLChristoffer Dall2017-11-101-3/+6
| | | | | | | | | | | | | | | | Since VLPIs are injected directly by the hardware there's no need to mark these as pending in software and queue them on the AP list. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: Fix GICv4 ITS initialization issuesChristoffer Dall2017-11-103-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should only try to initialize GICv4 data structures on a GICv4 capable system. Move the vgic_supports_direct_msis() check inito vgic_v4_init() so that any KVM VGIC initialization path does not fail on non-GICv4 systems. Also be slightly more strict in the checking of the return value in vgic_its_create, and only error out on negative return values from the vgic_v4_init() function. This is important because the kvm device code only treats negative values as errors and only cleans up in this case. Errornously treating a positive return value as an error from the vgic_v4_init() function can lead to NULL pointer dereferences, as has recently been observed. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Theory of operationsMarc Zyngier2017-11-101-0/+67
| | | | | | | | | | | | | | | | Yet another braindump so I can free some cells... Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Enable VLPI supportMarc Zyngier2017-11-102-0/+18
| | | | | | | | | | | | | | | | | | | | All it takes is the has_v4 flag to be set in gic_kvm_info as well as "kvm-arm.vgic_v4_enable=1" being passed on the command line for GICv4 to be enabled in KVM. Acked-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Prevent userspace from changing doorbell affinityMarc Zyngier2017-11-101-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We so far allocate the doorbell interrupts without taking any special measure regarding the affinity of these interrupts. We simply move them around as required when the vcpu gets scheduled on a different CPU. But that's counting without userspace (and the evil irqbalance) that can try and move the VPE interrupt around, causing the ITS code to emit VMOVP commands and remap the doorbell to another redistributor. Worse, this can happen while the vcpu is running, causing all kind of trouble if the VPE is already resident, and we end-up in UNPRED territory. So let's take a definitive action and prevent userspace from messing with us. This is just a matter of adding IRQ_NO_BALANCING to the set of flags we already have, letting the kernel in sole control of the affinity. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Prevent a VM using GICv4 from being savedMarc Zyngier2017-11-102-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv4 architecture doesn't make it easy for save/restore to work, as it doesn't give any guarantee that the pending state is written into the pending table. So let's not take any chance, and let's return an error if we encounter any LPI that has the HW bit set. In order for userspace to distinguish this error from other failure modes, use -EACCES as an error code. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Enable virtual cpuif if VLPIs can be deliveredMarc Zyngier2017-11-101-3/+6
| | | | | | | | | | | | | | | | | | | | | | In order for VLPIs to be delivered to the guest, we must make sure that the virtual cpuif is always enabled, irrespective of the presence of virtual interrupt in the LRs. Acked-by: Christoffer Dall <cdall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Hook vPE scheduling into vgic flush/syncMarc Zyngier2017-11-103-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | The redistributor needs to be told which vPE is about to be run, and tells us whether there is any pending VLPI on exit. Let's add the scheduling calls to the vgic flush/sync functions, allowing the VLPIs to be delivered to the guest. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Use the doorbell interrupt as an unblocking sourceMarc Zyngier2017-11-103-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The doorbell interrupt is only useful if the vcpu is blocked on WFI. In all other cases, recieving a doorbell interrupt is just a waste of cycles. So let's only enable the doorbell if a vcpu is getting blocked, and disable it when it is unblocked. This is very similar to what we're doing for the background timer. Reviewed-by: Christoffer Dall <cdall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Add doorbell interrupt handlingMarc Zyngier2017-11-101-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a vPE is not running, a VLPI being made pending results in a doorbell interrupt being delivered. Let's handle this interrupt and update the pending_last flag that indicates that VLPIs are pending. The corresponding vcpu is also kicked into action. Special care is taken to prevent the doorbell from being enabled at request time (this is controlled separately), and to make the disabling on the interrupt non-lazy. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Use pending_last as a scheduling hintMarc Zyngier2017-11-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When a vPE exits, the pending_last flag is set when there are pending VLPIs stored in the pending table. Similarily, this flag will be set when a doorbell interrupt fires, as it indicates the same condition. Let's update kvm_vgic_vcpu_pending_irq() to account for that flag as well, making a vcpu runnable when set. Acked-by: Christoffer Dall <cdall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Handle INVALL applied to a vPEMarc Zyngier2017-11-101-6/+9
| | | | | | | | | | | | | | | | | | | | | | There is no need to perform an INV for each interrupt when updating multiple interrupts. Instead, we can rely on the final VINVALL that gets sent to the ITS to do the work for all of them. Acked-by: Christoffer Dall <cdall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Propagate property updates to VLPIsMarc Zyngier2017-11-101-0/+3
| | | | | | | | | | | | | | | | | | Upon updating a property, we propagate it all the way to the physical ITS, and ask for an INV command to be executed there. Acked-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Handle MOVALL applied to a vPEMarc Zyngier2017-11-101-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of MOVALL doesn't allow us to call into the core ITS code as we hold a number of spinlocks. Let's try a method used in other parts of the code, were we copy the intids of the candicate interrupts, and then do whatever we need to do with them outside of the critical section. This allows us to move the interrupts one by one, at the expense of a bit of CPU time. Who cares? MOVALL is such a stupid command anyway... Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Handle CLEAR applied to a VLPIMarc Zyngier2017-11-101-0/+4
| | | | | | | | | | | | | | | | | | | | Handling CLEAR is pretty easy. Just ask the ITS driver to clear the corresponding pending bit (which will turn into a CLEAR command on the physical side). Acked-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Propagate affinity changes to the physical ITSMarc Zyngier2017-11-101-1/+15
| | | | | | | | | | | | | | | | | | | | When the guest issues an affinity change, we need to tell the physical ITS that we're now targetting a new vcpu. This is done by extracting the current mapping, updating the target, and reapplying the mapping. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Unmap VLPI when freeing an LPIMarc Zyngier2017-11-101-1/+5
| | | | | | | | | | | | | | | | | | When freeing an LPI (on a DISCARD command, for example), we need to unmap the VLPI down to the physical ITS level. Acked-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Handle INT command applied to a VLPIMarc Zyngier2017-11-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | If the guest issues an INT command targetting a VLPI, let's call into the irq_set_irqchip_state() helper to make it pending on the physical side. This works just as well if userspace decides to inject an interrupt using the normal userspace API... Acked-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Wire mapping/unmapping of VLPIs in VFIO irq bypassMarc Zyngier2017-11-103-2/+116
| | | | | | | | | | | | | | | | | | | | Let's use the irq bypass mechanism also used for x86 posted interrupts to intercept the virtual PCIe endpoint configuration and establish our LPI->VLPI mapping. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Add init/teardown of the per-VM vPE irq domainMarc Zyngier2017-11-107-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to control the GICv4 view of virtual CPUs, we rely on an irqdomain allocated for that purpose. Let's add a couple of helpers to that effect. At the same time, the vgic data structures gain new fields to track all this... erm... wonderful stuff. The way we hook into the vgic init is slightly convoluted. We need the vgic to be initialized (in order to guarantee that the number of vcpus is now fixed), and we must have a vITS (otherwise this is all very pointless). So we end-up calling the init from both vgic_init and vgic_its_create. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: GICv4: Add property field and per-VM predicateMarc Zyngier2017-11-103-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Add a new has_gicv4 field in the global VGIC state that indicates whether the HW is GICv4 capable, as a per-VM predicate indicating if there is a possibility for a VM to support direct injection (the above being true and the VM having an ITS). Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: vITS: Add a helper to update the affinity of an LPIMarc Zyngier2017-11-101-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | In order to help integrating the vITS code with GICv4, let's add a new helper that deals with updating the affinity of an LPI, which will later be augmented with super duper extra GICv4 goodness. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: vITS: Add MSI translation helpersMarc Zyngier2017-11-102-41/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The whole MSI injection process is fairly monolithic. An MSI write gets turned into an injected LPI in one swift go. But this is actually a more fine-grained process: - First, a virtual ITS gets selected using the doorbell address - Then the DevID/EventID pair gets translated into an LPI - Finally the LPI is injected Since the GICv4 code needs the first two steps in order to match an IRQ routing entry to an LPI, let's expose them as helpers, and refactor the existing code to use them Reviewed-by: Christoffer Dall <cdall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: vgic: Move kvm_vgic_destroy call aroundMarc Zyngier2017-11-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The way we call kvm_vgic_destroy is a bit bizarre. We call it *after* having freed the vcpus, which sort of defeats the point of cleaning up things before that point. Let's move kvm_vgic_destroy towards the beginning of kvm_arch_destroy_vm, which seems more sensible. Acked-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm: Select ARM_GIC_V3 and ARM_GIC_V3_ITSMarc Zyngier2017-11-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv4 support introduces a hard dependency between the KVM core and the ITS infrastructure. arm64 already selects it at the architecture level, but 32bit doesn't. In order to avoid littering the kernel with #ifdefs, let's just select the whole of the GICv3 suport code. You know you want it. Acked-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: vgic: restructure kvm_vgic_(un)map_phys_irqEric Auger2017-11-063-41/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to reuse the core of the map/unmap functions for IRQ forwarding. Let's move the computation of the hwirq in kvm_vgic_map_phys_irq and pass the linux IRQ as parameter. the host_irq is added to struct vgic_irq. We introduce kvm_vgic_map/unmap_irq which take a struct vgic_irq handle as a parameter. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: register irq bypass consumer on ARM/ARM64Eric Auger2017-11-063-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch selects IRQ_BYPASS_MANAGER and HAVE_KVM_IRQ_BYPASS configs for ARM/ARM64. kvm_arch_has_irq_bypass() now is implemented and returns true. As a consequence the irq bypass consumer will be registered for ARM/ARM64 with the forwarding callbacks: - stop/start: halt/resume guest execution - add/del_producer: set/unset forwarding at vgic/irqchip level We don't have any actual support yet, so nothing gets actually forwarded. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Eric Auger <eric.auger@redhat.com> [maz: dropped the DEOI stuff for the time being in order to reduce the dependency chain, amended commit message] Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * Merge git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/coreChristoffer Dall2017-11-0651-347/+2050
| |\
* | \ Merge tag 'armsoc-drivers' of ↵Linus Torvalds2017-11-17110-996/+6933
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "This branch contains platform-related driver updates for ARM and ARM64, these are the areas that bring the changes: New drivers: - driver support for Renesas R-Car V3M (R8A77970) - power management support for Amlogic GX - a new driver for the Tegra BPMP thermal sensor - a new bus driver for Technologic Systems NBUS Changes for subsystems that prefer to merge through arm-soc: - the usual updates for reset controller drivers from Philipp Zabel, with five added drivers for SoCs in the arc, meson, socfpa, uniphier and mediatek families - updates to the ARM SCPI and PSCI frameworks, from Sudeep Holla, Heiner Kallweit and Lorenzo Pieralisi Changes specific to some ARM-based SoC - the Freescale/NXP DPAA QBMan drivers from PowerPC can now work on ARM as well - several changes for power management on Broadcom SoCs - various improvements on Qualcomm, Broadcom, Amlogic, Atmel, Mediatek - minor Cleanups for Samsung, TI OMAP SoCs" [ NOTE! This doesn't work without the previous ARM SoC device-tree pull, because the R8A77970 driver is missing a header file that came from that pull. The fact that this got merged afterwards only fixes it at this point, and bisection of that driver will fail if/when you walk into the history of that driver. - Linus ] * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (96 commits) soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader bus: add driver for the Technologic Systems NBUS memory: omap-gpmc: Remove deprecated gpmc_update_nand_reg() soc: qcom: remove unused label soc: amlogic: gx pm domain: add PM and OF dependencies drivers/firmware: psci_checker: Add missing destroy_timer_on_stack() dt-bindings: power: add amlogic meson power domain bindings soc: amlogic: add Meson GX VPU Domains driver soc: qcom: Remote filesystem memory driver dt-binding: soc: qcom: Add binding for rmtfs memory of: reserved_mem: Accessor for acquiring reserved_mem of/platform: Generalize /reserved-memory handling soc: mediatek: pwrap: fix fatal compiler error soc: mediatek: pwrap: fix compiler errors arm64: mediatek: cleanup message for platform selection soc: Allow test-building of MediaTek drivers soc: mediatek: place Kconfig for all SoC drivers under menu soc: mediatek: pwrap: add support for MT7622 SoC soc: mediatek: pwrap: add common way for setup CS timing extenstion soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap ..
| * | | soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloaderNeil Armstrong2017-11-091-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case the VPU power domain has been powered on by the bootloader and no driver are attached to this power domain, the genpd will power it off after a certain amount of time, but the clocks hasn't been enabled by the kernel itself and the power-off will trigger some faults. This patch enable the clocks to have a coherent state for an eventual poweroff and switches to the pm_domain_always_on_gov governor. Fixes: 75fcb5ca4b46 ("soc: amlogic: add Meson GX VPU Domains driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | Merge tag 'gpmc-omap-for-v4.15-pt2' of https://github.com/rogerq/linux into ↵Arnd Bergmann2017-11-072-41/+24
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/drivers Pull "OMAP-GPMC: driver updates for v4.15, part 2" from Roger Quadros: * get rid of unused function gpmc_update_nand_reg(). * tag 'gpmc-omap-for-v4.15-pt2' of https://github.com/rogerq/linux: memory: omap-gpmc: Remove deprecated gpmc_update_nand_reg()
| | * | | memory: omap-gpmc: Remove deprecated gpmc_update_nand_reg()Ladislav Michl2017-11-032-41/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Deprecated gpmc_update_nand_reg() is no longer used, remove. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * | | | bus: add driver for the Technologic Systems NBUSSebastien Bourdelin2017-11-074-0/+402
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver implements a GPIOs bit-banged bus, called the NBUS by Technologic Systems. It is used to communicate with the peripherals in the FPGA on the TS-4600 SoM. Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | | soc: qcom: remove unused labelArnd Bergmann2017-11-031-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly added driver comes with a harmless warning: drivers/soc/qcom/rmtfs_mem.c: In function 'qcom_rmtfs_mem_probe': drivers/soc/qcom/rmtfs_mem.c:211:1: error: label 'remove_cdev' defined but not used [-Werror=unused-label] This removes the unused label to avoid the warning. Fixes: 702baebb8e00 ("soc: qcom: Remote filesystem memory driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | | soc: amlogic: gx pm domain: add PM and OF dependenciesArnd Bergmann2017-11-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new driver introduces harmless warnings: warning: (PM_RMOBILE && ARCH_RCAR_GEN1 && ARCH_RCAR_GEN2 && ARCH_R7S72100 && MESON_GX_PM_DOMAINS) selects PM_GENERIC_DOMAINS which has unmet direct dependencies (PM) warning: (MESON_GX_PM_DOMAINS) selects PM_GENERIC_DOMAINS_OF which has unmet direct dependencies (PM_GENERIC_DOMAINS && OF) This adds CONFIG_OF and CONFIG_PM dependencies to ensure it will only be enabled in valid configurations. Fixes: 75fcb5ca4b46 ("soc: amlogic: add Meson GX VPU Domains driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | | Merge tag 'amlogic-drivers-2' of ↵Arnd Bergmann2017-11-024-0/+306
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/drivers Pull "Amlogic drivers for v4.15, round 2" from Kevin Hilman: - add PM domain driver for GX VPU * tag 'amlogic-drivers-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: dt-bindings: power: add amlogic meson power domain bindings soc: amlogic: add Meson GX VPU Domains driver
| | * | | | dt-bindings: power: add amlogic meson power domain bindingsNeil Armstrong2017-10-291-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [khilman: minor whitespace fixups] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | | soc: amlogic: add Meson GX VPU Domains driverNeil Armstrong2017-10-293-0/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Video Processing Unit needs a specific Power Domain powering scheme this driver handles this as a PM Power Domain driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * | | | | drivers/firmware: psci_checker: Add missing destroy_timer_on_stack()Lorenzo Pieralisi2017-11-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PSCI checker suspend_test_thread() function (ie executed for the suspend test) requires an on-stack timer to carry out the test it executes; it sets it up through the setup_timer_on_stack() API. setup_timer_on_stack() requires its counterpart destroy_timer_on_stack() to be called when the timer is disposed of but the PSCI checker code is currently missing that call, leaving the timer object in an incosistent state when the PSCI checker stops the thread executing the suspend test. Add the missing destroy_timer_on_stack() call to fix the omission. Fixes: ea8b1c4a6019 ("drivers: psci: PSCI checker module") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reported-by: Kees Cook <keescook@chromium.org> Cc: Kees Cook <keescook@chromium.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | | | Merge tag 'v4.14-next-soc' of https://github.com/mbgg/linux-mediatek into ↵Arnd Bergmann2017-11-026-87/+447
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/drivers Pull "Mediatek: soc driver updates for v4.15" from Matthias Brugger: - add 32 bit read/write support to pwrap - add mt7622 support to pwrap - test build all mediatek soc drivers - fix compiler issues - clean up Kconfig description * tag 'v4.14-next-soc' of https://github.com/mbgg/linux-mediatek: soc: mediatek: pwrap: fix fatal compiler error soc: mediatek: pwrap: fix compiler errors arm64: mediatek: cleanup message for platform selection soc: Allow test-building of MediaTek drivers soc: mediatek: place Kconfig for all SoC drivers under menu soc: mediatek: pwrap: add support for MT7622 SoC soc: mediatek: pwrap: add common way for setup CS timing extenstion soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types soc: mediatek: pwrap: add pwrap_write32 for writing in 32-bit mode soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode dt-bindings: arm: mediatek: add MT7622 string to the PMIC wrapper doc ARM: mediatek: Cocci spatch "of_table" soc: mediatek: pwrap: fixup warnings from coding style
| | * | | | | soc: mediatek: pwrap: fix fatal compiler errorMatthias Brugger2017-10-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When adding the MT6380 compatible, the sentinel for of_device_id was deleted, which leades to the following compiler error: FATAL: drivers/soc/mediatek/mtk-pmic-wrap: struct of_device_id is not terminated with a NULL entry! Fix this by adding the sentinel again. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| | * | | | | soc: mediatek: pwrap: fix compiler errorsMatthias Brugger2017-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compiling using sparse, we got the following error: drivers/soc/mediatek/mtk-pmic-wrap.c:686:25: error: dubious one-bit signed bitfield Changing the data type to unsigned fixes this. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| | * | | | | arm64: mediatek: cleanup message for platform selectionSean Wang2017-10-201-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The latest kernel tree already can support more MediaTek platforms such as MT2712 and MT7622, so additional descriptions for those platforms are added and certain cleanups are also being made here. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| | * | | | | soc: Allow test-building of MediaTek driversJean Delvare2017-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The COMPILE_TEST alternative dependency allows test-building the drivers but only as long as the build system itself will look into the directory where the drivers reside. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Sean Wang <sean.wang@mediatek.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| | * | | | | soc: mediatek: place Kconfig for all SoC drivers under menuSean Wang2017-10-201-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cleanup for placing all Kconfig for all MediaTek SoC drivers under the independent menu as other SoCs vendor usually did. Since the menu would be shown depending on "ARCH_MEDIATEK || COMPILE_TEST" selected and MTK_PMIC_WRAP is still safe compiling with the case of "COMPILE_TEST" only, the superfluous dependency for those items under the menu also is also being removed for the sake of simplicity. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| | * | | | | soc: mediatek: pwrap: add support for MT7622 SoCChenglin Xu2017-10-201-0/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the registers, callbacks and data structures required to make the PMIC wrapper work on MT7622. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| | * | | | | soc: mediatek: pwrap: add common way for setup CS timing extenstionSean Wang2017-10-201-22/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Multiple platforms would always use their own way handling CS timing extension on the bus which leads to a little bit code duplication. Therefore, the patch groups the similar logic to handle CS timing extension into the common function which allows the following SoCs have more reusability for configing CS timing. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-30 02:12:25 +0100