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* pinctrl: mvebu: armada-xp: remove non-existing NAND pinsThomas Petazzoni2015-06-102-4/+2
| | | | | | | | | | | | After updating to a more recent version of the Armada XP datasheet, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.7+ Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mvebu: armada-375: remove non-existing NAND re/we pinsThomas Petazzoni2015-06-102-4/+2
| | | | | | | | | | | | After updating to a more recent version of the Armada 375, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mvebu: armada-370: fix spi0 pin descriptionThomas Petazzoni2015-06-102-4/+4
| | | | | | | | | | | | Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly named "spi0-1" instead of just "spi0". This commit fixes that. This DT binding change does not affect any of the in-tree users. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.7+ Fixes: 5f597bb2be57 ("pinctrl: mvebu: add pinctrl driver for Armada 370") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mvebu: armada-38x: fix PCIe functionsThomas Petazzoni2015-06-102-48/+39
| | | | | | | | | | | | | | | | | | | A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: don't print unavailable function groupsLudovic Desroches2015-06-101-1/+4
| | | | | | | | | There is no reason to try to print groups associated to a function if get_function_groups returns an error. Moreover, it can lead to a NULL pointer dereference error. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: dt-binding: Add DT binding documentation for MSM8660Bjorn Andersson2015-06-101-0/+90
| | | | | Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: Add MSM8660 pinctrl definitionsBjorn Andersson2015-06-103-0/+993
| | | | | Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: berlin: comment the spi functionsAntoine Tenart2015-06-103-21/+21
| | | | | | | | Add comments for the SPI functions, to distinguish CLK, SDI, SDO and C{0,1,2,3}n. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: berlin: fix spi1 SS0n function nameAntoine Tenart2015-06-101-1/+1
| | | | | | | | Rename function ss0 to spi1 to be consistent with the other Berlin function names. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Add allwinner A33 PIO controller supportVishnu Patekar2015-06-044-0/+520
| | | | | | | | | | A33 PIO has 7 ports which starts from PB and has two interrupt ports. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: samsung: Fix the pointer in PTR_ERR()Fabio Estevam2015-06-041-1/+1
| | | | | | | | | | PTR_ERR should access the value just tested by IS_ERR The semantic patch that makes this change is available in scripts/coccinelle/tests/odd_ptr_err.cocci. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Remove .owner fieldFabio Estevam2015-06-047-8/+0
| | | | | | | | | | | platform_driver does not need to set the owner field, as it will be populated by the driver core, so just remove it. The semantic patch that makes this change is available in scripts/coccinelle/api/platform_no_drv_owner.cocci. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: fix confusing debug message in pinctrl_register_map()Masahiro Yamada2015-06-021-1/+1
| | | | | | | | | | | There are two types for pinctrl maps: pinmux and pinconfig This debug message shows the number of maps of both types. The string "pinmux map" is not precise. Let's say "pinctrl map" instead. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [also fixed %d -> %u] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: add static const to zynq_pctrl_groupsMasahiro Yamada2015-06-021-1/+1
| | | | | | | | This array is only referenced in this file and never updated. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: add static to zynq_pinsMasahiro Yamada2015-06-021-1/+1
| | | | | | | This array is only referenced in this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: Fix pinctrl register irq fail bug.Hongzhou Yang2015-06-021-2/+2
| | | | | | | | | | | | | | | Since mt6397 is no need to support interrupt controller, I judged "interrupt-controller" property to skip it last patch. But the if judgement should on the contrary, this is a bug. And find of_property_read_bool is better for this case. So using of_property_read_bool instead of of_find_property. Also fix bug of misuse pointer. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Reviewed-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: Fix bug of ies/smt setting for mt8173.Hongzhou Yang2015-06-021-1/+9
| | | | | | | | Add ies/smt support for MSDC3. Also fix ies bug for pin 106 and 107. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Spelling s/reseved/reserved/Geert Uytterhoeven2015-06-012-20/+20
| | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: use "const struct ..." rather than "struct ... const"Masahiro Yamada2015-06-011-1/+1
| | | | | | | | | | | Only this member, pins, is defined as "struct ... const *", but the others in this struct, pinlops, pmxops, confops, etc. are defined as "const struct ... *". Swap the "struct pinctrl_pin_desc" and "const" for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: remove useless const qualifierMasahiro Yamada2015-06-011-1/+1
| | | | | | | | | This "const" claims the get_function_groups callback never changes the given num_groups pointer. It is always true in C language, so not worth mentioning. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SELMasahiro Yamada2015-06-011-4/+4
| | | | | | | | | | | | The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830, 0xf8000834, respectively. Each offset address must be prefixed with 0x. Fixes: add958cee967 "pinctrl: Add driver for Zynq" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macroMasahiro Yamada2015-06-011-1/+2
| | | | | | | | | The offset to the mux register is missing. Fixes: add958cee967 "pinctrl: Add driver for Zynq" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra-xusb: Fix allocation of pinsJon Hunter2015-06-011-0/+18
| | | | | | | | | | | | | | | | | | | | | | Commit e5b3b2d9ed20 ("pinctrl: allows not to define the get_group_pins operation") allows pin controllers not to register the get_group_pins() function. However, a side-effect of not registering this function is that pins are not allocated and potentially multiple devices could attempt to configure the same pins [1]. Although this problem exists in the pinctrl core, because only a few devices are impacted by this, fix this for tegra-xusb by adding the get_group_pins() function. Please note that in addition to adding the get_group_pins() functions the pins/lanes for the tegra-xusb also need to be registered when calling pinctrl_register(). This also allows the current pinmux state to be viewed by the debugfs node "pinmux-pins" for the tegra-xusb pad controller. [1] http://www.spinics.net/lists/linux-gpio/msg05810.html Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra-xusb: Remove unused structureJon Hunter2015-06-011-5/+0
| | | | | | | | | The structure tegra_xusb_padctl_group is defined but never used and so remove this. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: improve debugfs for strict controllersLinus Walleij2015-05-281-8/+33
| | | | | | | | | | If we know we are using a strict pin controller (one that cannot mix device functions+group use and GPIO) we can be a bit more specific in debugfs, just print either device-function-group or GPIO consumer for the pin. Let's do that to be helpful. Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: add OF dependency to MT6397Linus Walleij2015-05-201-0/+1
| | | | | | | | | | | | X86_64 allmodconfig screams like so: warning: (PINCTRL_MT6397) selects PINCTRL_MTK_COMMON which has unmet direct dependencies (PINCTRL && (ARCH_MEDIATEK || COMPILE_TEST) && OF) So add OF to dependencies to shut up this warning. Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7791: Add PWM pin groups and functionsYoshihiro Shimoda2015-05-191-0/+125
| | | | | | | Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sirf: add sirf atlas7 pinctrl and gpio supportWei Chen2015-05-195-0/+4801
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Pinctrl module (ioc) controls the Pad's function select (each pad can have 8 functions), Pad's Drive Strength, Pad's Pull Select and Pad's Input Disable status. The ioc has two modules, ioc_top & ioc_rtc. Both of these two modules have function select/clear, Pull select and Drive Strength registers. But only ioc_rtc has input-disable registers. The Pads on ioc_top have to access ioc_rtc to set their input-disable status and intpu-disable-value. So have to use one ioc driver instance to drive these two ioc modules at the same time, and each ioc module will be treat as one bank on the "IOC Device". The GPIO Controller controls the GPIO status if the Pad has been config as GPIO by Pinctrl already. Includes the GPIO Input/output, Interrupt type, Interrupt Status, and Set/Get Values. The GPIO pull up/down are controlled by Pinctrl. There are 7 GPIO Groups and splited into 3 MACROs in atlas7. The GPIO Groups in one MACRO share one GPIO controllers, each GPIO Group are treated as one GPIO bank. For example: In VDIFM macro, there is one GPIO Controller, it has 3 banks to control 3 gpio groups. Its gpio name space is from 0 to 95. The Device Tree can be written as following: gpio-ranges = <&pinctrl 0 0 0>, <&pinctrl 32 0 0>, <&pinctrl 64 0 0>; gpio-ranges-group-names = "gnss_gpio_grp", "lcd_vip_gpio_grp", "sdio_i2s_gpio_grp"; bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp". bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp". bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp". Signed-off-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: zynq: add static to platform_driver remove callbackMasahiro Yamada2015-05-191-1/+1
| | | | | | | | This function is only referenced in this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7790: Add PWM pin groups and functionsYoshihiro Shimoda2015-05-191-0/+101
| | | | | | | Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: add pinctrl/GPIO/EINT driver for mt8127Yingjoe Chen2015-05-194-0/+1684
| | | | | | | | | MT8127 pinctrl/eint are similar to mt8135 and mt8173, add support for mt8127 using mediatek common pinctrl driver. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: Add Pinctrl/GPIO driver for mt6397.Hongzhou Yang2015-05-198-5/+524
| | | | | | | | | | | | | | Add mt6397 support using mediatek common pinctrl driver. mt6397 is a PMIC, and pinctrl/GPIO is part of 6397 chip. Pinctrl/GPIO driver should obtain regmap from PMIC, so adding this support to common code. Also, mt6397 is no need to support interrupt controller, so changing common code to skip it. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: add ies/smt control to common code.Hongzhou Yang2015-05-193-116/+198
| | | | | | | | | | | | | | Input enable and smt setting have different register, modify code to fix it. Several mediatek soc use similar input enable/smt setting procedure as mt8173, some soc use generic input enable/smt setting, some soc has no input enable/smt setting. Adding common code to handle all those cases, so future soc driver can use it. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: add mtk_pctrl_spec_pull_set_samereg common codeYingjoe Chen2015-05-193-121/+136
| | | | | | | | | | | Several mediatek soc use similar pull setting procedure as mt8173, the pupd enable and resistance setting are in the same register. Add common code mtk_pctrl_spec_pull_set_samereg out of spec_pull_set in mt8173 to handle this case, so future soc driver can use it. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: data struct optimize and remove unused memberYingjoe Chen2015-05-192-14/+6
| | | | | | | | | | | | | struct mtk_desc_pin.chip, mtk_pinctrl_devdata.invser_offset and mtk_pinctrl_devdata.chip_type are never used in code. Remove them. Some per-pin data are using int for pin number and offsets. Change to short and rearrange to reduce const data size. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mt6397: Add pinfunc header file for mt6397.Hongzhou Yang2015-05-191-0/+256
| | | | | | | Add pinfunc header file, mt8135/mt8173 relate dts will include it. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: Modify pinctrl bindings for mt6397.Hongzhou Yang2015-05-191-2/+7
| | | | | | | | | Since 6397 is no need to support interrupt controller, moving interrupt controller relate property to optional list. Also adding mt8173 and mt8127 to bindings. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: lpc18xx: add the missing group function mapJoachim Eastwood2015-05-191-7/+76
| | | | | | | | Add the required group function map and fill it at probe using the pin capabilities information already present in the driver. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: cygnus: fixed typo in the gpio driverRay Jui2015-05-191-2/+2
| | | | | | | | Fixed a small typo in the Cygnus GPIO driver Signed-off-by: Jason Uy <jasonuy@broadcom.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add Pistachio SoC pin control driverAndrew Bresticker2015-05-123-0/+1513
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the pin controller present on the IMG Pistachio SoC. This driver provides pinmux and pinconfig operations as well as GPIO and IRQ chips for the GPIO banks. Changes from v4: - Switched to using gpiochip_add_pin_range(). - Fixed up Kconfig entry. Changes from v3: - Addressed review comments from Ezequiel. Changes from v2: - Removed module stuff which would be compiled out. Changes from v1: - Addressed review comments from Linus. - Changed compatible string to "img,pistachio-system-pinctrl". - Look for GPIO sub-nodes by name. - A couple of bug fixes. Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: Kevin Cernekee <cernekee@chromium.org> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: lpc18xx: create pin cap lookup helperJoachim Eastwood2015-05-121-11/+18
| | | | | | | | | | | | | Both pconf_get_pin and pconf_set_pin needs to lookup pin cap based on the pin number. Create a common helper function that both functions can use that also handles the case where no pin number is found in the pins array. This also fixes a small bug in pconf_get_pin where pconf_get_i2c0 would use the pins array index rather than the pin number. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a73a4: Remove obsolete multi-platform checkGeert Uytterhoeven2015-05-121-4/+0
| | | | | | | | | | | | As of commit 9d07d414d4c33d86 ("ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform"), r8a73a4 is only supported in generic ARM multi-platform builds. Hence CONFIG_ARCH_MULTIPLATFORM is always set, and the check can be removed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentationUlrich Hecht2015-05-121-1/+2
| | | | | | | | | | | Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: Enable building of r8a7793 PFC supportUlrich Hecht2015-05-122-0/+6
| | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: Add r8a7793 supportUlrich Hecht2015-05-123-0/+30
| | | | | | | | | | Regarding pin control, r8a7791 and r8a7793 are identical, so it is sufficient to add an sh_pfc_soc_info structure to enable r8a7793 support. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7740: Fix typo SCIFAB in commentGeert Uytterhoeven2015-05-121-1/+1
| | | | | | | | | The last serial port is called "SCIFB", not "SCIFAB". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: sunrisepoint: Add Intel Sunrisepoint-H supportMika Westerberg2015-05-121-0/+263
| | | | | | | | | | Intel Sunrisepoint-H is a desktop version of the PCH (Platform Controller Hub). It has slightly different pin configuration compared to the LP version. This patch adds support for Sunrisepoint-H to the existing pinctrl-sunrisepoint.c driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Grammar s/used in as/used as/Geert Uytterhoeven2015-05-121-1/+1
| | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: Remove r8a73a4 platform_device_id entryGeert Uytterhoeven2015-05-121-3/+0
| | | | | | | | | | | | | As of commit 9d07d414d4c33d86 ("ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform"), r8a73a4 is only supported in generic DT-only ARM multi-platform builds. The driver doesn't need to match platform devices by name anymore, hence remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: use ERR_CAST instead of ERR_PTR/PTR_ERRFabian Frederick2015-05-061-1/+1
| | | | | | | Inspired by scripts/coccinelle/api/err_cast.cocci Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-30 23:10:33 +0100