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* MIPS: Add MFHC0 and MTHC0 instructions to uasm.Steven J. Hill2014-11-244-9/+16
| | | | | | | | | New instructions for Extended Physical Addressing (XPA) functionality. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8453/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cosmetic cleanups of page table headers.Steven J. Hill2014-11-243-67/+71
| | | | | | | | | | | | * Clean up white spaces and tabs. * Remove _PAGE_R4KBUG which is no longer used. * Get rid of hardcoded values and calculate shifts and masks where possible. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8457/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add CP0 macros for extended EntryLo registersSteven J. Hill2014-11-241-0/+40
| | | | | | | | | | Add read/write macros to access the upper bits of the extended EntryLo0 and EntryLo1 registers used by XPA. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8455/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove now unused definition of phys_t.Ralf Baechle2014-11-241-16/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Replace use of phys_t with phys_addr_t.Ralf Baechle2014-11-2423-64/+64
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BITRalf Baechle2014-11-2415-43/+40
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* PCMCIA: Alchemy Don't select 64BIT_PHYS_ADDR in Kconfig.Ralf Baechle2014-11-241-2/+0
| | | | | | | For Alchemy 64BIT_PHYS_ADDR is already always set in arch/mips/Kconfig. Also 64BIT_PHYS_ADDR is about to be removed. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lib: memset: Clean up some MIPS{EL,EB} ifdeferyMarkos Chandras2014-11-241-4/+2
| | | | | | | | | | The toolchain defines exactly one of __MIPSEB__ and __MIPSEL__. As a result, simplify the ifdefery a little bit. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8522/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIOMarkos Chandras2014-11-241-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the __raw_{read,write}{b,w,l} functions to perform repeatable MMIO could result in problems if the host bus does not match the endianness of the PCI/ISA. This problem is visible on big-endian SEAD3 configurations after commit 2925f6c0c7af32720dcbadc586463aeceb6baa22 "net: smc911x: use io{read,write}*_rep accessors". This effectively moves away from using the __mem_* variants to __raw_* ones and causes a kernel bug as follows: Call Trace: CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 00000000, ra == 8012b3b0 Oops[#1]: Cpu 0 $ 0 : 00000000 00000065 00000000 00000004 $ 4 : 00000000 00000000 9a82dd60 00000000 $ 8 : 00000000 00000000 a00ae278 00000007 $12 : 0000000e 00000011 804c4228 ffff9411 $16 : 00000100 00000000 80560000 807fc6d0 $20 : 807fc8d0 807fcad0 807fbec0 00000100 $24 : 00009150 80109be0 $28 : 9a82c000 9a82dd28 00000001 8012b3b0 Hi : 00000000 Lo : 00000000 epc : 00000000 (null) Not tainted ra : 8012b3b0 call_timer_fn.isra.39+0x24/0x84 Status: 10009503 KERNEL EXL IE Cause : 00800808 BadVA : 00000000 PrId : 00019c20 (MIPS M14Kc) Modules linked in: Process swapper (pid: 1, threadinfo=9a82c000, task=9a82ba18, tls=00000000) Stack : 00000040 00000000 00000007 8056732c 80580000 00000001 9a82dd60 00200200 80560000 8012b598 8056732c 80580000 00000001 00000000 9a82dd60 9a82dd60 00000000 807fbd44 807fbd40 805664e0 0000000a 80800000 00000004 80125924 0000fda0 000007f0 80000000 00000001 80800000 007f0000 00200140 80166338 00000000 8100fda0 0000fda0 000007f0 80000000 00000001 80800000 007f0000 ... Call Trace: [<8012b598>] run_timer_softirq+0x188/0x1f4 [<80125924>] __do_softirq+0xc4/0x18c [<80166338>] handle_percpu_irq+0x54/0x84 [<80125aa4>] do_softirq+0x68/0x70 [<80103b50>] do_IRQ+0x18/0x28 [<80125d1c>] irq_exit+0x94/0xc0 [<80125aa4>] do_softirq+0x68/0x70 [<80102130>] ret_from_irq+0x0/0x4 [<80102130>] ret_from_irq+0x0/0x4 [<80125d1c>] irq_exit+0x94/0xc0 [<803165b0>] __bzero+0xd4/0x164 [<80346d0c>] mem32_serial_out+0x0/0x1c [<8010d4ac>] free_init_pages+0x98/0xfc [<80180a08>] free_hot_cold_page+0x2c/0x1c4 [<80180bd8>] __free_pages+0x38/0x98 [<8010d4a0>] free_init_pages+0x8c/0xfc [<8010d4ac>] free_init_pages+0x98/0xfc [<8049fb04>] kernel_init+0x28/0x15c [<80147484>] schedule_tail+0x1c/0x60 [<8049fadc>] kernel_init+0x0/0x15c [<80102178>] ret_from_kernel_thread+0x14/0x1c [<8040a06f>] skb_pad+0xe7/0x13c Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Steve Glendinning <steve.glendinning@shawell.net> Cc: Ben Boeckel <mathstuf@gmail.com> Cc: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Cc: David S. Miller <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: Jeffrey Deans <Jeffrey.Deans@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6672/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: <asm/types.h> fix indentation.Ralf Baechle2014-11-241-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MAINTAINERS: Add entry for BMIPS multiplatform kernelKevin Cernekee2014-11-241-0/+12
| | | | | | | | | | | | | | | | Add myself as a maintainer for the new BMIPS target. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jfraser@broadcom.com Cc: dtor@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8505/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable VDSO randomizationPrem Karat2014-11-241-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on commit 1091458d09e1a (mmap randomization) For 32-bit address spaces randomize within a 16MB space, for 64-bit within a 256MB space. Test Results: ------------ Without Patch (VDSO is not randomized) --------------------------------------- root@Maleo:~# ./aslr vdso FAIL: ASLR not functional (vdso always at 0x7fff7000) root@Maleo:~# ./aslr rekey vdso pre_val==cur_val value=0x7fff7000 With patch:(VDSO is randmoized and doesn't interfere with stack) ---------------------------------------------------------------- root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7f830ea2 current_value=0x776e2000 root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7fb0cea2 current_value=0x77209000 root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7f985ea2 current_value=0x7770c000 root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7fbc6ea2 current_value=0x7fe25000 Maps file output: ------------------------- root@cavium-octeon2:~# ./aslr rekey maps 78584000-785a5000 rwxp 00000000 00:00 0 [heap] 7f9d0000-7f9f1000 rw-p 00000000 00:00 0 [stack] 7ffa5000-7ffa6000 r-xp 00000000 00:00 0 [vdso] root@cavium-octeon2:~# ./aslr rekey maps 77de0000-77e01000 rwxp 00000000 00:00 0 [heap] 7f91b000-7f93c000 rw-p 00000000 00:00 0 [stack] 7ff99000-7ff9a000 r-xp 00000000 00:00 0 [vdso] root@cavium-octeon2:~# ./aslr rekey maps 77d7f000-77da0000 rwxp 00000000 00:00 0 [heap] 7fc2a000-7fc4b000 rw-p 00000000 00:00 0 [stack] 7fe09000-7fe0a000 r-xp 00000000 00:00 0 [vdso] root@cavium-octeon2:~# ./aslr rekey maps 7794c000-7794d000 r-xp 00000000 00:00 0 [vdso] 77e4b000-77e6c000 rwxp 00000000 00:00 0 [heap] 7f6e7000-7f708000 rw-p 00000000 00:00 0 [stack] root@cavium-octeon2:~# Signed-off-by: Prem Karat <pkarat@mvista.com> Cc: linux-mips@linux-mips.org Cc: sergei.shtylyov@cogentembedded.com Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6812 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove a temporary hack for debugging cache flushes in SMTC configurationRalf Baechle2014-11-241-59/+0
| | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: aaro.koskinen@iki.fi Cc: david.daney@cavium.com Cc: linux-kernel@vger.kernel.org Cc: markos.chandras@imgtec.com Cc: dengcheng.zhu@imgtec.com Cc: chenhc@lemote.com Cc: akpm@linux-foundation.org Patchwork: https://patchwork.linux-mips.org/patch/8535/
* MIPS: Remove declaration of obsolete arch_init_clk_ops()Maarten ter Huurne2014-11-241-3/+0
| | | | | | | | | Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Cc: Apelete Seketeli <apelete@seketeli.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7671/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: atomic.h: Reformat to fit in 79 columnsMaciej W. Rozycki2014-11-241-180/+181
| | | | | | | Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8484/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Apply `.insn' to fixup labels throughoutMaciej W. Rozycki2014-11-243-0/+8
| | | | | | | | | | | | | | | | | | | | Fix the issue with the ISA bit being lost in fixups that jump to labels placed just before a section switch. Such a switch leads to the ISA bit being lost, because GAS concludes there is no code that follows and therefore the label refers to data. Use the `.insn' pseudo-op to convince the tool this is not the case. This lack of label annotation leads to microMIPS compilation errors like: mips-linux-gnu-ld: arch/mips/built-in.o: .fixup+0x3b8: Unsupported jump between ISA modes; consider recompiling with interlinking enabled. mips-linux-gnu-ld: final link failed: Bad value Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix microMIPS LL/SC immediate offsetsMaciej W. Rozycki2014-11-249-91/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the microMIPS encoding some memory access instructions have their immediate offset reduced to 12 bits only. That does not match the GCC `R' constraint we use in some places to satisfy the requirement, resulting in build failures like this: {standard input}: Assembler messages: {standard input}:720: Error: macro used $at after ".set noat" {standard input}:720: Warning: macro instruction expanded into multiple instructions Fix the problem by defining a macro, `GCC_OFF12_ASM', that expands to the right constraint depending on whether microMIPS or standard MIPS code is produced. Also apply the fix to where `m' is used as in the worst case this change does nothing, e.g. where the pointer was already in a register such as a function argument and no further offset was requested, and in the best case it avoids an extraneous sequence of up to two instructions to load the high 20 bits of the address in the LL/SC loop. This reduces the risk of lock contention that is the higher the more instructions there are in the critical section between LL and SC. Strictly speaking we could just bulk-replace `R' with `ZC' as the latter constraint adjusts automatically depending on the ISA selected. However it was only introduced with GCC 4.9 and we keep supporing older compilers for the standard MIPS configuration, hence the slightly more complicated approach I chose. The choice of a zero-argument function-like rather than an object-like macro was made so that it does not look like a function call taking the C expression used for the constraint as an argument. This is so as not to confuse the reader or formatting checkers like `checkpatch.pl' and follows previous practice. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8482/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Kconfig: Only allow 32-bit microMIPS buildsMaciej W. Rozycki2014-11-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Only allow 32-bit microMIPS builds, we're not ready yet for 64-bit microMIPS support. QEMU does have support for the 64-bit microMIPS ISA and with minor tweaks it is possible to have a 64-bit processor emulated there that runs microMIPS code, so despite the lack of actual 64-bit microMIPS hardware there is a way to run 64-bit microMIPS Linux, but it can all be considered early development and we are not there yet. Userland tools are lacking too, e.g. GCC produces bad code: {standard input}: Assembler messages: {standard input}:380: Warning: wrong size instruction in a 16-bit branch delay slot And our build fails early on, so disable the configuration, for the sake of automatic random config checkers if nothing else. Whoever needs to experiment with 64-bit microMIPS support can revert this change easily. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8481/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: signal.c: Fix an invalid cast in ISA mode bit handlingMaciej W. Rozycki2014-11-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix: arch/mips/kernel/signal.c: In function 'handle_signal': arch/mips/kernel/signal.c:533:21: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] unsigned int tmp = (unsigned int)current->mm->context.vdso; ^ arch/mips/kernel/signal.c:536:9: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] vdso = (void *)tmp; ^ cc1: all warnings being treated as errors when building a 64-bit kernel. This is not really a supported configuration, but the cast is wrong either way, Linux makes the assumption that sizeof(void *) equals sizeof(unsigned long) and therefore the latter type is expected to be used where integer operations have to be applied to pointers for some reason. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8480/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: mm: Only build one microassembler that is suitableMaciej W. Rozycki2014-11-241-3/+7
| | | | | | | | | | | | | | | | | | | | | The microMIPS microassembler is only suitable for configurations where the kernel itself is built to microMIPS machine code and not where only user microMIPS software is supported. The former is controlled with the CPU_MICROMIPS configuration setting, whereas SYS_SUPPORTS_MICROMIPS is used for the latter. Not only that, but with a given microMIPS vs standard MIPS kernel configuration only one microassembler is needed, that matches the ISA selected -- CP0.Config3.ISAOnExc is mandatory on microMIPS processors, so there is never a need to mix microMIPS and standard MIPS code. Consequently build only the microassembler that matches the ISA selected for the kernel. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8479/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Kconfig: Enable microMIPS support for MaltaMaciej W. Rozycki2014-11-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Add missing microMIPS support to Malta. Currently the kernel only enables support for the instruction set for the SEAD-3 board despite the fact processor features have nothing to do with the board a processor is installed in. In this case there is no way to run microMIPS software in a fully supported way under Linux on QEMU. QEMU supports the emulation of a Malta board, but does not emulate SEAD-3. Linux supports running microMIPS code on a SEAD-3 board, but hardcodes such support to off on an emulated Malta board even if the processor selected has the microMIPS instruction set implemented. Adding support for the SEAD-3 to QEMU is a major project. Flipping a bit in the kernel that shouldn't have been cleared in the first place is a trivial effort. Thus the answer is plain... Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8478/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: loongson: common: rtc: make loongson_rtc_resources staticAaro Koskinen2014-11-241-1/+1
| | | | | | | | | | | Make loongson_rtc_resources static to eliminate the following sparse warning: warning: symbol 'loongson_rtc_resources' was not declared. Should it be static? Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8529/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: loongson: common: init: Add a missing includeAaro Koskinen2014-11-241-0/+1
| | | | | | | | | | | Add a missing include to eliminate the following sparse warnings: warning: symbol 'prom_init' was not declared. Should it be static? warning: symbol 'prom_free_prom_memory' was not declared. Should it be static? Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8531/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: loongson: lemote-2f: reset: make ml2f_reboot staticAaro Koskinen2014-11-241-1/+1
| | | | | | | | | | Make ml2f_reboot static to elimite the following sparse warning: warning: symbol 'ml2f_reboot' was not declared. Should it be static? Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8528/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: loongson: lemote-2f: irq: Make internal data staticAaro Koskinen2014-11-241-2/+2
| | | | | | | | | | | Make internal static to eliminate the following sparse warnings: warning: symbol 'ip6_irqaction' was not declared. Should it be static? warning: symbol 'cascade_irqaction' was not declared. Should it be static? Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8527/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: loongson: common: Setup: add a missing includeAaro Koskinen2014-11-241-0/+1
| | | | | | | | | | Add a missing include to get rid of the following sparse warning: warning: symbol 'plat_mem_setup' was not declared. Should it be static? Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8530/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: cs5536_pci: Add a missing includeAaro Koskinen2014-11-241-0/+1
| | | | | | | | | | | Add a missing include to get rid of the following sparse warnings: warning: symbol 'cs5536_pci_conf_write4' was not declared. Should it be static? warning: symbol 'cs5536_pci_conf_read4' was not declared. Should it be static? Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8526/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: common: Fix array initializer syntax.Aaro Koskinen2014-11-243-32/+32
| | | | | | | | | | Fix array initializer syntax to get rid of the following sparse warnings: "obsolete array initializer, use C99 syntax". Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8525/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uaccess.h: Fix strnlen_user comment.Ralf Baechle2014-11-241-4/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP22/IP32: Add line to arch/mips/Makefile archhelp about vmlinux.32Joshua Kinard2014-11-241-0/+1
| | | | | | | | | | | | | Building a 64bit kernel for the SGI O2 (IP32) and the SGI Indy (IP22) uses the 'vmlinux.32' target, which converts the output 64-bit 'vmlinux' image into a 32-bit wrapped image. This is needed for certain revisions of the IP22 and IP32 ARCS PROMs to boot correctly, but this target is missing from the 'archhelp' info that is emitted by 'make help'. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7991/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lib: mips-atomic.c: Remove obsolete ifdeferyMarkos Chandras2014-11-241-20/+0
| | | | | | | | | | | Having #ifdefs just to guard comments is not really helpful so drop them. Moreover, the code wasn't really reached anyway since there is a #ifndef CONFIG_CPU_MIPSR2 on the top of the file. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8513/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Mark octeon_model_get_string() with __initAaro Koskinen2014-11-243-7/+5
| | | | | | | | | | | Mark octeon_model_get_string() with __init and make internal functions static. Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7668/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Move code to avoid forward declarationAaro Koskinen2014-11-241-19/+19
| | | | | | | | | | Move code to avoid forward declarations. Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7667/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Delete potentially dangerous feature checksAaro Koskinen2014-11-242-95/+0
| | | | | | | | | | | | | | We should not need to read fuses during normal operation, also the current code has issues with that (not safe for concurrent access). Since there are no in-kernel users for these, just delete them. Drivers should not need such OCTEON_HAS_FEATURE mechanism in any case, instead the information should be passed via device tree. Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7665/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Move cvmx_fuse_read_byte()Aaro Koskinen2014-11-242-19/+21
| | | | | | | | | | | Move cvmx_fuse_read_byte() into a .c file. Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Aaro Koskinen <aaro.koskinen@nsn.com> Patchwork: https://patchwork.linux-mips.org/patch/7666/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: oprofile: Backtrace: don't fail on leaf functionsAaro Koskinen2014-11-241-2/+3
| | | | | | | | | | | Continue the backtrace if we cannot find SP adjustment and RA save. In that case, just assume the current RA. This allows us to get samples of frequent callers of e.g. GLIBC memset(). Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8109/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: oprofile: Enable backtrace on timer-based profilingAaro Koskinen2014-11-241-1/+6
| | | | | | | | | | | | | Allow unsupported CPU types to use backtrace with timer-based profiling. Some CPUs (notably OCTEON) lack architecture-specific oprofile driver. In such case oprofile can fallback to timer-based mode, and arch code can still provide the backtrace functionality. So just set up the backtrace hook always. Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8108/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: traps: Dump the PageGrain and Wired registers on MCMarkos Chandras2014-11-241-0/+2
| | | | | | | | | | They can be useful to determine how the MMU is configured on a MC exception. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8401/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: traps: Dump the HTW registers on a MC exceptionMarkos Chandras2014-11-241-0/+5
| | | | | | | | | The HTW registers can be useful to debug a MC exception. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8400/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: traps: Replace printk with pr_err for MC exceptionsMarkos Chandras2014-11-241-6/+6
| | | | | | | | | printk should not be used without a KERN_ facility level Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8399/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clocksource: mips-gic: Add device-tree supportAndrew Bresticker2014-11-242-7/+35
| | | | | | | | | | | | | | | | | | | | | | | | Parse the GIC timer frequency and interrupt from the device-tree. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8421/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Add device-tree supportAndrew Bresticker2014-11-241-5/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | Add device-tree support for the MIPS GIC. Update the GIC irqdomain's xlate() callback to handle the three-cell specifier described in the MIPS GIC binding document. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8422/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* of: Add binding document for MIPS GICAndrew Bresticker2014-11-242-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Global Interrupt Controller (GIC) present on certain MIPS systems can be used to route external interrupts to individual VPEs and CPU interrupt vectors. It also supports a timer and software-generated interrupts. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8420/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Read the initrd address from the firmware environmentAlban Bedel2014-11-241-0/+8
| | | | | | | | | | Allow loading an initrd passed by the firmware. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Use the firmware lib to parse the kernel command lineAlban Bedel2014-11-241-28/+2
| | | | | | | | | | | | No need to duplicate code that is available in the firmware library. It also give us access to the firmware environment which is needed to read the initrd address and size. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8353/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath25: add Wireless device supportSergey Ryazanov2014-11-244-0/+79
| | | | | | | | | | | Atheros AR5312 and AR2315 both have a builtin wireless device, this patch add helper code and register platform device for all supported WiSoCs. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8249/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* ath5k: update dependenciesSergey Ryazanov2014-11-245-11/+11
| | | | | | | | | | | | | | | | | | | | - Use config symbol defined in the driver instead of arch specific one for conditional compilation. - Rename the ATHEROS_AR231X config symbol to ATH25. - Fix include (ar231x_platform.h -> ath25_platform.h). - Some of AR231x SoCs (e.g. AR2315) have PCI bus support, so remove !PCI dependency, which block AHB support build. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Acked-by: John W. Linville <linville@tuxdriver.com> Cc: Jiri Slaby <jirislaby@gmail.com> Cc: Nick Kossifidis <mickflemm@gmail.com> Cc: "Luis R. Rodriguez" <mcgrof@do-not-panic.com> Cc: linux-wireless@vger.kernel.org Cc: ath5k-devel@lists.ath5k.org Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8248/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* ath5k: revert AHB bus support removingSergey Ryazanov2014-11-246-3/+294
| | | | | | | | | | | | | | | | | | | This reverts commit 093ec3c5337434f40d77c1af06c139da3e5ba6dc. AHB bus code has been removed, since we did not have support Atheros AR231x SoC, required for building the AHB version of ath5k. Now that support WiSoC chips added we can restore functionality back. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Acked-by: John W. Linville <linville@tuxdriver.com> Cc: Jiri Slaby <jirislaby@gmail.com> Cc: Nick Kossifidis <mickflemm@gmail.com> Cc: "Luis R. Rodriguez" <mcgrof@do-not-panic.com> Cc: linux-wireless@vger.kernel.org Cc: ath5k-devel@lists.ath5k.org Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath25: add AR2315 PCI host controller driverSergey Ryazanov2014-11-245-3/+597
| | | | | | | | | Add PCI host controller driver and DMA address calculation hook. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8246/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath25: register AR5312 flash controllerSergey Ryazanov2014-11-241-2/+36
| | | | | | | | | | | AR5312 SoC flash controller maps the flash content to memory and translates the memory access operations to the flash access operations. Such controller is fully supported by the physmap-flash driver. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>R5312 SoC flash Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8245/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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