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* MN10300: And Panasonic AM34 subarch and implement SMPAkira Takeuchi2010-10-2780-482/+4495
| | | | | | | | | | Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Delete idle_timestamp from irq_cpustat_tAkira Takeuchi2010-10-272-3/+0
| | | | | | | | Delete idle_timestamp from irq_cpustat_t as it's an unread relic. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Make various interrupt priority settings configurableAkira Takeuchi2010-10-272-6/+76
| | | | | | | | | Make the settings of interrupt priorities used by various services configurable at run time. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Optimise do_csum()Akira Takeuchi2010-10-271-27/+22
| | | | | | | | | Optimise do_csum() to gang up the loads so they're less likely to get interruptions between. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Implement atomic ops using atomic ops unitMark Salter2010-10-272-47/+351
| | | | | | | | Implement atomic ops using the atomic ops unit available in the AM34 CPU. This allows the equivalent of the LL/SC instructions to be found on other CPUs. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Make the FPU operate in non-lazy mode under SMPAkira Takeuchi2010-10-2714-248/+440
| | | | | | | | | | Make the FPU operate in non-lazy mode under SMP so that when the process that is currently using the FPU migrates to a different CPU, we don't have to ping its previous CPU to flush the FPU context. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: SMP TLB flushingAkira Takeuchi2010-10-274-29/+290
| | | | | | | | | Implement global TLB flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB controlAkira Takeuchi2010-10-273-47/+65
| | | | | | | | | Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits are a more suitable layout. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Make the use of PIDR to mark TLB entries controllableAkira Takeuchi2010-10-274-62/+84
| | | | | | | | | Make controllable the use of the PIDR register to mark TLB entries as belonging to particular processes. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Rename __flush_tlb*() to local_flush_tlb*()David Howells2010-10-276-28/+42
| | | | | | | | | | Rename __flush_tlb*() to local_flush_tlb*() as it's more appropriate, and ready to differentiate local from global TLB flushes when SMP is introduced. Whilst we're at it, get rid of __flush_tlb_global() and make local_flush_tlb_page() take an mm_struct pointer rather than VMA pointer. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: AM34 erratum requires MMUCTR read and write on exception entryAkira Takeuchi2010-10-273-6/+37
| | | | | | | | | An AM34 erratum requires MMUCTR read and write on entry to certain exceptions, prior to EPSW.NMID being cleared to allow NMIs to happen. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Make the boot wrapper able to use writeback cachingAkira Takeuchi2010-10-271-1/+48
| | | | | | | | | Make the boot wrapper able to use writeback caching, including flushing the cache before jumping to the main kernel. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Cache: Implement SMP global cache flushingAkira Takeuchi2010-10-279-15/+535
| | | | | | | | | Implement SMP global cache flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Allow some cacheflushes to be avoided if cache snooping is availableDavid Howells2010-10-279-96/+309
| | | | | | | The AM34 core is able to do cache snooping, and so can skip some of the cache flushing. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: AM34: Add cacheflushing by using the AM34 purge registersAkira Takeuchi2010-10-274-1/+678
| | | | | | | | | | The AM34 CPU core provides an automated way of purging the cache rather than manually iterating over all the tags in the cache. Make it possible to use these. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: SMP: Differentiate local cache flushingAkira Takeuchi2010-10-274-112/+289
| | | | | | | | | | | | | | | | | | | Differentiate local cache flushing from global cache flushing so that they can be done differently on SMP systems. Rename the cache functions from: mn10300_[id]cache_*() to: mn10300_[id]_localcache_*() and on a UP system, assign the global labels to the local labels. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Cacheflush functions should take unsigned long addressesAkira Takeuchi2010-10-272-15/+15
| | | | | | | | | The functions that perform cache flushing should take addresses of unsigned long type, not unsigned int. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: AM34: The current cacheflush routines operate by controlling tag regsDavid Howells2010-10-274-2/+23
| | | | | | | | | | The current cache flush and invalidate routines operate by controlling the cache tag registers. Rename the files and add config items to select them. This makes it easier to support the use of other cache flush methods instead, such as the use of AM34's area purge registers, if available. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Reorder asm/cacheflush.h to put primitives firstDavid Howells2010-10-271-44/+44
| | | | | | | | Reorder asm/cacheflush.h to put arch primitives first, before the main functions so that the main functions can be inline asm rather than #defines when non-trivial. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Provide a MN10300_CACHE_ENABLED config optionDavid Howells2010-10-276-10/+13
| | | | | | | Provide a MN10300_CACHE_ENABLED config option as inverted logic of MN10300_CACHE_DISABLED to make things simpler. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Cache: Split cache bits out of arch KconfigDavid Howells2010-10-272-28/+33
| | | | | | Split the cache bits out of arch/mn10300/Kconfig as they're quite complex. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Remove monitor/JTAG functionsAkira Takeuchi2010-10-274-55/+2
| | | | | | | | | Remove the monitor trap function and the set_jtag_stub function as they're not really necessary. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Add CPU register bits for AM34Akira Takeuchi2010-10-272-5/+74
| | | | | | | | Add CPU register declarations for the AM34 subarch. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Don't hard code the cacheline size in register defsAkira Takeuchi2010-10-271-5/+9
| | | | | | | | Don't hard code the cacheline size in the cache control register definitions. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Move DMA engine control reg defs to MN103E010 processor directoryAkira Takeuchi2010-10-272-86/+103
| | | | | | | | | Move the DMA engine control register definitions to the MN103E010 processor directory so that the MN2WS0050 processor can have its own. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Differentiate AM33_2 and AM33_3 in configAkira Takeuchi2010-10-271-2/+9
| | | | | | | | | | | Differentiate AM33_2 and AM33_3 CPU cores in configuration. The MN103E010 processor contains an AM33_2 core. Whilst we're at it, prepare for AM34-based stuff by declaring AM34_2 too. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Provide the functions to fully disable maskable interruptsAkira Takeuchi2010-10-271-0/+77
| | | | | | | | | | | | | | The local_irq_disable() function and co. merely raise the interrupt mask on the MN10300 arch to exclude normal interrupts. This still lets other, higher priority maskable interrupts through, such as are used to service gdbstub's serial port and the MN10300 on-chip serial port virtual FIFOs. Provide functions to allow the maskable interrupts to be fully disabled, which will exclude those interrupts. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Add reads[bwl]() and writes[bwl]()Akira Takeuchi2010-10-271-0/+13
| | | | | | | | Add reads[bwl]() and writes[bwl]() for MN10300. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Don't cast away the volatile in test_bit()Akira Takeuchi2010-10-271-1/+1
| | | | | | | | | Don't cast away the volatile in test_bit()'s parameter when we change its type from const volatile void * so that we can dereference it. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* Typedef SMP call function pointerDavid Howells2010-10-272-13/+14
| | | | | | | | | | | | Typedef the pointer to the function to be called by smp_call_function() and friends: typedef void (*smp_call_func_t)(void *info); as it is used in a fair number of places. Signed-off-by: David Howells <dhowells@redhat.com> cc: linux-arch@vger.kernel.org
* MN10300: Prevent cnt32_to_63() from being preempted in sched_clock()David Howells2010-10-271-0/+5
| | | | | | | | | | | | | | | Prevent cnt32_to_63() from being preempted in sched_clock() because it may read its internal counter, get preempted, get delayed for more than the half period of the 'TSC' and then write the internal counter, thus corrupting it. Whilst some callers of sched_clock() have interrupts disabled or hold spinlocks, not all do, and so preemption must be held here. Note that sched_clock() is called from lockdep, but that shouldn't be a problem because although preempt_disable() calls into lockdep, lockdep has a recursion counter to deal with this. Signed-off-by: David Howells <dhowells@redhat.com>
* mn10300: Use pci_claim_resourceDavid Howells2010-10-271-10/+6
| | | | | | | | Instead of open-coding pci_find_parent_resource and request_resource, just call pci_claim_resource. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: David Howells <dhowells@redhat.com>
* bitops: Change the bitmap index from int to unsigned long [mn10300]Justin Chen2010-10-272-8/+8
| | | | | | | | Change the index to unsigned long in all bitops for [mn10300] Signed-off-by: Justin Chen <justin.chen@hp.com> Reviewed-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: BUG to BUG_ON changesStoyan Gaydarov2010-10-275-10/+5
| | | | | Signed-off-by: Stoyan Gaydarov <stoyboyker@gmail.com> Signed-off-by: David Howells <dhowells@redhat.com>
* Partially revert patch that encloses asm-offset.h numbers in bracketsDavid Howells2010-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Partially revert patch: commit 3234282f33b29d349bcada40204fc7c8fda7fe72 Author: Jan Beulich <JBeulich@novell.com> Date: Tue Oct 19 14:52:26 2010 +0100 x86, asm: Fix CFI macro invocations to deal with shortcomings in gas This breaks MN10300 arch as this changes many instances of instructions similar to the following: MOV number,D0 which represents an immediate value load into: MOV (number),D0 which the assembler then interprets as a load from absolute address. arch/mn10300/kernel/entry.S:64: Error: Invalid opcode/operands arch/mn10300/kernel/entry.S:65: Error: junk at end of line, first unrecognized character is `0' arch/mn10300/kernel/entry.S:74: Error: Invalid opcode/operands arch/mn10300/kernel/entry.S:74: Error: junk at end of line, first unrecognized character is `1' arch/mn10300/kernel/entry.S:75: Error: Invalid opcode/operands arch/mn10300/kernel/entry.S:76: Error: junk at end of line, first unrecognized character is `0' cc: Jan Beulich <jbeulich@novell.com> cc: Alexander van Heukelum <heukelum@fastmail.fm> cc: H. Peter Anvin <hpa@linux.intel.com> cc: Ingo Molnar <mingo@elte.hu> Signed-off-by: David Howells <dhowells@redhat.com>
* fix braino in fs: do not assign default i_ino in new_inodeAl Viro2010-10-271-1/+1
| | | | | | | | | | | usbfs_get_inode() is something completely different... Bogosity introduced by commit 85fe4025c616 ("fs: do not assign default i_ino in new_inode"). Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Cc: Christoph Hellwig <hch@lst.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'drm-core-next' of ↵Linus Torvalds2010-10-27212-11671/+18747
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (476 commits) vmwgfx: Implement a proper GMR eviction mechanism drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2 drm/radeon/kms: properly compute group_size on 6xx/7xx drm/radeon/kms: fix 2D tile height alignment in the r600 CS checker drm/radeon/kms/evergreen: set the clear state to the blit state drm/radeon/kms: don't poll dac load detect. gpu: Add Intel GMA500(Poulsbo) Stub Driver drm/radeon/kms: MC vram map needs to be >= pci aperture size drm/radeon/kms: implement display watermark support for evergreen drm/radeon/kms/evergreen: add some additional safe regs v2 drm/radeon/r600: fix tiling issues in CS checker. drm/i915: Move gpu_write_list to per-ring drm/i915: Invalidate the to-ring, flush the old-ring when updating domains drm/i915/ringbuffer: Write the value passed in to the tail register agp/intel: Restore valid PTE bit for Sandybridge after bdd3072 drm/i915: Fix flushing regression from 9af90d19f drm/i915/sdvo: Remove unused encoding member i915: enable AVI infoframe for intel_hdmi.c [v4] drm/i915: Fix current fb blocking for page flip drm/i915: IS_IRONLAKE is synonymous with gen == 5 ... Fix up conflicts in - drivers/gpu/drm/i915/{i915_gem.c, i915/intel_overlay.c}: due to the new simplified stack-based kmap_atomic() interface - drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: added .llseek entry due to BKL removal cleanups.
| * vmwgfx: Implement a proper GMR eviction mechanismThomas Hellstrom2010-10-279-160/+252
| | | | | | | | | | | | | | | | | | | | Use Ben's new range manager hooks to implement a manager for GMRs that manages ids rather than ranges. This means we can use the standard TTM code for binding, unbinding and eviction. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2Alex Deucher2010-10-271-0/+3
| | | | | | | | | | | | | | | | | | | | broken by: drm/radeon/r600: fix tiling issues in CS checker. v2: only apply it to 1D tiling case. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: properly compute group_size on 6xx/7xxAlex Deucher2010-10-262-6/+10
| | | | | | | | | | | | | | | | Needed for tiled surfaces. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: fix 2D tile height alignment in the r600 CS checkerAlex Deucher2010-10-261-2/+2
| | | | | | | | | | | | | | | | | | | | macro tile heights are aligned to num channels, not num banks. Noticed by Dave Airlie. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms/evergreen: set the clear state to the blit stateAlex Deucher2010-10-264-54/+65
| | | | | | | | | | | | | | | | | | | | | | The hw stores a default clear state for registers in the context range that can be initialized when the CP is set up. Set the blit state as the default clear state and use the CLEAR_STATE packet to load the blit state rather than loading it from an IB. This reduces overhead when doing bo moves using the 3D engine. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: don't poll dac load detect.Dave Airlie2010-10-261-0/+10
| | | | | | | | | | | | This is slightly destructive, cpu intensive and can cause lockups. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * gpu: Add Intel GMA500(Poulsbo) Stub DriverLee, Chun-Yi2010-10-265-1/+81
| | | | | | | | | | | | | | | | | | | | | | Currently, there have no GMA500(Poulsbo) native video driver to support intel opregion. So, use this stub driver to enable the acpi backlight control sysfs entry files by requrest acpi_video_register. [airlied: fix warnings] Signed-off-by: Lee, Chun-Yi <jlee@novell.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: MC vram map needs to be >= pci aperture sizeAlex Deucher2010-10-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The vram map in the radeon memory controller needs to be >= the pci aperture size. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=28402 The problematic cards in the above bug have 64 MB of vram, but the pci aperture is 128 MB and the MC vram map was only 64 MB. This can lead to hangs. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: implement display watermark support for evergreenAlex Deucher2010-10-262-1/+449
| | | | | | | | | | | | | | | | | | | | Improper display watermarks can result in underflow to the display controllers which can cause flickering or other artifacts. This patch implements display watermark support and line buffer allocation for evergreen asics. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms/evergreen: add some additional safe regs v2Alex Deucher2010-10-262-1/+9
| | | | | | | | | | | | | | | | | | | | These are needed for enabling dynamic GPR allocation in the shaders in the userspace acceleration drivers. v2: fix typo in reg name Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/r600: fix tiling issues in CS checker.Dave Airlie2010-10-262-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The CS checker had some incorrect alignment requirements for 2D surfaces, this made rendering to mipmap levels that were 2D broken. Also the CB height was being worked out from the BO size, this doesn't work at all when rendering mipmap levels, instead we work out what height userspace wanted from slice max and use that to check it fits inside the BO, however the DDX send the wrong slice max for an unaligned buffer so we have to workaround for that even though its a userspace bug. Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * Merge remote branch 'intel/drm-intel-next' of ../drm-next into drm-core-nextDave Airlie2010-10-2629-1366/+1979
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'intel/drm-intel-next' of ../drm-next: (63 commits) drm/i915: Move gpu_write_list to per-ring drm/i915: Invalidate the to-ring, flush the old-ring when updating domains drm/i915/ringbuffer: Write the value passed in to the tail register agp/intel: Restore valid PTE bit for Sandybridge after bdd3072 drm/i915: Fix flushing regression from 9af90d19f drm/i915/sdvo: Remove unused encoding member i915: enable AVI infoframe for intel_hdmi.c [v4] drm/i915: Fix current fb blocking for page flip drm/i915: IS_IRONLAKE is synonymous with gen == 5 drm/i915: Enable SandyBridge blitter ring drm/i915/ringbuffer: Remove broken intel_fill_struct() drm/i915/ringbuffer: Fix emit batch buffer regression from 8187a2b drm/i915: Copy the updated reloc->presumed_offset back to the user drm/i915: Track objects in global active list (as well as per-ring) drm/i915: Simplify most HAS_BSD() checks drm/i915: cache the last object lookup during pin_and_relocate() drm/i915: Do interrupible mutex lock first to avoid locking for unreference drivers: gpu: drm: i915: Fix a typo. agp/intel: Also add B43.1 to list of supported devices drm/i915: rearrange mutex acquisition for pread ...
| | * drm/i915: Move gpu_write_list to per-ringChris Wilson2010-10-244-26/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... to prevent flush processing of an idle (or even absent) ring. This fixes a regression during suspend from 87acb0a5. Reported-and-tested-by: Alexey Fisher <bug-track@fisher-privat.net> Tested-by: Peter Clifton <pcjc2@cam.ac.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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