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* MIPS: Use ALIGN(x, bytes) instead of __ALIGN_MASK(x, bytes - 1)Matt Turner2010-02-271-3/+3
| | | | | | | | | | | ALIGN(x, bytes) expands to __ALIGN_MASK(x, bytes - 1), so use the one that is most clear. Signed-off-by: Matt Turner <mattst88@gmail.com> To: linux-mips@linux-mips.org Cc: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/999/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Crazy spinlock speed test.David Daney2010-02-273-0/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is just a test program for raw_spinlocks. The main reason I wrote it is to validate my spinlock changes that I sent in a previous patch. To use it enable CONFIG_DEBUG_FS and CONFIG_SPINLOCK_TEST then at run time do: # mount -t debugfs none /sys/kernel/debug/ # cat /sys/kernel/debug/mips/spin_single # cat /sys/kernel/debug/mips/spin_multi On my 600MHz octeon cn5860 (16 CPUs) I get spin_single spin_multi base 106885 247941 spinlock_patch 75194 219465 This shows that for uncontended locks the spinlock patch gives 41% improvement and for contended locks 12% improvement (1/time). Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/969/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Optimize spinlocks.David Daney2010-02-273-81/+67
| | | | | | | | | | | | | | | | | | | | The current locking mechanism uses a ll/sc sequence to release a spinlock. This is slower than a wmb() followed by a store to unlock. The branching forward to .subsection 2 on sc failure slows down the contended case. So we get rid of that part too. Since we are now working on naturally aligned u16 values, we can get rid of a masking operation as the LHU already does the right thing. The ANDI are reversed for better scheduling on multi-issue CPUs On a 12 CPU 750MHz Octeon cn5750 this patch improves ipv4 UDP packet forwarding rates from 3.58*10^6 PPS to 3.99*10^6 PPS, or about 11%. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/937/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: devboard PM needs to save CPLD registers.Manuel Lauss2010-02-271-0/+32
| | | | | | | | | | Save/restore CPLD registers when doing suspend-to-ram; this fixes issues with harddisk and ethernet not working correctly when resuming on DB1200. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/986/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: PowerTV: Eliminate duplicate opcode definition macrosDavid VomLehn2010-02-271-53/+49
| | | | | | | | | | | | Change to different macros for assembler macros since the old names in powertv_setup.c were co-opted for use in asm/asm.h. This broken the build for the powertv platform. This patch introduces new macros based on the new macros in asm.h to take the place of the old macro values. Signed-off-by: David VomLehn <dvomlehn@cisco.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/985/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lemote 2F: Move printks out of port_access_lock.Ralf Baechle2010-02-271-2/+2
| | | | | | No point in protecting them and printks are sloow. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: PNX833x: Convert IRQ controller locks to raw spinlocks.Ralf Baechle2010-02-271-18/+18
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c.David Daney2010-02-271-5/+5
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/973/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Replace rwlocks in irq_chip handlers with raw_spinlocks.David Daney2010-02-271-28/+14
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/972/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Convert octeon_irq_msi_lock to raw spinlock.Ralf Baechle2010-02-271-5/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Remove pointless sample_lock from oprofile code.Ralf Baechle2010-02-271-7/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SNI: Convert sni_rm200_i8259A_lock to raw spinlock.Ralf Baechle2010-02-271-11/+11
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: i8259: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-273-16/+16
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP27: Convert nmi_lock lock to arch spinlock;Ralf Baechle2010-02-271-2/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP27: Remove code obfuscation by enter_panic_mode().Ralf Baechle2010-02-271-3/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: GT641xx: Convert timer lock to raw spinlock.Ralf Baechle2010-02-271-5/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Simplify DMA channel allocation code.Ralf Baechle2010-02-271-55/+56
| | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@googlemail.com>
* MIPS: Yosemite: Convert SMP startup lock to arch spinlock.Ralf Baechle2010-02-271-4/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Remove time_lock.Ralf Baechle2010-02-271-7/+0
| | | | | | | | The sole user is au1xxx_calc_clock() which is only used in early bootup where the is no paralellism thus no race condition to protect against. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@googlemail.com>
* MIPS: DEC: Convert KN01 lock to raw spinlock.Ralf Baechle2010-02-271-5/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Convert timer locks to raw spinlocks.Ralf Baechle2010-02-271-17/+17
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: PowerTV: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-271-3/+3
| | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: David VomLehn <dvomlehn@cisco.com>
* MIPS: Malta: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-271-3/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SB1480: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-271-7/+7
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SB1250: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-271-7/+7
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: GT641xx: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-271-9/+9
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Jazz: Convert irq controller lock to raw spinlock.Ralf Baechle2010-02-271-5/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Make various locks static.Ralf Baechle2010-02-279-9/+9
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Staging: Octeon: Remove /proc/octeon_ethernet_statsDavid Daney2010-02-274-178/+0
| | | | | | | | | | | This file shouldn't be in /proc, so we remove it. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: netdev@vger.kernel.org To: gregkh@suse.de Patchwork: http://patchwork.linux-mips.org/patch/970/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Staging: Octeon: Reformat a bunch of comments.David Daney2010-02-277-71/+44
| | | | | | | | | | | Many of the comments didn't follow kerneldoc guidlines. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: netdev@vger.kernel.org To: gregkh@suse.de Patchwork: http://patchwork.linux-mips.org/patch/971/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Staging: Octeon: Free transmit SKBs in a timely mannerDavid Daney2010-02-276-63/+142
| | | | | | | | | | | | | | | | | | | | | | | | If we wait for the once-per-second cleanup to free transmit SKBs, sockets with small transmit buffer sizes might spend most of their time blocked waiting for the cleanup. Normally we do a cleanup for each transmitted packet. We add a watchdog type timer so that we also schedule a timeout for 150uS after a packet is transmitted. The watchdog is reset for each transmitted packet, so for high packet rates, it never expires. At these high rates, the cleanups are done for each packet so the extra watchdog initiated cleanups are neither needed nor triggered. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: netdev@vger.kernel.org To: gregkh@suse.de Cc: Eric Dumazet <eric.dumazet@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/968/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> This version has spelling and comment changes based on feedback from Eric Dumazet.
* MIPS: Octeon: Do proper acknowledgment of CIU timer interrupts.David Daney2010-02-271-4/+63
| | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: netdev@vger.kernel.org To: gregkh@suse.de Patchwork: http://patchwork.linux-mips.org/patch/967/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Staging: Octeon: Run phy bus accesses on a workqueue.David Daney2010-02-273-63/+109
| | | | | | | | | | | | | When directly accessing a phy, we must acquire the mdio bus lock. To do that we cannot be in interrupt context, so we need to move these operations to a workqueue. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: netdev@vger.kernel.org To: gregkh@suse.de Patchwork: http://patchwork.linux-mips.org/patch/965/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Staging: octeon: remove unneeded includesDavid Daney2010-02-276-6/+0
| | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: netdev@vger.kernel.org To: gregkh@suse.de Patchwork: http://patchwork.linux-mips.org/patch/964/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use generic ucontext.hYoichi Yuasa2010-02-271-21/+1
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/959/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use generic serial.hYoichi Yuasa2010-02-271-22/+1
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/960/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use generic parport.hYoichi Yuasa2010-02-271-15/+1
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/958/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use generic current.hYoichi Yuasa2010-02-271-23/+1
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/957/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUsDavid Daney2010-02-271-0/+3
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Give Octeon+ CPUs their own cputype.David Daney2010-02-273-6/+12
| | | | | | | | | | This allows us to treat them differently at runtime. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/951/ Patchwork: http://patchwork.linux-mips.org/patch/987/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Implement Read Inhibit/eXecute InhibitDavid Daney2010-02-2710-79/+348
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit (XI) bits in the page tables work. The upper two bits of EntryLo{0,1} are RI and XI when the feature is enabled in the PageGrain register. SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to 64-bit systems by continuing to place the RI and XI bits in the top of EntryLo even when EntryLo is 64-bits wide. Because we need to carry the RI and XI bits in the PTE, the layout of the PTE is changed. There is a two instruction overhead in the TLB refill hot path to get the EntryLo bits into the proper position. Also the TLB load exception has to probe the TLB to check if RI or XI caused the exception. Also of note is that the layout of the PTE bits is done at compile and runtime rather than statically. In the 32-bit case this allows for the same number of PFN bits as before the patch as the _PAGE_HUGE is not supported in 32-bit kernels (we have _PAGE_NO_EXEC and _PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE). The patch is tested on Cavium Octeon+, but should also work on 32-bit systems with the Smart-MIPS ASE. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/952/ Patchwork: http://patchwork.linux-mips.org/patch/956/ Patchwork: http://patchwork.linux-mips.org/patch/962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add TLBR and ROTR to uasm.David Daney2010-02-272-2/+11
| | | | | | | | | | The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and ROTR support in uasm. We also add a UASM_i_ROTR macro. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/953/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add accessor functions and bit definitions for c0_PageGrainDavid Daney2010-02-271-0/+11
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/950/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels.David Daney2010-02-271-10/+10
| | | | | | | | | | | 64-bit CPUs have 64-bit c0_entrylo{0,1} registers. We should use the 64-bit dmtc0 instruction to set them. This becomes important if we want to set the RI and XI bits present in some processors. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/954/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove trailing space in messagesFrans Pop2010-02-273-3/+3
| | | | | | | | Signed-off-by: Frans Pop <elendil@planet.nl> To: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/946/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Make the debugging of compressed kernel configurableWu Zhangjin2010-02-272-0/+21
| | | | | | | | | | | | | | This patch adds a new DEBUG_ZBOOT option to allow the users to enable it to debug the compressed kernel support for a new board and this optoin should be disabled to reduce the kernel image size and speed up the kernel booting procedure when the compressed kernel support is stable. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> To: Ralf Baechle <ralf@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/918/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove #if 0 r4k_update_mmu_cache_hwbugDavid Daney2010-02-271-34/+0
| | | | | | | | | | The function is #if 0ed out. There are no other occurrences of its name in the tree. It is safe to remove. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/936/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: TXx9: Remove forced serial console settingYoichi Yuasa2010-02-275-26/+0
| | | | | | | | | | It is not always used, even if it is available. Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/933/ Acked-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: Make ar7_register_devices much more durableAlexander Clouter2010-02-271-66/+81
| | | | | | | | | | [Ralf: Fixed up the rejects and changed all the new printk(KERN_...); to pr_xxx() as suggested by Wu.] Signed-off-by: Alexander Clouter <alex@digriz.org.uk> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/920/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: Fix USB slave mem range typoAlexander Clouter2010-02-271-1/+1
| | | | | | | Signed-off-by: Alexander Clouter <alex@digriz.org.uk> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/919/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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