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* clk: Fix minor errors in of_clk_init() function commentsSylwester Nawrocki2014-03-281-2/+2
| | | | | Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: reverse default clk provider initialization order in of_clk_init()Sylwester Nawrocki2014-03-281-1/+1
| | | | | | | | | | | | | | | This restores the default clocks registration order as parsed from devicetree, i.e. as before commit 1771b10d605d26ccee771a7fb4b08718 "clk: respect the clock dependencies in of_clk_init", for when there is no explicit parent clock dependencies between clock providers specified in the device tree. It prevents regressions (boot failure, division by 0 errors) on imx and exynos platforms. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sirf: update copyright years to 2014Barry Song2014-03-273-3/+6
| | | | | Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mmp: try to use closer one when do round rateChao Xie2014-03-271-3/+7
| | | | | | | | | | | | The orignal code will use the bigger rate between "previous rate" and "current rate" when caculate the rate. In fact, hardware cares about the closest one. So choose the closer rate between "previous rate" and "current rate". Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mmp: fix the wrong calculation formulaChao Xie2014-03-271-5/+5
| | | | | | | | | | | The formula is numerator/denominator = Fin / (Fout * factor) So Fout = Fin * denominator / (numerator * factor). Current clk_factor_round_rate and clk_factor_recalc_rate use wrong formula. This patch will fix them. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mmp: fix wrong mask when calculate denominatorChao Xie2014-03-271-1/+1
| | | | | | | | The code has typo when calculate denominator. It should use den_mask instead of num_mask. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Adds quadfs clock bindingGabriel FERNANDEZ2014-03-251-0/+45
| | | | | Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Adds clockgen-vcc and clockgen-mux clock bindingGabriel FERNANDEZ2014-03-252-0/+89
| | | | | Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Adds clockgen clock bindingGabriel FERNANDEZ2014-03-251-0/+48
| | | | | Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Adds divmux and prediv clock bindingGabriel FERNANDEZ2014-03-253-0/+168
| | | | | Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Support for A9 MUX clocksGabriel FERNANDEZ2014-03-251-0/+19
| | | | | | | | | | | The patch supports the A9-mux clocks used by ClockGenA9 A9-mux clock : Multiplexer inside ClockGenA9. A9 clock can be driven by either PLL or External clock (with an optional divide-by-2). This is implemented as 3-parent clock : PLL, Ext-clk OR Ext-clk/2 Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Support for ClockGenA9/DDR/GPUGabriel FERNANDEZ2014-03-251-0/+139
| | | | | | | | | | | | | | The patch added support for DT registration of ClockGenA9/DDR/GPU ClockgenA9/DDR : It includes c32 type PLL (also in ClockgenA1x), hence only CLK_OF_DECLARE implementation is required. ClockgenGPU : It includes c65 type PLL (also in ClockgenAx), hence only CLK_OF_DECLARE implementation is required. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Support for QUADFS inside ClockGenB/C/D/E/FGabriel FERNANDEZ2014-03-252-1/+1040
| | | | | | | | | | | | | | | The patch supports the 216/432/660 type Quad Frequency Synthesizers used by ClockGenB/C/D/E/F QUADFS clock : It includes support for all 216/432/660 type Quad Frequency Synthesizers : implemented as Fixed Parent / Rate / Gate clock, with clock rate calculated reading H/w settings done at BOOT. QuadFS have 4 outputs : chan0 chan1 chan2 chan3 Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Support for VCC-mux and MUX clocksGabriel FERNANDEZ2014-03-251-0/+272
| | | | | | | | | | | | | | | | | The patch supports the VCC-mux and MUX clocks used by ClockGenC/F VCC-mux clock : Divider-Multiplexer-Gate inside ClockGenC/F It includes support for each channel : 4-parent Multiplexer, Post Divide by 1, 2, 4 or 8, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider, clk_mux, clk_gate and clk_composite (to combine all) MUX clock : 2-parent clock used inside ClockGenC/F. The clock is implemented using generic clocks implemented in the kernel clk_mux. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Support for PLLs inside ClockGenA(s)Gabriel FERNANDEZ2014-03-253-1/+608
| | | | | | | | | | | | | | | The patch supports the c65/c32 type PLLs used by ClockGenA(s) PLL clock : It includes support for all c65/c32 type PLLs inside ClockGenA(s) : implemented as Fixed Parent / Fixed Rate clock, with clock rate calculated reading H/w settings done at BOOT. c65 PLLs have 2 outputs : HS and LS c32 PLLs have 1-4 outputs : ODFx Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Support for DIVMUX and PreDiv ClocksGabriel FERNANDEZ2014-03-253-0/+531
| | | | | | | | | | | | | | | | | | The patch supports the DIVMUX and PreDiv clocks used by ClockGenA(s) DIVMUX clock : Divider-Multiplexer-Gate inside ClockGenA(s) It includes support for each channel : 3-parent Multiplexer, Divider for each Parent, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider and clk_mux. PreDiv clock : Fixed Divider Clock used inside ClockGenA(s) to divide the oscillator clock by factor-of-16. The clock is implemented using generic clocks implemented in the kernel clk_divider. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: support hardware-specific debugfs entriesAlex Elder2014-03-252-0/+12
| | | | | | | | | Add a new clk_ops->debug_init method to allow a clock hardware driver to populate the clock's debugfs directory with entries beyond those common for every clock. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: s2mps11: Use of_get_child_by_nameKrzysztof Kozlowski2014-03-241-1/+1
| | | | | | | | of_find_node_by_name() walks over all nodes and can thus walk outside of the parent node. Use of_get_child_by_name() instead. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: s2mps11: Fix possible NULL pointer dereferenceKrzysztof Kozlowski2014-03-241-1/+1
| | | | | | | | | | If parent device does not have of_node set the s2mps11_clk_parse_dt() returned NULL. This NULL was later passed to of_clk_add_provider() which dereferenced it in pr_debug() call. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: <stable@vger.kernel.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: hisilicon: fix warning from smatchZhangfei Gao2014-03-211-8/+7
| | | | | | | | | drivers/clk/hisilicon/clk-hi3620.c:338 mmc_clk_delay() warn: always true condition '(para >= 0) => (0-u32max >= 0)' Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: shmobile: add CPG driver for rz-platformsWolfram Sang2014-03-213-0/+133
| | | | | Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: turn rate change failed warning into pr_debugSascha Hauer2014-03-201-1/+1
| | | | | | | | | | If a rate change failed it's the opportunity of the caller to handle this. Do not spam the log with a message. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
* MAINTAINERS: use LKML for common clk frameworkMike Turquette2014-03-201-1/+1
| | | | | | | Framework is not ARM specific and used by many architectures. Change ML from LAKML to LKML. Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: respect the clock dependencies in of_clk_initGregory CLEMENT2014-03-201-4/+79
| | | | | | | | | | | | | | | | | | | | | Until now the clock providers were initialized in the order found in the device tree. This led to have the dependencies between the clocks not respected: children clocks could be initialized before their parent clocks. Instead of forcing each platform to manage its own initialization order, this patch adds this work inside the framework itself. Using the data of the device tree the of_clk_init function now delayed the initialization of a clock provider if its parent provider was not ready yet. The strict dependency check (all parents of a given clk must be initialized) was added by Boris BREZILLON Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mpc85xx: Update the driver to align to new clock bindingsTang Yuantian2014-03-201-22/+48
| | | | | | | | | | | | The clock bindings for Freescale CoreNet platform are updated. So, the driver needs to be updated accordingly. The main changes include: - Added a new node to present the input system clock - Changed PLL and MUX's compatible string Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: at91: optimization of the set_rate callbackJean-Jacques Hiblot2014-03-191-30/+8
| | | | | | Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: at91: fix programmable clk irq handlingJean-Jacques Hiblot2014-03-192-93/+89
| | | | | | | | | | The PCKRDY bit is not set until the system clock is enabled. This patch moves the management of the ready status in the system clock driver. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: at91: propagate rate change on system clksBoris BREZILLON2014-03-191-1/+1
| | | | | | | | System clks are just gates, and thus do not provide any rate operations. Authorize clk rate change to be propagated to system clk parents. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: at91: replace prog clk round_rate with determine_rateBoris BREZILLON2014-03-191-28/+28
| | | | | | | | Implement the determine_rate callback to choose the best parent clk that fulfills the requested rate. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Documentation: clk: Add locking documentationLaurent Pinchart2014-03-191-0/+34
| | | | | | | | Briefly document the common clock framework locking scheme from a clock driver point of view. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'clk-hisi' of ↵Mike Turquette2014-03-197-39/+164
|\ | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon updating clock drivers for Hisilicon
| * clk: hisi: remove static variableHaojian Zhuang2014-03-194-42/+72
| | | | | | | | | | | | | | Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * clk: hip04: add clock driverHaojian Zhuang2014-03-194-1/+94
| | | | | | | | | | | | Now only fixed rate clocks are appended into the clock driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * clk: hisi: assign missing clk to tableHaojian Zhuang2014-03-191-0/+2
| | | | | | | | | | | | The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* | clk: sunxi: fix thinko in commentEmilio López2014-03-191-1/+1
| | | | | | | | | | | | | | | | This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: sunxi: fix some calculationsEmilio López2014-03-191-3/+3
| | | | | | | | | | | | | | | | | | | | Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: sunxi: fix A20 PLL4 calculationEmilio López2014-03-191-0/+7
| | | | | | | | | | | | | | | | | | Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge tag 'sunxi-clk-for-3.15' of https://bitbucket.org/emiliolopez/linux ↵Mike Turquette2014-03-192-48/+344
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into clk-next-sunxi Allwinner sunXi SoCs clock changes This adds support for the new, more correct clock node naming and gets the A10 compatibles in line with the rest of the other SoCs. It also adds support for the USB, GMAC and A31's PLL6 clocks. Some of these changes also require DT modifications that will be merged via arm-soc.
| * | clk: sunxi: Add new clock compatiblesMaxime Ripard2014-02-182-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A10 compatibles were following a slightly different compatible patterns than the rest of the SoCs for historical reasons. Add compatibles matching the other pattern to the clock driver for consistency, and keep the older one for backward compatibility. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai2014-02-182-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A20/A31 clock module controls the transmit clock source and interface type of the GMAC ethernet controller. Model this as a single clock for GMAC drivers to use. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: Add support for PLL6 on the A31Maxime Ripard2014-02-182-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | The A31 has a slightly different PLL6 clock. Add support for this new clock in our driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: Add USB clock register defintionsRoman Byshko2014-02-182-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add register definitions for the usb-clk register found on sun4i, sun5i and sun7i SoCs. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: Add support for USB clock-register reset bitsHans de Goede2014-02-181-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usb-clk register is special in that it not only contains clk gate bits, but also has a few reset bits. This commit adds support for this by allowing gates type sunxi clks to also register a reset controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: get divs parent clock name from parent factor clockChen-Yu Tsai2014-02-031-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Divs clocks consist of a parent factor clock with multiple outputs, and seperate clocks for each output. Get the name of the parent clock from the parent factor clock, instead of the DT node name. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: add names for pll5, pll6 parent clocks to factors_dataChen-Yu Tsai2014-02-031-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some factor clocks, such as the parent clock of pll5 and pll6, have multiple output names. Add the corresponding names to factors_data tied to compatible string. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: update clock-output-names dt binding documentationChen-Yu Tsai2014-02-031-6/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | clock-output-names is now required for most of sunxi clock nodes, to provide the name of the corresponding clock. Add the new requirements, exceptions, as well as examples. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: add clock-output-names dt property supportChen-Yu Tsai2014-02-031-0/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | sunxi clock drivers use dt node name as clock name, but clock nodes should be named clk@X, so the names would be the same. Let the drivers read clock names from dt clock-output-names property. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* | clk: socfpga: Fix section mismatch warningDinh Nguyen2014-03-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_pll_init() The variable socfpga_child_clocks references the function __init socfpga_pll_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_periph_init() The variable socfpga_child_clocks references the function __init socfpga_periph_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_gate_init() The variable socfpga_child_clocks references the function __init socfpga_gate_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Reported-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge tag 'clk-mvebu-3xx-3.15-2' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette2014-03-192-2/+28
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next-mvebu clock: mvebu new SoC changes for v3.15 (incremental pull #2) - mvebu (Armada 375) - fix ratio register offest - mvebu (Armada 380) - expand core divider clock driver to support 380 SoC (enables nand support)
| * | clk: mvebu: Update binding documentation for the core divider clockEzequiel Garcia2014-03-141-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Core Divider clock support two new compatible strings for Armada 375 and Armada 380 SoCs. Add the compatible strings to the documentation. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-7-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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