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* pinctrl: sh-pfc: r8a7791: Add I2C pinsValentine Barshak2014-01-071-0/+196
| | | | | | | | This adds I2C[0-4] pinmux support to R8A7791 SoC. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7791: Add VIN pinsValentine Barshak2014-01-071-0/+360
| | | | | | | | | | | This adds VIN[0-2] pinmux support to r8a7791 SoC. VIN1 B mirror is also added along with the primary configuration since it's the only one that provides access to all 24 data bits on VIN1. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7791: Group USB PWEN and OVC pins togetherValentine Barshak2014-01-071-28/+12
| | | | | | | | | | This groups USB PWEN and OVC pins together on R8A7791 SoC, the same way it's done on R8A7790, since both are needed for a USB device. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7790: Fix vsync value in the vin3_sync_mux arrayValentine Barshak2014-01-071-1/+1
| | | | | | | | This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/). Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: ARM: Constify pins and cfg_regs arraysLaurent Pinchart2013-12-208-11/+11
| | | | | | | The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: sh: Constify pins and cfg_regs arraysLaurent Pinchart2013-12-2012-12/+12
| | | | | | | The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: Constify IRQ GPIOs arraysLaurent Pinchart2013-12-202-3/+3
| | | | | | | The arrays are never modified, make them const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: Constify enum_ids and var_field_width compound literalsLaurent Pinchart2013-12-201-4/+5
| | | | | | | | | The enum_ids and var_field_width fields of struct pinmux_data_reg and pinmux_cfg_reg are initialized using compound literals. Cast them to const to store them in .rodata. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: msm: Fix set gpio settingAxel Lin2013-12-201-2/+10
| | | | | | | | Set g->out_bit bit for gpio output high, clear g->out_bit bit for gpio output low. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: at91: replace clk_prepare + clk_enable by clk_prepare_enableBoris BREZILLON2013-12-161-4/+2
| | | | | | | | | Replace the clk_prepare and clk_enable calls by a single clk_prepare_enable call. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: at91: fix clk_unprepare and clk_disable orderBoris BREZILLON2013-12-161-5/+3
| | | | | | | | | | clk_unprepare shall be called before clk_disable. Fix the issue by replacing the clk_unprepare and clk_disable calls by a single clk_disable_unprepare call. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Adds slew-rate, input-enable/disableSherman Yin2013-12-163-0/+11
| | | | | | | | This commit adds slew-rate and input-enable/disable support for pinconf -generic. Signed-off-by: Sherman Yin <syin@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl-msm: Rename compatible to be more specificBjorn Andersson2013-12-162-3/+3
| | | | | | | | Use the more specific form 8974 for the compatible to reduce the risk of future mishaps. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl-msm: Remove separate allocation of bitmapsBjorn Andersson2013-12-161-27/+5
| | | | | | | | Make the bitmaps part of the msm_pinctrl allocation instead of separately allocating them. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl-msm: Tidy up error handlingBjorn Andersson2013-12-161-50/+26
| | | | | Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl-msm: Fix spelling misstakes and missing constsBjorn Andersson2013-12-162-9/+9
| | | | | Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: msm: Update Kconfig for PINCTRL_MSM8X74Bjorn Andersson2013-12-161-3/+6
| | | | | | | | | | | | Add GPIOLIB and OF as dependencies for PINCTRL_MSM8X74, to fix build errors from i386-randconfig. Also add help text and make the entries tristate, while touching these entries. Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> [Rebased on top of pin control development branch] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinconf: remove warning: unused variable 'ops'Alexandre Belloni2013-12-131-2/+0
| | | | | Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: at91: implement at91_pinconf_dbg_showAlexandre Belloni2013-12-131-0/+25
| | | | | | | | | This allows to get the pin configuration by using debugfs. On my system: # cat /sys/kernel/debug/pinctrl/pinctrl.3/pinconf-pins Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: add pinmux controller driver for Tegra124Ashwini Ghuge2013-12-123-0/+3142
| | | | | | | | | | | | | | | | | | | | | | | | | This adds a driver for the Tegra124 pinmux, and required parameterization data for Tegra124. The driver uses the common Tegra pincontrol driver utility functions to implement the majority of the driver. This driver is not compatible with the earlier NVIDIA's SoCs, hence add new compatibile as "nvidia,tegra124-pinmux". Originally written by Ashwini Gguhe. Thierry: - Cleanups in patches. ldewangan: - Fix some entries for groups. - Fix MUX enums and group sequence. Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> CC: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Add devicetree binding document for Tegra124Laxman Dewangan2013-12-121-0/+144
| | | | | | | | | | | | | | | | | This device tree binding document describes the Tegra124 pincontrol DT bindings. This document lists all valid properties, names, mux options of Tegra124 pins. Changes from V1: - Referred the dt-binding header file on describing the nodes. Changes from V2: - Rewording reg properties. - drop drv_type as it is not applicable. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: Support GPIO to IRQ mapping specified IRQ resourcesLaurent Pinchart2013-12-124-17/+82
| | | | | | | | | | | | | | | | | | On non-DT platforms IRQ controllers associated with the GPIOs have a fixed IRQ base value known at compile time. The sh-pfc driver translates GPIO number to IRQ numbers using a hardcoded table. This mechanism breaks on DT platforms, as the IRQ base values are dynamic in that case. Fix this by specifying IRQs associated with GPIOs in IRQ resources, populated automatically from the device tree. When IRQ resources are specified the driver requires one IRQ resource per GPIO able to generate an interrupt, and uses the translation table to compute the IRQ resource offset instead of the IRQ number. Cc: devicetree@vger.kernel.org Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: Rename sh_pfc window field to windowsLaurent Pinchart2013-12-127-20/+21
| | | | | | | | There's more than one window, name the field windows. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: sh73a0: Sort IRQ entries by IRQ numberLaurent Pinchart2013-12-121-24/+23
| | | | | | | | | This makes catching duplicate entries easier. Merge the two IRQ9 entries found after sorting. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: sh73a0: Add missing IRQ15Laurent Pinchart2013-12-121-0/+1
| | | | | | | | The external IRQ15 input multiplexed on GPIO 0 is missing. Add it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: Terminate gpios array by -1Laurent Pinchart2013-12-122-4/+4
| | | | | | | | | 0 is a valid GPIO value, use -1 to terminate the gpios array in IRQ lists. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: Turn unsigned indices into unsigned intLaurent Pinchart2013-12-122-5/+5
| | | | | | | | Some indices take positive values only, make them unsigned. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinconf: remove checks on ops->pin_config_getAlexandre Belloni2013-12-121-16/+4
| | | | | | | | | | | | | | | | | | | | | ops->pin_config_get() is only used in one specific path that will only be taken for generic pinconf drivers (ops->is_generic == true) when dumping the pinconf by using debugfs. By removing the check in pinconf_check_ops(), let's stop pressuring people to write a pin_config_get() function that will never be used and so will probably never be tested. Removing the check in pinconf_pins_show() allows driver to not implement pin_config_get() but still get a dump of the pinconf in debugfs by implementing pin_config_dbg_show(). Finally, not implementing pin_config_get() now results in returning -ENOTSUPP instead of -EINVAL. While this doesn't have any real impact for now, this feels more right. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: at91: initialize config parameter to 0Alexandre Belloni2013-12-121-1/+2
| | | | | | | | When passing a not initialized config parameter, at91_pinconf_get() would return a bogus value. Fix that by initializing it to zero before using it. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: at91: correct a few typosAlexandre Belloni2013-12-121-3/+3
| | | | | Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'pinmux/next/pfc' of git://linuxtv.org/pinchartl/fbdev into develLinus Walleij2013-12-117-110/+705
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| * pinctrl: sh-pfc: pfc-r8a7790: Add VIN2 and VIN3 pinsValentine Barshak2013-12-101-0/+168
| | | | | | | | | | | | | | | | | | There are VIN2 and VIN3 channels available on the R8A7790 SoC. VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit. Add both here, covering all possible data pin configurations. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: pfc-r8a7790: Add missing VIN1 pinsValentine Barshak2013-12-101-8/+104
| | | | | | | | | | | | | | | | | | Both VIN0 and VIN1 channels support identical input interfaces. Add missing VIN1 pins here and organize them in the same pin groups as VIN0. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: pfc-r8a7790: Reorganize VIN0 data pinsValentine Barshak2013-12-101-30/+95
| | | | | | | | | | | | | | | | | | | | | | | | This reorganizes and renames VIN0 data pin groups to cover all possible configurations. There's total of eight data pin groups, one per each configuration. Most of the groups share the same pin/mux array. Only the 18-bit configuration needs a separate pin/mux array since in combines interleaved data pins. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: pfc-r8a7790: Group VIN0 HSYNC and VSYNC togetherValentine Barshak2013-12-101-12/+6
| | | | | | | | | | | | | | | | This groups VIN0 HSYNC and VSYNC pins together since one cannot be used without another. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: pfc-r8a7790: Rename VIN pin groupsValentine Barshak2013-12-101-16/+16
| | | | | | | | | | | | | | | | This drops superfluous "signal" word from the pin group names and renames data_enable group to clkenb as in the h/w manual. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * sh-pfc: r8a7791: Fix msiof groups to follow GROUPTakashi Yoshii2013-12-101-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | SH_PFC_PIN_GROUP(), pins[], mux[], defines clk, sync, ss1, ss2, rx, tx But, msiof?_groups[] defines clk, ctrl, data Fix msiof[012]_groups members to be consistent to PIN_GROUP. Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
| * sh-pfc: r8a7790: Add Audio pin supportKuninori Morimoto2013-12-101-0/+68
| | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
| * sh-pfc: r8a7790: Add SSI pin supportKuninori Morimoto2013-12-101-0/+239
| | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
| * sh-pfc: Share common PORTCR macro definitionLaurent Pinchart2013-12-105-45/+1
| | | | | | | | | | | | | | | | The macro is defined identically in four different locations. Share it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: make the MSM SoC driver depend on OFLinus Walleij2013-12-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We had a compilation failure on x86_64 due to missing OF support as this was an implicit dependency. Add an explicit dependency on OF and OF_IRQ on the SoC driver. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- ChangeLog v2->v3: - Total failure with older approaches: what we need to do is have the *SoC subdriver* depend on OF and OF_IRQ. This is because the placeholder bool PINCTRL_MSM cannot cascade its dependencies when a subdriver selects it, Kconfig is smart but not that smart. ChangeLog v1->v2: - OK so "depends on OF" did not work here let's try to simply select OF and OF_IRQ for this then? It's one of those "warning: (PINCTRL_MSM8X74) selects PINCTRL_MSM which has unmet direct dependencies (PINCTRL && OF)" that I simply cannot find my way out of :-/
* | pinctrl: make the MSM SoC driver depend on OFLinus Walleij2013-12-111-0/+1
|/ | | | | | | | | We had a compilation failure on x86_64 due to missing OF support as this was an implicit dependency. Add an explicit dependency on OF and OF_IRQ on the SoC driver. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: baytrail: lock IRQs when starting themLinus Walleij2013-12-091-0/+22
| | | | | | | | | | | This uses the new API for tagging GPIO lines as in use by IRQs. This enforces a few semantic checks on how the underlying GPIO line is used. Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Mathias Nyman <mathias.nyman@linux.intel.com> Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add documentation for pinctrl-msm8x74Bjorn Andersson2013-12-061-0/+92
| | | | | | | This adds initial documentation for the pinctrl-msm8x74 driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add msm8x74 configurationBjorn Andersson2013-12-063-0/+641
| | | | | | | | Add initial definition of parameters for pinctrl-msm for the msm8x74 platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add Qualcomm TLMM driverBjorn Andersson2013-12-064-0/+1157
| | | | | | | | This adds a pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl-baytrail: show pin label with the reset of the gpio debug dataMathias Nyman2013-12-031-1/+7
| | | | | | | | | The default gpiolib debug output shows pin labels. We want baytrail custom debug output to have the same functionality. Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: provide documentation pointerLinus Walleij2013-12-031-2/+4
| | | | | | | | | The PIN_CONFIG_OUTPUT parameter is really tricky to understand and needs an explicit pointer to the documentation. Cc: Tomasz Figa <t.figa@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinctrl-imx: add imx25 pinctrl driverDenis Carikli2013-11-254-0/+384
| | | | | | | | | | | | | | | | | | | | | | This is mostly cut and paste from the imx35 pinctrl driver. The data was generated using sed and awk on arch/arm/plat-mxc/include/mach/iomux-mx25.h. Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: Russell King <linux@arm.linux.org.uk> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Eric Bénard <eric@eukrea.com> Signed-off-by: Denis Carikli <denis@eukrea.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: imx1-core populate subdevicesMarkus Pargmann2013-11-252-0/+29
| | | | | | | | Support gpio devicetree subnodes to allow a more detailed DT hardware description. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 17:51:48 +0100