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* Merge branch 'pci/host/qcom'Bjorn Helgaas2018-06-061-1/+1
|\ | | | | | | | | * pci/host/qcom: PCI: qcom: Include gpio/consumer.h
| * PCI: qcom: Include gpio/consumer.hArnd Bergmann2018-06-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_GPIOLIB is disabled, we run into a build failure: drivers/pci/dwc/pcie-qcom.c: In function 'qcom_pcie_probe': drivers/pci/dwc/pcie-qcom.c:1223:16: error: implicit declaration of function 'devm_gpiod_get_optional'; did you mean 'devm_regulator_get_optional'? [-Werror=implicit-function-declaration] pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW); Including gpio/consumer.h directly is the correct fix. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* | Merge branch 'pci/host/mobiveil'Bjorn Helgaas2018-06-064-0/+947
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add Mobiveil PCIe host controller driver (Subrahmanya Lingappa) - add Mobiveil MSI support (Subrahmanya Lingappa) * pci/host/mobiveil: PCI: mobiveil: Add MSI support PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver DT bindings
| * | PCI: mobiveil: Add MSI supportSubrahmanya Lingappa2018-06-041-4/+202
| | | | | | | | | | | | | | | | | | | | | | | | Implement MSI support for Mobiveil PCIe Host Bridge IP device driver. Signed-off-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Marc Zyngier <marc.zyngier@arm.com>
| * | PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driverSubrahmanya Lingappa2018-06-041-0/+669
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for Mobiveil AXI PCIe Host Bridge Soft IP - GPEX 4.0, a PCIe gen4 IP. This IP has upto 8 outbound and inbound windows for the address translation. Signed-off-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> [bhelgaas: fold in mobiveil_pcie_of_match[] NULL termination from Wei Yongjun <weiyongjun1@huawei.com>] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Marc Zyngier <marc.zyngier@arm.com>
| * | PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver DT bindingsSubrahmanya Lingappa2018-05-303-0/+81
| |/ | | | | | | | | | | | | | | | | Add DT bindings for the Mobiveil PCIe Host Bridge IP driver and update the vendor prefixes file. Signed-off-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
* | Merge branch 'lorenzo/pci/mediatek'Bjorn Helgaas2018-06-063-93/+144
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - implement Mediatek chained IRQ handling (Honghui Zhang) - fix vendor ID & class type for Mediatek MT7622 (Honghui Zhang) * lorenzo/pci/mediatek: PCI: mediatek: Implement chained IRQ handling setup PCI: mediatek: Set up vendor ID and class type for MT7622 # Conflicts: # drivers/pci/host/Kconfig
| * | PCI: mediatek: Implement chained IRQ handling setupHonghui Zhang2018-05-212-91/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement irq_chip based solution for IRQs management in order to comply with IRQ framework. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
| * | PCI: mediatek: Set up vendor ID and class type for MT7622Honghui Zhang2018-05-042-3/+29
| |/ | | | | | | | | | | | | | | | | MT7622's hardware default value of vendor ID and class type is not correct, fix that by setup the correct values before linkup with Endpoint. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
* | Merge branch 'lorenzo/pci/hv'Bjorn Helgaas2018-06-061-91/+71
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - fix Hyper-V bus registration failure caused by domain/serial number confusion (Sridhar Pitchai) - improve Hyper-V refcounting and coding style (Stephen Hemminger) - avoid potential Hyper-V hang waiting for a response that will never come (Dexuan Cui) * lorenzo/pci/hv: PCI: hv: Do not wait forever on a device that has disappeared PCI: hv: Use list_for_each_entry() PCI: hv: Convert remove_lock to refcount PCI: hv: Remove unused reason for refcount handler PCI: hv: Make sure the bus domain is really unique
| * | PCI: hv: Do not wait forever on a device that has disappearedDexuan Cui2018-05-251-12/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before the guest finishes the device initialization, the device can be removed anytime by the host, and after that the host won't respond to the guest's request, so the guest should be prepared to handle this case. Add a polling mechanism to detect device presence. Signed-off-by: Dexuan Cui <decui@microsoft.com> [lorenzo.pieralisi@arm.com: edited commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Haiyang Zhang <haiyangz@microsoft.com> Cc: Stephen Hemminger <sthemmin@microsoft.com> Cc: K. Y. Srinivasan <kys@microsoft.com>
| * | PCI: hv: Use list_for_each_entry()Stephen Hemminger2018-05-241-20/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are several places where list_for_each_entry() could be used to simplify the code. Signed-off-by: Stephen Hemminger <sthemmin@microsoft.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: hv: Convert remove_lock to refcountStephen Hemminger2018-05-241-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use refcount instead of atomic for the reference counting on bus. Refcount is safer because it handles overflow correctly. Signed-off-by: Stephen Hemminger <sthemmin@microsoft.com> [lorenzo.pieralisi@arm.com: updated commit subject] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: hv: Remove unused reason for refcount handlerStephen Hemminger2018-05-241-44/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The get/put functions were taking a reason code. This appears to be a debug infrastructure that is no longer used. Move the functions to start of file to eliminate need for forward declaration. Forward declarations are discouraged on Linux. Signed-off-by: Stephen Hemminger <sthemmin@microsoft.com> [lorenzo.pieralisi@arm.com: updated commit subject] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: hv: Make sure the bus domain is really uniqueSridhar Pitchai2018-05-021-11/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When Linux runs as a guest VM in Hyper-V and Hyper-V adds the virtual PCI bus to the guest, Hyper-V always provides unique PCI domain. commit 4a9b0933bdfc ("PCI: hv: Use device serial number as PCI domain") overrode unique domain with the serial number of the first device added to the virtual PCI bus. The reason for that patch was to have a consistent and short name for the device, but Hyper-V doesn't provide unique serial numbers. Using non-unique serial numbers as domain IDs leads to duplicate device addresses, which causes PCI bus registration to fail. commit 0c195567a8f6 ("netvsc: transparent VF management") avoids the need for commit 4a9b0933bdfc ("PCI: hv: Use device serial number as PCI domain"). When scripts were used to configure VF devices, the name of the VF needed to be consistent and short, but with commit 0c195567a8f6 ("netvsc: transparent VF management") all the setup is done in the kernel, and we do not need to maintain consistent name. Revert commit 4a9b0933bdfc ("PCI: hv: Use device serial number as PCI domain") so we can reliably support multiple devices being assigned to a guest. Tag the patch for stable kernels containing commit 0c195567a8f6 ("netvsc: transparent VF management"). Fixes: 4a9b0933bdfc ("PCI: hv: Use device serial number as PCI domain") Signed-off-by: Sridhar Pitchai <sridhar.pitchai@microsoft.com> [lorenzo.pieralisi@arm.com: trimmed commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: stable@vger.kernel.org # v4.14+ Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'lorenzo/pci/host/misc'Bjorn Helgaas2018-06-063-32/+30
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - update Layerscape maintainer email addresses (Minghuan Lian) - add COMPILE_TEST to improve build test coverage (Rob Herring) * lorenzo/pci/host/misc: MAINTAINERS: Update Layerscape PCIe driver maintainers list PCI: Improve host drivers compile test coverage # Conflicts: # drivers/pci/dwc/Kconfig
| * | MAINTAINERS: Update Layerscape PCIe driver maintainers listMinghuan Lian2018-05-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Change Layerscape PCIe driver maintainers' email address from freescale to nxp. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Roy Zang <roy.zang@nxp.com>
| * | PCI: Improve host drivers compile test coverageRob Herring2018-05-012-29/+26
| |/ | | | | | | | | | | | | | | | | | | | | | | Add COMPILE_TEST on driver config options with it. Some ARM drivers still have arch dependencies, so we have to keep those dependent on ARM. Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> [lorenzo.pieralisi@arm.com: rebased, updated log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* | Merge branch 'lorenzo/pci/endpoint'Bjorn Helgaas2018-06-064-32/+51
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - use usleep() instead of mdelay() in endpoint test (Jia-Ju Bai) - add configfs entries for pci_epf_driver device IDs (Kishon Vijay Abraham I) - clean up pci_endpoint_test driver (Gustavo Pimentel) * lorenzo/pci/endpoint: PCI: endpoint: Create configfs entry for each pci_epf_device_id table entry misc: pci_endpoint_test: Use pci_irq_vector function PCI: endpoint: functions/pci-epf-test: Replace lower into upper case characters misc: pci_endpoint_test: Replace lower into upper case characters PCI: endpoint: Replace mdelay with usleep_range() in pci_epf_test_write()
| * | PCI: endpoint: Create configfs entry for each pci_epf_device_id table entryKishon Vijay Abraham I2018-05-182-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to be able to provide correct driver_data for pci_epf device, a separate configfs entry for each pci_epf_device_id table entry in pci_epf_driver is required. Add support to create configfs entry for each pci_epf_device_id table entry here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
| * | misc: pci_endpoint_test: Use pci_irq_vector functionGustavo Pimentel2018-05-151-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace "pdev->irq + index" operation by the pci_irq_vector() call, that converts from device vector to Linux IRQ. Suggested-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: endpoint: functions/pci-epf-test: Replace lower into upper case charactersGustavo Pimentel2018-05-151-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | Replace all initial lower case character into upper case in comments and debug printks. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | misc: pci_endpoint_test: Replace lower into upper case charactersGustavo Pimentel2018-05-151-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | Replace all initial lower case character into upper case in comments and debug printks. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: endpoint: Replace mdelay with usleep_range() in pci_epf_test_write()Jia-Ju Bai2018-05-081-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci_epf_test_write() is never called in atomic context. The call chain ending up at pci_epf_test_write() is: [1] pci_epf_test_write() <- pci_epf_test_cmd_handler() pci_epf_test_cmd_handler() is set as a parameter of INIT_DELAYED_WORK() in pci_epf_test_probe(). This function is not called in atomic context. Despite never getting called from atomic context, pci_epf_test_write() calls mdelay() to busy wait. This is not necessary and can be replaced with usleep_range() to avoid busy waiting. Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
* | Merge branch 'lorenzo/pci/dwc-fixes'Bjorn Helgaas2018-06-060-0/+0
|\ \ | | | | | | | | | | | | | | | | | | - fix DesignWare enumeration below bridges (Koen Vandeputte) * lorenzo/pci/dwc-fixes: PCI: dwc: Fix enumeration end when reaching root subordinate
| * | PCI: dwc: Fix enumeration end when reaching root subordinateKoen Vandeputte2018-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The subordinate value indicates the highest bus number which can be reached downstream though a certain device. Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in parent") ensures that downstream devices cannot assign busnumbers higher than the upstream device subordinate number, which was indeed illogical. By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a value of 0x01. Due to this combined with above commit, enumeration stops digging deeper downstream as soon as bus num 0x01 has been assigned, which is always the case for a bridge device. This results in all devices behind a bridge bus to remain undetected, as these would be connected to bus 0x02 or higher. Fix this by initializing the RC to a subordinate value of 0xff, which is not altering hardware behaviour in any way, but informs probing function pci_scan_bridge() later on which reads this value back from register. Following nasty errors during boot are also fixed by this: [ 0.459145] pci_bus 0000:02: busn_res: can not insert [bus 02-ff] under [bus 01] (conflicts with (null) [bus 01]) ... [ 0.464515] pci_bus 0000:03: [bus 03] partially hidden behind bridge 0000:01 [bus 01] ... [ 0.464892] pci_bus 0000:04: [bus 04] partially hidden behind bridge 0000:01 [bus 01] ... [ 0.466488] pci_bus 0000:05: [bus 05] partially hidden behind bridge 0000:01 [bus 01] [ 0.466506] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 05 [ 0.466517] pci_bus 0000:02: busn_res: can not insert [bus 02-05] under [bus 01] (conflicts with (null) [bus 01]) [ 0.466534] pci_bus 0000:02: [bus 02-05] partially hidden behind bridge 0000:01 [bus 01] Fixes: a20c7f36bd3d ("PCI: Do not allocate more buses than available in parent") Tested-by: Niklas Cassel <niklas.cassel@axis.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Cc: <stable@vger.kernel.org> # 4.15 Cc: Binghui Wang <wangbinghui@hisilicon.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Jianguo Sun <sunjianguo1@huawei.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Minghuan Lian <minghuan.Lian@freescale.com> Cc: Mingkai Hu <mingkai.hu@freescale.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Roy Zang <tie-fei.zang@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Xiaowei Song <songxiaowei@hisilicon.com> Cc: Zhou Wang <wangzhou1@hisilicon.com>
* | | Merge branch 'lorenzo/pci/dwc'Bjorn Helgaas2018-06-0632-141/+371
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - reduce Keystone "link already up" log level (Fabio Estevam) - move private DT functions to drivers/pci/ (Rob Herring) - factor out dwc CONFIG_PCI Kconfig dependencies (Rob Herring) - add DesignWare support to the endpoint test driver (Gustavo Pimentel) - add DesignWare support for endpoint mode (Gustavo Pimentel) - use devm_ioremap_resource() instead of devm_ioremap() in dra7xx and artpec6 (Gustavo Pimentel) - fix Qualcomm bitwise NOT issue (Dan Carpenter) - add Qualcomm runtime PM support (Srinivas Kandagatla) * lorenzo/pci/dwc: PCI: qcom: add runtime pm support to pcie_port PCI: qcom: Fix a bitwise vs logical NOT typo PCI: dwc: dra7xx: Use devm_ioremap_resource() instead of devm_ioremap() PCI: dwc: artpec6: Use devm_ioremap_resource() instead of devm_ioremap() misc: pci_endpoint_test: Add DesignWare EP entry dt-bindings: PCI: designware: Add support for EP in DesignWare driver PCI: dwc: Add support for EP mode dt-bindings: PCI: designware: Example update PCI: Move private DT related functions into private header PCI: dwc: Move CONFIG_PCI depends to menu PCI: dwc: Replace magic number by defines PCI: dwc: Small computation improvement PCI: dwc: Replace lower into upper case characters PCI: dwc: Define maximum number of vectors PCI: imx6: Remove space before tabs PCI: keystone: Do not treat link up message as error # Conflicts: # include/linux/of_pci.h
| * | | PCI: qcom: add runtime pm support to pcie_portSrinivas Kandagatla2018-05-231-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is required when the pcie controller sits on a bus with its own power domain and clocks which are controlled via a bus driver like simple pm bus. As these bus driver have runtime pm enabled, it makes sense to update the usage counter so that the runtime pm does not suspend the clks or power domain associated with the bus driver. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Vinod Koul <vkoul@kernel.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
| * | | PCI: qcom: Fix a bitwise vs logical NOT typoDan Carpenter2018-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a typo that accidentally sets "val" to zero when we intended just to clear BIT(0). Fixes: 90d52d57ccac ("PCI: qcom: Add support for IPQ4019 PCIe controller") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by: John Crispin <john@phrozen.org>
| * | | PCI: dwc: dra7xx: Use devm_ioremap_resource() instead of devm_ioremap()Gustavo Pimentel2018-05-151-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the use of devm_ioremap() with devm_ioremap_resource() as reported and discussed in the mailing list thread provided. Link: https://lkml.kernel.org/r/20180120001645.GA21343@lenoch Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | | PCI: dwc: artpec6: Use devm_ioremap_resource() instead of devm_ioremap()Gustavo Pimentel2018-05-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the use of devm_ioremap() with devm_ioremap_resource() as reported and discussed in the mailing list thread link. Link: https://lkml.kernel.org/r/20180120001645.GA21343@lenoch Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
| * | | misc: pci_endpoint_test: Add DesignWare EP entryGustavo Pimentel2018-05-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the DesignWare EP device ID entry to pci_endpoint_test driver table. Allow the device to be recognized and handled by the pci_endpoint_test driver. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | | dt-bindings: PCI: designware: Add support for EP in DesignWare driverGustavo Pimentel2018-05-151-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree binding documentation for the EP in PCIe DesignWare driver. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
| * | | PCI: dwc: Add support for EP modeGustavo Pimentel2018-05-155-18/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe controller dual mode is capable of operating in Root Complex (RC) mode as well as EP mode by configuration option. Add EP support to the DesignWare driver on top of RC mode support. Add new property on pci_epc structure which allow to configure pci_epf_test driver accordingly to the controller specific requirements. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | | dt-bindings: PCI: designware: Example updateGustavo Pimentel2018-05-151-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace "ctrlreg" reg-name by "dbi" to be coherent with similar drivers, however it still be compatible with any previous DT that uses the old reg-name. Replace the PCIe base address example by a real PCIe base address in use. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
| * | | PCI: Move private DT related functions into private headerRob Herring2018-05-1418-34/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The functions in linux/of_pci.h are primarily used by host bridge drivers, so they can be private to drivers/pci/. The remaining functions are still used mostly in host bridge drivers that still live in arch specific code. Hopefully someday, those will get moved into drivers/pci as well. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jingoo Han <jingoohan1@gmail.com>
| * | | PCI: dwc: Move CONFIG_PCI depends to menuRob Herring2018-05-141-14/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no need for every config option to explicitly depend on CONFIG_PCI, so move it out of individual option to the menu option. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jingoo Han <jingoohan1@gmail.com>
| * | | PCI: dwc: Replace magic number by definesGustavo Pimentel2018-05-142-14/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace magic numbers by a self-explained define to ease human comprehension. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
| * | | PCI: dwc: Small computation improvementGustavo Pimentel2018-05-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace a division by 2 operation for a right shift rotation of 1 bit. Probably any recent and decent compiler does this kind of substitution in order to improve code performance. Nevertheless it's a coding good practice whenever there is a division / multiplication by multiple of 2 to replace it by the equivalent operation in this case, the shift rotation. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
| * | | PCI: dwc: Replace lower into upper case charactersGustavo Pimentel2018-05-143-35/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace of all initial lowercase character in comments and debug messages to uppercase to maintain coherence. Fix messages coherence within the DesignWare driver. Fix code style on dw_pcie_irq_domain_free() function. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
| * | | PCI: dwc: Define maximum number of vectorsGustavo Pimentel2018-05-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a callback to define the maximum number of vectors used by the RC. Since this is a parameter associated to each SoC IP setting, makes sense to be configurable and easily visible to future modifications. Set DesignWare driver vectors number maximum to 256. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Jingoo Han <jingoohan1@gmail.com>
| * | | PCI: imx6: Remove space before tabsFabio Estevam2018-05-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove space before tabs to fix the following checkpatch warning: WARNING: please, no space before tabs +^Icase IMX6QP: ^I^I/* FALLTHROUGH */$ Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | | PCI: keystone: Do not treat link up message as errorFabio Estevam2018-05-141-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | The "Link already up" message does not indicate any error, so change it to dev_info() level instead. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com>
* | | Merge branch 'lorenzo/pci/armada8k'Bjorn Helgaas2018-06-062-5/+21
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | - enable register clock for Armada 7K/8K (Gregory CLEMENT) * lorenzo/pci/armada8k: PCI: armada8k: Fix clock resource by adding a register clock PCI: armada8k: Remove useless test before clk_disable_unprepare()
| * | | PCI: armada8k: Fix clock resource by adding a register clockGregory CLEMENT2018-03-082-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Armada 7K/8K we need to explicitly enable the register clock. This clock is optional because not all the SoCs using this IP need it but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updated accordingly. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | | PCI: armada8k: Remove useless test before clk_disable_unprepare()Gregory CLEMENT2018-03-081-2/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | clk_disable_unprepare() already checks that the clock pointer is valid. No need to test it before calling it. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* | | Merge branch 'pci/virtualization'Bjorn Helgaas2018-06-0614-54/+159
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add generic enable function for simple SR-IOV hardware (Alexander Duyck) - use generic SR-IOV enable for ena, nvme (Alexander Duyck) - add ACS quirk for Intel 7th & 8th Gen mobile (Alex Williamson) - add ACS quirk for Intel 300 series (Mika Westerberg) * pci/virtualization: PCI/IOV: Allow PF drivers to limit total_VFs to 0 PCI: Add "pci=noats" boot parameter PCI: Add ACS quirk for Intel 300 series PCI: Add ACS quirk for Intel 7th & 8th Gen mobile nvme-pci: Use pci_sriov_configure_simple() to enable VFs net: ena: Use pci_sriov_configure_simple() to enable VFs PCI/IOV: Add pci-pf-stub driver for PFs that only enable VFs PCI/IOV: Add pci_sriov_configure_simple()
| * | | PCI/IOV: Allow PF drivers to limit total_VFs to 0Jakub Kicinski2018-05-251-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SR-IOV PF drivers implement .sriov_configure(), which allows user-space to enable VFs by writing the desired number of VFs to the sysfs "sriov_numvfs" file (see sriov_numvfs_store()). The PCI core limits the number of VFs to the TotalVFs advertised by the device in its SR-IOV capability. The PF driver can limit the number of VFs to even fewer (it may have pre-allocated data structures or knowledge of device limitations) by calling pci_sriov_set_totalvfs(), but previously it could not limit the VFs to 0. Change pci_sriov_get_totalvfs() so it always respects the VF limit imposed by the PF driver, even if the limit is 0. This sequence: pci_sriov_set_totalvfs(dev, 0); x = pci_sriov_get_totalvfs(dev); previously set "x" to TotalVFs from the SR-IOV capability. Now it will set "x" to 0. Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com> [bhelgaas: split to separate patch] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | PCI: Add "pci=noats" boot parameterGil Kupfer2018-05-116-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a "pci=noats" boot parameter. When supplied, all ATS related functions fail immediately and the IOMMU is configured to not use device-IOTLB. Any function that checks for ATS capabilities directly against the devices should also check this flag. Currently, such functions exist only in IOMMU drivers, and they are covered by this patch. The motivation behind this patch is the existence of malicious devices. Lots of research has been done about how to use the IOMMU as protection from such devices. When ATS is supported, any I/O device can access any physical address by faking device-IOTLB entries. Adding the ability to ignore these entries lets sysadmins enhance system security. Signed-off-by: Gil Kupfer <gilkup@cs.technion.ac.il> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joerg Roedel <jroedel@suse.de>
| * | | PCI: Add ACS quirk for Intel 300 seriesMika Westerberg2018-04-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel 300 series chipset still has the same ACS issue as the previous generations so extend the ACS quirk to cover it as well. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-07 14:38:04 +0100