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* pinctrl: intel: Do pin translation when lock IRQAndy Shevchenko2018-07-291-0/+30
| | | | | | | | | | | | | Default GPIOLIB callbacks for request and release IRQ do not do a GPIO to pin translation which is necessary for Intel hardware, such as Intel Cannonlake. Absence of the translation prevents some pins to be locked as IRQ due to direction check. Introduce own callbacks to make translation possible to avoid above issue. Fixes: a60eac3239f0 ("pinctrl: intel: Allow custom GPIO base for pad groups") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: imx: off by one in imx_pinconf_group_dbg_show()Dan Carpenter2018-07-291-1/+1
| | | | | | | | | | The > should really be >= here. It's harmless because pinctrl_generic_get_group() will return a NULL if group is invalid. Fixes: ae75ff814538 ("pinctrl: pinctrl-imx: add imx pinctrl core driver") Reported-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: include chained_irq.h headerArnd Bergmann2018-07-291-0/+1
| | | | | | | | | | | | | | | | | | Some randconfig builds fail in the mtk-eint driver: drivers/pinctrl/mediatek/mtk-eint.c: In function 'mtk_eint_irq_handler': drivers/pinctrl/mediatek/mtk-eint.c:324:2: error: implicit declaration of function 'chained_irq_enter'; did you mean 'rcu_irq_enter'? [-Werror=implicit-function-declaration] chained_irq_enter(chip, desc); ^~~~~~~~~~~~~~~~~ rcu_irq_enter drivers/pinctrl/mediatek/mtk-eint.c:367:2: error: implicit declaration of function 'chained_irq_exit'; did you mean 'rcu_irq_exit'? [-Werror=implicit-function-declaration] The functions are declared in linux/irqchip/chained_irq.h, and including that header makes it build in all configurations. Fixes: e46df235b4e6 ("pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fit") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl/amd: only handle irq if it is pending and unmaskedDaniel Kurtz2018-07-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMD pinctrl driver demultiplexes GPIO interrupts and fires off their individual handlers. If one of these GPIO irqs is configured as a level interrupt, and its downstream handler is a threaded ONESHOT interrupt, the GPIO interrupt source is masked by handle_level_irq() until the eventual return of the threaded irq handler. During this time the level GPIO interrupt status will still report as high until the actual gpio source is cleared - both in the individual GPIO interrupt status bit (INTERRUPT_STS_OFF) and in its corresponding "WAKE_INT_STATUS_REG" bit. Thus, if another GPIO interrupt occurs during this time, amd_gpio_irq_handler() will see that the (masked-and-not-yet-cleared) level irq is still pending and incorrectly call its handler again. To fix this, have amd_gpio_irq_handler() check for both interrupts status and mask before calling generic_handle_irq(). Note: Is it possible that this bug was the source of the interrupt storm on Ryzen when using chained interrupts before commit ba714a9c1dea85 ("pinctrl/amd: Use regular interrupt instead of chained")? Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl/amd: fix gpio irq level in debugfsDaniel Kurtz2018-07-292-7/+11
| | | | | | | | | | | | | | | | | According to the AMD BKDG, the GPIO ActiveLevel bits (10:9) map to: 00 Active High 01 Active Low 10 Active on both edges iff LevelTrig (bit 8) == 0 11 Reserved The current code has a bug where it interprets 00 => Active Low, and 01 => Active High. Fix the bug, restrict "Active on both" to just the edge trigger case, and refactor a bit to make the logic more readable. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: stm32: add syscfg mask parameterLudovic Barre2018-07-291-2/+14
| | | | | | | | | | | This patch adds mask parameter to define IRQ mux field. This field could vary depend of IRQ mux selection register. To avoid backward compatibility, the drivers set the legacy value by default. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* dt-bindings: pinctrl: add syscfg mask parameterLudovic Barre2018-07-291-3/+4
| | | | | | | | | | This patch adds mask parameter to define IRQ mux field. This field could vary depend of IRQ mux selection register. This parameter is needed if the mask is different of 0xf. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: stm32: check node status before new gpio bank registeringAlexandre Torgue2018-07-291-2/+16
| | | | | | | | Register a new GPIO bank only if GPIO bank node is enabled. This patch also adds checks on ranges which are defined only if a bank is registered. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: stm32: fix bank io port numberAlexandre Torgue2018-07-292-1/+10
| | | | | | | | | | | In case the exti line is not in line with the bank number (that is the case when there is an hole between two banks, for example GPIOK and then GPIOZ), use "st,bank-ioport" DT property to get the right exti line. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: berlin: add the as370 SoC pinctrl driverJisheng Zhang2018-07-293-0/+374
| | | | | | | | Add the pin-controller driver for Synaptics AS370 SoC, with definition of its groups and functions. This uses the core Berlin pinctrl driver. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'samsung-pinctrl-4.19' of ↵Linus Walleij2018-07-257-10/+113
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v4.19 1. Add handling of external wakeup interrupts mask inside the pin controller driver. Existing solution is spread between the driver and machine code. The machine code writes the mask but its value is taken from pin controller driver. This moves everything into pin controller driver allowing later to remove the cross-subsystem interaction. Also this is a necessary step for implementing later Suspend to RAM on ARMv8 Exynos5433. 2. Bring necessary suspend/resume callbacks for Exynos542x and Exynos5260. 3. Document hidden requirement about one external wakeup interrupts device node. 4. Minor documentation cleanups.
| * dt-bindings: pinctrl: samsung: Add SPDX license identifierKrzysztof Kozlowski2018-07-241-5/+2
| | | | | | | | | | | | Replace GPL license statement with SPDX license identifier (GPL-2.0). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * pinctrl: samsung: Write external wakeup interrupt maskKrzysztof Kozlowski2018-07-243-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinctrl driver defines an IRQ chip which handles external wakeup interrupts, therefore from logical point of view, it is the owner of external interrupt mask. The register controlling the mask belongs to Power Management Unit address space so it has to be accessed with PMU syscon regmap handle. This mask should be written to hardware during system suspend. Till now ARMv7 machine code was responsible for this which created a dependency between pin controller driver and arch/arm/mach code. Try to rework this dependency so the pinctrl driver will write external wakeup interrupt mask during late suspend. Impact on ARMv7 designs (S5Pv210 and Exynos) ============================================ This duplicates setting mask with existing machine code arch/arm/mach-exynos/suspend.c and arch/arm/mach-s5pv210/pm.c but it is not a problem - the wakeup mask register will be written twice. The machine code will be cleaned up later. The difference between implementation here and ARMv7 machine code (arch/arm/mach-*) is the time of writing the mask: 1. The machine code is writing the mask quite late during system suspend path, after offlining secondary CPUs and just before doing actual suspend. 2. The implementation in pinctrl driver uses late suspend ops, therefore it will write the mask much earlier. Hopefully late enough, after all drivers will enable or disable their interrupt wakeups (enable_irq_wake() etc). Impact on ARMv8 designs (Exynos5433 and Exynos7) ================================================ The Suspend to RAM was not supported and external wakeup interrupt mask was not written to HW. This change brings us one step closer to supporting Suspend to RAM. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Sylwester Nawrocki <snawrocki@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
| * ARM: exynos: Define EINT_WAKEUP_MASK registers for S5Pv210 and Exynos5433Krzysztof Kozlowski2018-07-242-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | S5Pv210 and Exynos5433/Exynos7 have different address of EINT_WAKEUP_MASK register. Rename existing S5P_EINT_WAKEUP_MASK to avoid confusion and add new ones. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Sylwester Nawrocki <snawrocki@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
| * pinctrl: samsung: Add dedicated compatible for S5Pv210 wakeup interruptsKrzysztof Kozlowski2018-07-242-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The S5Pv210 external wakeup interrupts differ from Exynos therefore separate compatible is needed. Duplicate existing flavor specific data from exynos4210_wkup_irq_chip and add new compatible for S5Pv210. At this point this new compatible does not bring anything new and works exactly as existing "samsung,exynos4210-wakeup-eint". Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Sylwester Nawrocki <snawrocki@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
| * pinctrl: samsung: Document hidden requirement about one external wakeupKrzysztof Kozlowski2018-07-241-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv7 hardware (S5Pv210 and Exynos SoCs) provides only 32 external interrupts which can wakeup device from deep sleep modes. On S5Pv210 these are gph0-gph3. On all ARMv7 Exynos designs these are gpx0-gpx3. There is only one 32-bit register for controlling the external wakeup interrupt mask (masking and unmasking waking capability of these interrupts). This lead to implementation in pinctrl driver and machine code which was using static memory for storing the mask value and not caring about multiple devices of pin controller... because only one pin controller device will be handling this. Since each pin controller node in Device Tree maps onto one device, this corresponds to hidden assumption in parsing the Device Tree: external wakeup interrupts can be defined only once. Make this assumption an explicit requirement. ARMv8 Exynos5433 and Exynos7 bring additional 32 external wakeup interrupts (up to 64 total, banks gpa0-gpa3 and gpf1-gpf5) and another 32-bit wide register for controlling them. Existing code does not support it but anyway these additional interrupts will be belonging to the same pin controller device/node. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Sylwester Nawrocki <snawrocki@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
| * pinctrl: samsung: Document suspend and resume membersKrzysztof Kozlowski2018-07-241-0/+8
| | | | | | | | | | | | | | | | | | | | | | Add missing documentation for suspend and resume members of struct samsung_pin_ctrl and samsung_pinctrl_drv_data. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Sylwester Nawrocki <snawrocki@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
| * pinctrl: samsung: Define suspend and resume callbacks for all banks and SoCsKrzysztof Kozlowski2018-07-241-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Suspend and resume callbacks in Exynos/S5Pv210 pin controller drivers, save and restore state of registers. This operations should be done for all banks which have external interrupts (as denoted by using EXYNOS_PIN_BANK_EINTG/EINTW macros). Add all banks of Exynos5260 and Exynos5420. This is necessary step for supporting suspend to RAM on these SoCs. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Sylwester Nawrocki <snawrocki@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
* | pinctrl: mt7622: Fix probe fail by misuse the selectorSean Wang2018-07-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the commit acf137951367 ("pinctrl: core: Return selector to the pinctrl driver") and the commit 47f1242d19c3 ("pinctrl: pinmux: Return selector to the pinctrl driver"), it's necessary to add the fixes needed for the pin controller drivers to use the appropriate returned selector for a negative error number returned in case of the fail at these functions. Otherwise, the driver would have a failed probe and that causes boot message cannot correctly output and devices fail to acquire their own pins. Cc: Kevin Hilman <khilman@baylibre.com> Fixes: acf137951367 ("pinctrl: core: Return selector to the pinctrl driver") Fixes: 47f1242d19c3 ("pinctrl: pinmux: Return selector to the pinctrl driver") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: single: Fix missing unlock on error pathWei Yongjun2018-07-171-2/+2
| | | | | | | | | | | | | | | | | | | | Add the missing unlock before return from function in the error handling case. Fixes: 0f5972033509 ("pinctrl: single: Fix group and function selector use") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: core: Remove broken remove_last group and pinmux functionsTony Lindgren2018-07-172-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With no users left for these functions let's remove them. Reported-by: H. Nikolaus Schaller <hns@goldelico.com> Cc: Christ van Willegen <cvwillegen@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Jacopo Mondi <jacopo+renesas@jmondi.org> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Tested-By: H. Nikolaus Schaller <hns@goldelico.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: rza1: Fix selector use for groups and functionsTony Lindgren2018-07-171-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We must use a mutex around the generic_add functions and save the function and group selector in case we need to remove them. Otherwise the selector use will be racy for deferred probe at least. Fixes: 5a49b644b307 ("pinctrl: Renesas RZ/A1 pin and gpio controller") Reported-by: H. Nikolaus Schaller <hns@goldelico.com> Cc: Christ van Willegen <cvwillegen@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Sean Wang <sean.wang@mediatek.com> Acked-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Tested-By: H. Nikolaus Schaller <hns@goldelico.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: single: Fix group and function selector useTony Lindgren2018-07-171-36/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We must use a mutex around the generic_add functions and save the function and group selector in case we need to remove them. Otherwise the selector use will be racy for deferred probe at least. Note that struct device_node *np is unused in pcs_add_function() we remove that too and fix a checkpatch warning for bare unsigned while at it. Fixes: 571aec4df5b7 ("pinctrl: single: Use generic pinmux helpers for managing functions") Reported-by: H. Nikolaus Schaller <hns@goldelico.com> Cc: Christ van Willegen <cvwillegen@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Jacopo Mondi <jacopo+renesas@jmondi.org> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Tested-By: H. Nikolaus Schaller <hns@goldelico.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: pinmux: Return selector to the pinctrl driverTony Lindgren2018-07-171-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We must return the selector from pinmux_generic_add_function() so pin controller device drivers can remove the right group if needed for deferred probe for example. And we now must make sure that a proper name is passed so we can use it to check if the entry already exists. Note that fixes are also needed for the pin controller drivers to use the selector value. Fixes: a76edc89b100 ("pinctrl: core: Add generic pinctrl functions for managing groups") Reported-by: H. Nikolaus Schaller <hns@goldelico.com> Cc: Christ van Willegen <cvwillegen@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Jacopo Mondi <jacopo+renesas@jmondi.org> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Tested-By: H. Nikolaus Schaller <hns@goldelico.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: core: Return selector to the pinctrl driverTony Lindgren2018-07-171-3/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We must return the selector from pinctrl_generic_add_group() so pin controller device drivers can remove the right group if needed for deferred probe for example. And we now must make sure that a proper name is passed so we can use it to check if the entry already exists. Note that fixes are also needed for the pin controller drivers to use the selector value. Fixes: c7059c5ac70a ("pinctrl: core: Add generic pinctrl functions for managing groups") Reported-by: H. Nikolaus Schaller <hns@goldelico.com> Cc: Christ van Willegen <cvwillegen@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Jacopo Mondi <jacopo+renesas@jmondi.org> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Tested-By: H. Nikolaus Schaller <hns@goldelico.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-binding: pinctrl: berlin: document AS370 SoC pinctrlJisheng Zhang2018-07-161-1/+2
| | | | | | | | | | | | | | Add as370 to existing berlin pinctrl device tree binding. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: at91-pio4: Remove redundant return value checkWei Yongjun2018-07-161-4/+0
| | | | | | | | | | | | | | | | | | | | | | Remove unneeded error handling on the result of a call to platform_get_resource() when the value is passed to devm_ioremap_resource(). Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: ocelot: fix gpio4 twi functionAlexandre Belloni2018-07-161-1/+1
| | | | | | | | | | | | | | | | the TWI function on GPIO4 is actually a multiplexed SCL, not an original TWI SDA or SCL. Fix it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: add driver for i.MX8MQLucas Stach2018-07-163-0/+359
| | | | | | | | | | | | | | | | | | | | The i.MX8MQ pincontrol works in a similar way to the earlier i.MX SoCs. This driver builds on top of the imx specific pinconf handling. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: Add DT binding for i.MX8MQ IOMUXCAbel Vesa2018-07-161-0/+36
| | | | | | | | | | | | | | | | | | | | This adds the binding for the i.MX8MQ pin controller, in the same fashion as earlier i.MX SoCs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: baytrail: Mark expected switch fall-throughsGustavo A. R. Silva2018-07-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Addresses-Coverity-ID: 1292308 ("Missing break in switch") Addresses-Coverity-ID: 1292309 ("Missing break in switch") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: at91-pio4: add support for drive strengthLudovic Desroches2018-07-163-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the drive strength configuration. Usually, this value is expressed in mA. Since the numeric value depends on VDDIOP voltage, a value we can't retrieve at runtime, the controller uses low, medium and high to define the drive strength. The PIO controller accepts two values for the low drive configuration: 0 and 1. Most of the time, we don't care about the drive strength. So we keep the default value which is 0. The drive strength is advertised through the sysfs only when it has been explicitly set in the device tree i.e. if its value is different from 0. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mt7622: mark expected switch fall-throughGustavo A. R. Silva2018-07-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Warning level 2 was used: -Wimplicit-fallthrough=2 Addresses-Coverity-ID: 1463284 ("Missing break in switch") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: add gen_clk pinsJerome Brunet2018-07-162-0/+17
| | | | | | | | | | | | | | | | | | Add the pinctrl configuration for gen_clk on gxbb and axg. gen_clk allows to output and devide several internal clocks of SoC, including most of the plls. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sh-pfc: r8a77990: Add USB3.0 pins, groups and functionsTakeshi Kihara2018-07-161-0/+27
| | | | | | | | | | | | | | | | | | | | This patch adds USB30_{PWEN,OVC} and USB3HS0_ID pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sh-pfc: r8a77990: Add USB2.0 pins, groups and functionsTakeshi Kihara2018-07-161-0/+38
| | | | | | | | | | | | | | | | | | | | This patch adds USB0_{PWEN,OVC}_{A,B} and USB0_ID pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sh-pfc: r8a77990: Revise USB ID pin nameYoshihiro Shimoda2018-07-161-2/+2
| | | | | | | | | | | | | | | | | | Since the datasheet Rev.1.00 has an error about the USB ID pin name, this patch revises it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sh-pfc: r8a77965: Add HSCIF pins, groups, and functionsTakeshi Kihara2018-07-161-0/+333
| | | | | | | | | | | | | | | | | | This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliantDouglas Anderson2018-07-091-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If you do this on an sdm845 board: grep "" /sys/kernel/debug/pinctrl/*spmi:pmic*/pinconf-groups ...it looks like nonsense. For every pin you see listed: input bias disabled, input bias high impedance, input bias pull down, input bias pull up, ... That's because pmic_gpio_config_get() isn't complying with the rules that pinconf_generic_dump_one() expects. Specifically for boolean parameters (anything with a "struct pin_config_item" where has_arg is false) the function expects that the function should return its value not through the "config" parameter but should return "0" if the value is set and "-EINVAL" if the value isn't set. Let's fix this. From a quick sample of other pinctrl drivers, it appears to be tradition to also return 1 through the config parameter for these boolean parameters when they exist. I'm not one to knock tradition, so I'll follow tradition and return 1 in these cases. While I'm at it, I'll also continue searching for four leaf clovers, kocking on wood three times, and trying not to break mirrors. NOTE: This also fixes an apparent typo for reading PIN_CONFIG_BIAS_DISABLE where the old driver was accidentally using "=" instead of "==" and thus was setting some internal state when you tried to query PIN_CONFIG_BIAS_DISABLE. Oops. Fixes: eadff3024472 ("pinctrl: Qualcomm SPMI PMIC GPIO pin controller driver") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: msm: Fix msm_config_group_get() to be compliantDouglas Anderson2018-07-091-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If you do this on an sdm845 board: cat /sys/kernel/debug/pinctrl/3400000.pinctrl/pinconf-groups ...it looks like nonsense. For every pin you see listed: input bias bus hold, input bias disabled, input bias pull down, input bias pull up That's because msm_config_group_get() isn't complying with the rules that pinconf_generic_dump_one() expects. Specifically for boolean parameters (anything with a "struct pin_config_item" where has_arg is false) the function expects that the function should return its value not through the "config" parameter but should return "0" if the value is set and "-EINVAL" if the value isn't set. Let's fix this. From a quick sample of other pinctrl drivers, it appears to be tradition to also return 1 through the config parameter for these boolean parameters when they exist. I'm not one to knock tradition, so I'll follow tradition and return 1 in these cases. While I'm at it, I'll also continue searching for four leaf clovers, kocking on wood three times, and trying not to break mirrors. Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Document pin_config_group_get() return codes like pin_config_get()Douglas Anderson2018-07-091-1/+2
| | | | | | | | | | | | | | | | | | The pinconf_generic_dump_one() function makes the assumption that pin_config_group_get() should return -EINVAL and -ENOTSUPP just like pin_config_get() does. Document that so it's more obvious. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: actions: fix unsigned less than zero comparisonColin Ian King2018-07-021-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check to see if platform_get_irq failed is performed on the unsigned value of pctrl->irq[i] and the check is never true because an unsigned cannot be less than zero. Fix this by assinging the signed int ret to the return of platform_get_irq and checking ret instead. Detected by CoverityScan, CID#1470247 ("Unsigned comparison against 0") Fixes: 6c5d0736e9c0 ("pinctrl: actions: Add interrupt support for OWL S900 SoC") Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: intel: Convert to use SPDX identifierAndy Shevchenko2018-07-0213-56/+15
| | | | | | | | | | | | | | | | | | | | Reduce size of duplicated comments by switching to use SPDX identifier. No functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: intel: Add Ice Lake PCH pin controller supportAndy Shevchenko2018-06-293-0/+445
| | | | | | | | | | | | | | | | | | | | This adds pinctrl/GPIO support for Intel Ice Lake PCH. The Ice Lake PCH GPIO is based on the same version of the Intel GPIO hardware than Intel Cannon Lake with different set of pins and ACPI ID. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: armada-37xx: add suspend/resume supportMiquel Raynal2018-06-291-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add suspend/resume hooks in pinctrl driver to handle S2RAM operations. Beyond the traditional register save/restore operations, these hooks also keep the GPIOs used for both-edge IRQ synchronized between their level (low/high) and expected IRQ polarity (falling/rising edge). Since pinctrl is an infrastructure module, its resume should be issued prior to other IO drivers. The pinctrl PM operations are requested at early/late stages for this reason. Suggested-by: Ken Ma <make@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: actions: Add interrupt support for OWL S900 SoCManivannan Sadhasivam2018-06-294-18/+307
| | | | | | | | | | | | | | | | Add interrupt support for Actions Semi OWL S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: Add gpio interrupt bindings for Actions S900 SoCManivannan Sadhasivam2018-06-291-0/+10
| | | | | | | | | | | | | | | | Add gpio interrupt bindings for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: qcom: add gpio-ranges, gpio-reserved-rangesChristian Lamparter2018-06-2812-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the gpio-ranges and gpio-reserved-ranges property definitions to the binding text files supported by the pinctrl-msm driver framework. gpio-ranges: For DT-based platforms the pinctrl-msm framework currently relies on the deprecated-for-DT gpiochip_add_pin_range() function to add the range of GPIOs to be handled by the pin controller. Due to interactions within gpiolib code, this causes the pinctrl-msm driver to bail out (-517) during boot when a gpio-hog is declared. This can be fatal and cause the system to not boot or reset (for a detailed explanation and call-trace, refer to patch: "pinctrl: msm: fix gpio-hog related boot issues" in this series). gpio-reserved-ranges: The binding has been added as a precaution since the TrustZone firmware (aka QSEE), which is running as the hypervisor, might have reserved certain, but undisclosed pins. Hence reading or writing to the registers for those pins will cause an XPU violation and this subsequently crashes the kernel. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: aspeed: Fix documentationJoel Stanley2018-06-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Fixes these warnings: pinctrl-aspeed.c:112: warning: Function parameter or member 'map' not described in 'aspeed_sig_desc_eval' pinctrl-aspeed.c:112: warning: Excess function parameter 'regmap' description in 'aspeed_sig_desc_eval' Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: cedarfork: Correct EAST pin orderingMika Westerberg2018-06-281-46/+46
| | | | | | | | | | | | | | | | | | The driver missed the fact that PECI_SMB_DATA has moved from EAST community 224 to 182 instead. Correct the pin ordering accordingly. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>