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* mmc: sdhci-of-esdhc: add peripheral clock supportyangbo lu2017-04-242-2/+72
| | | | | | | | | | | | | eSDHC could select peripheral clock or platform clock as clock source by the PCS bit of eSDHC Control Register, and this bit couldn't be reset by software reset for all. In default, the platform clock is used. But we have to use peripheral clock since it has a higher frequency to support eMMC HS200 mode and SD UHS-I mode. This patch is to add peripheral clock support and use it instead of platform clock if it's declared in eSDHC dts node. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-pci: Allow for 3 bytes from Intel DSMAdrian Hunter2017-04-241-6/+6
| | | | | | | | The DSM used by some Intel controllers can return a 3 byte package. Allow for that by using memcpy to copy the bytes. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: cavium: Fix a shift wrapping bugDan Carpenter2017-04-241-1/+1
| | | | | | | "dat" is a u64 and "shift" starts as 54 so this is a shift wrapping bug. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: cavium: Check pointer before de-referenceJan Glauber2017-04-241-1/+1
| | | | | | | | | | | | | | Add a pointer check to prevent this smatch warning: drivers/mmc/host/cavium.c:803 cvm_mmc_request() error: we previously assumed 'cmd->data' could be null (see line 782) This is a theoretical fix because MMC_CMD_ADTC seems to imply that cmd->data is not null. Nevertheless checking cmd->data before using it improves readability. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: cavium: Remove redundant pointer checkJan Glauber2017-04-241-1/+1
| | | | | | | | | | Remove redundant mmc->card check reported by smatch: drivers/mmc/host/cavium.c:694 cvm_mmc_dma_request() warn: variable dereferenced before check 'mmc->card' (see line 675) Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: add support for descriptor chain modeHeiner Kallweit2017-04-241-16/+156
| | | | | | | | | | | | | | | | | | So far a bounce buffer is used to serialize the scatterlist(s). This overhead can be avoided by switching to descriptor chain mode. As result the performance is drastically improved. On a Odroid-C2 with a 128 GB eMMC module raw reads reach 140 MB/s. Prerequisite for descriptor chain mode is that all scatterlist buffers are 8 byte aligned for 64-bit DMA. That's not always the case, at least the brcmfmac SDIO WiFi driver is known to cause problems. Therefore, for each request, check upfront whether all scatterlist buffers are 8 byte aligned and fall back to bounce buffer mode if that's not the case. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: add basic tuning for rx clock phaseHeiner Kallweit2017-04-241-0/+49
| | | | | | | | | | | | | | | | | | This patch adds basic tuning which changes the rx clock phase only until a working setting is found. On a Odroid C2 with 128GB eMMC card and 200 MHz MMC clock only 180° rx clock phase make the system boot w/o CRC errors. With other MMC devices / clock speeds this might be different, therefore don't change the driver config in general. When retuning skip the currently active parameter set. This avoids the current problematic config to be chosen again if it causes CRC errors just occasionally. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: introduce struct meson_tuning_paramsHeiner Kallweit2017-04-241-1/+16
| | | | | | | | | Introduce struct meson_tuning_params for storing the clock phase configurations. There's no functional change because tx and rx clock phase were implicitely set to CLK_PHASE_0 before. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core: add proper be32 annotationWinkler, Tomas2017-04-244-17/+16
| | | | | | | | | Annotate big endian values correctly and make sparse happy. In mmc_app_send_scr remove scr function parameter as it was updating card->raw_scr anyway. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-cadence: add parsing sdhci propertiesPiotr Sroka2017-04-241-0/+2
| | | | | | | | | Add calling sdhci_get_of_property function to parse sdhci properties. Signed-off-by: Piotr Sroka <piotrs@cadence.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: host: omap_hsmmc: checking for NULL instead of IS_ERR()Dan Carpenter2017-04-241-2/+2
| | | | | | | | | devm_pinctrl_get() returns error pointers, it never returns NULL. Fixes: 455e5cd6f736 ("mmc: omap_hsmmc: Pin remux workaround to support SDIO interrupt on AM335x") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* MAINTAINERS: add entry for Marvell Xenon MMC Host Controller driversHu Ziji2017-04-241-0/+7
| | | | | | | | | Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host Controller drivers. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-xenon: Add SoC PHY PAD voltage controlHu Ziji2017-04-243-1/+113
| | | | | | | | | | | | | Some SoCs have PHY PAD outside Xenon IP. PHY PAD voltage should match signalling voltage in use. Add generic SoC PHY PAD voltage control interface. Implement Aramda-3700 SoC PHY PAD voltage control. Signed-off-by: Hu Ziji <huziji@marvell.com> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHCHu Ziji2017-04-244-3/+774
| | | | | | | | | | | | | | | | | | | | | Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY. Multiple types of PHYs are supported. Add support to multiple types of PHYs init and configuration. Add register definitions of PHYs. Xenon PHY cannot fit in kernel common PHY framework. Xenon SDHC PHY register is a part of Xenon SDHC register set. Besides, MMC initialization has to call several PHY functions to complete timing setting. Those PHY setting functions have to access SDHC registers and know current MMC setting, such as bus width, clock frequency and speed mode. As a result, implement Xenon PHY in MMC host directory. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionalityHu Ziji2017-04-244-0/+612
| | | | | | | | | | | | | | | | | Add Xenon eMMC/SD/SDIO host controller core functionality. Add Xenon specific initialization process. Add Xenon specific mmc_host_ops APIs. Add Xenon specific register definitions. Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig. Marvell Xenon SDHC conforms to SD Physical Layer Specification Version 3.01 and is designed according to the guidelines provided in the SD Host Controller Standard Specification Version 3.00. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* dt: bindings: Add bindings for Marvell Xenon SD Host ControllerHu Ziji2017-04-241-0/+170
| | | | | | | | | | | Marvell Xenon SDHC can support eMMC/SD/SDIO. Add Xenon-specific properties. Also add properties for Xenon PHY setting. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.cHu Ziji2017-04-242-1/+3
| | | | | | | | | | | Export sdhci_enable_sdio_irq() from sdhci.c. Thus vendor SDHC driver can implement its specific SDIO irq control. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.cHu Ziji2017-04-242-2/+5
| | | | | | | | | | | Export sdhci_start_signal_voltage_switch() from sdhci.c. Thus vendor sdhci driver can implement its own signal voltage switch routine. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Export sdhci_set_ios() from sdhci.cHu Ziji2017-04-242-1/+3
| | | | | | | | | | Export sdhci_set_ios() in sdhci.c. Thus vendor sdhci driver can implement its own set_ios() routine. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* clk: apn806: Turn the eMMC clock as optional for dts backwards compatibleGregory CLEMENT2017-04-241-7/+13
| | | | | | | | | | First version of the binding didn't have the eMMC clock. This patch allows to not registering the eMMC clock if it is not present in the device tree. Then the device tree can be backwards compatible. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* clk: apn806: Add eMMC clock to system controller driverKonstantin Porotchkin2017-04-242-2/+16
| | | | | | | | | | | | | | Add fixed clock of 400MHz to system controller driver. This clock is used as SD/eMMC clock source. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> [fixed up conflicts, added error handling --rmk] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* MAINTAINERS: Add entry for Cavium MMC driverJan Glauber2017-04-241-0/+8
| | | | | | | Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: cavium: Support DDR mode for eMMC devicesJan Glauber2017-04-241-1/+11
| | | | | | | Add support for switching to DDR mode for eMMC devices. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: cavium: Add scatter-gather DMA supportJan Glauber2017-04-243-10/+127
| | | | | | | | | Add Support for the scatter-gather DMA available in the ThunderX MMC units. Up to 16 DMA requests can be processed together. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: cavium: Add MMC PCI driver for ThunderX SOCsJan Glauber2017-04-244-0/+215
| | | | | | | Add a platform driver for ThunderX ARM SOCs. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: cavium: Add core MMC driver for Cavium SOCsJan Glauber2017-04-242-0/+1174
| | | | | | | | | | | | | | | | | | | | | | | | | | This core driver will be used by a MIPS platform driver or by an ARM64 PCI driver. The core driver implements the mmc_host_ops and slot probe & remove functions. Callbacks are provided to allow platform specific interrupt enable and bus locking. The host controller supports: - up to 4 slots that can contain sd-cards or eMMC chips - 1, 4 and 8 bit bus width - SDR and DDR - transfers up to 52 Mhz (might be less when multiple slots are used) - DMA read/write - multi-block read/write (but not stream mode) Voltage is limited to 3.3v and shared for all slots (vmmc and vmmcq). A global lock for all MMC devices is required because the host controller is shared. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* dt-bindings: mmc: Add Cavium SOCs MMC bindingsJan Glauber2017-04-241-0/+57
| | | | | | | | | | | | | | | Add description of Cavium Octeon and ThunderX SOC device tree bindings. CC: Ulf Hansson <ulf.hansson@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> CC: devicetree@vger.kernel.org Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core: refactor mmc_request_done()Linus Walleij2017-04-241-11/+16
| | | | | | | | | | | | | | | | | | | | | | We have this construction: if (a && b && !c) finalize; else block; finalize; Which is equivalent by boolean logic to: if (!a || !b || c) block; finalize; Which is simpler code. Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core: refactor asynchronous request finalizationLinus Walleij2017-04-241-53/+33
| | | | | | | | | | mmc_wait_for_data_req_done() is called in exactly one place, and having it spread out is making things hard to oversee. Factor this function into mmc_finalize_areq(). Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core: move some code in mmc_start_areq()Linus Walleij2017-04-241-8/+5
| | | | | | | | | | | | "previous" is a better name for the variable storing the previous asynchronous request, better than the opaque name "data" atleast. We see that we assign the return status to the returned variable on all code paths, so we might as well just do that immediately after calling mmc_finalize_areq(). Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core: Factor out mrq preparation from mmc_start_request()Adrian Hunter2017-04-241-13/+27
| | | | | | | | In preparation to reuse the code for CQE support. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core: Factor out debug prints from mmc_start_request()Adrian Hunter2017-04-241-13/+20
| | | | | | | | In preparation to reuse the code for CQE support. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: block: Factor out data preparationAdrian Hunter2017-04-241-69/+82
| | | | | | | | | Factor out data preparation into a separate function mmc_blk_data_prep() which can be re-used for command queuing. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: block: Change mmc_apply_rel_rw() to get block address from the requestAdrian Hunter2017-04-241-1/+1
| | | | | | | | | | mmc_apply_rel_rw() will be used by Software Command Queuing also. In that case the command argument is not the block address so change mmc_apply_rel_rw() to get block address from the request. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: block: Disable Command Queue while RPMB is usedAdrian Hunter2017-04-241-8/+38
| | | | | | | | | | | | RPMB does not allow Command Queue commands. Disable and re-enable the Command Queue when switching. Note that the driver only switches partitions when the queue is empty. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Harjani Ritesh <riteshh@codeaurora.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmc_test: Disable Command Queue while mmc_test is usedAdrian Hunter2017-04-243-0/+23
| | | | | | | | | | | Normal read and write commands may not be used while the command queue is enabled. Disable the Command Queue when mmc_test is probed and re-enable it when it is removed. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Harjani Ritesh <riteshh@codeaurora.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmc: Add functions to enable / disable the Command QueueAdrian Hunter2017-04-245-0/+34
| | | | | | | | Add helper functions to enable or disable the Command Queue. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: queue: Share mmc request array between partitionsAdrian Hunter2017-04-244-96/+156
| | | | | | | | | | | | | | eMMC can have multiple internal partitions that are represented as separate disks / queues. However switching between partitions is only done when the queue is empty. Consequently the array of mmc requests that are queued can be shared between partitions saving memory. Keep a pointer to the mmc request queue on the card, and use that instead of allocating a new one for each partition. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: block: Introduce queue semanticsAdrian Hunter2017-04-243-56/+95
| | | | | | | | | | | | | | | | | Change from viewing the requests in progress as 'current' and 'previous', to viewing them as a queue. The current request is allocated to the first free slot. The presence of incomplete requests is determined from the count (mq->qcnt) of entries in the queue. Non-read-write requests (i.e. discards and flushes) are not added to the queue at all and require no special handling. Also no special handling is needed for the MMC_BLK_NEW_REQUEST case. As well as allowing an arbitrarily sized queue, the queue thread function is significantly simpler. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: block: Use local var for mqrq_curAdrian Hunter2017-04-241-12/+14
| | | | | | | | | A subsequent patch will remove 'mq->mqrq_cur'. Prepare for that by assigning it to a local variable. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: host: s3cmci: allow probing from device treeSergio Prado2017-04-241-131/+126
| | | | | | | | | | Allows configuring Samsung S3C24XX MMC/SD/SDIO controller using a device tree. Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com> [Arnd: fix broken conditional expression] Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* dt-bindings: mmc: add DT binding for S3C24XX MMC/SD/SDIO controllerSergio Prado2017-04-241-0/+42
| | | | | | | | | | Adds the device tree bindings description for Samsung S3C24XX MMC/SD/SDIO controller, used as a connectivity interface with external MMC, SD and SDIO storage mediums. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-pci: Set MMC_CAP_AGGRESSIVE_PM for BYT-related Intel controllersAzhar Shaikh2017-04-241-4/+3
| | | | | | | | | Set MMC_CAP_AGGRESSIVE_PM for BYT-related Intel SD card controllers. Signed-off-by: Azhar Shaikh <azhar.shaikh@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-acpi: Set MMC_CAP_AGGRESSIVE_PM for BYT-related Intel controllersAzhar Shaikh2017-04-241-4/+2
| | | | | | | | | Set MMC_CAP_AGGRESSIVE_PM for BYT-related Intel SD card controllers. Signed-off-by: Azhar Shaikh <azhar.shaikh@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: factor out setting response configuration bitsHeiner Kallweit2017-04-241-14/+18
| | | | | | | | | Factor out setting the response configuration bits thus further reducing complexity of function meson_mmc_start_cmd. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: factor out setting block sizeHeiner Kallweit2017-04-241-15/+27
| | | | | | | | | Factor out setting the block size. This also contributes to reducing complexity of function meson_mmc_start_cmd. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-cadence: refactor probe functionPiotr Sroka2017-04-241-1/+1
| | | | | | | | | Use added dev variable for devm_clk_get. Signed-off-by: Piotr Sroka <piotrs@cadence.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-cadence: Update PHY delay configurationPiotr Sroka2017-04-241-7/+46
| | | | | | | | | | DTS properties are used instead of fixed data because PHY settings can be different for different chips/boards. Signed-off-by: Piotr Sroka <piotrs@cadence.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* dt-bindings: mmc: add description of PHY delays for sdhci-cadencePiotr Sroka2017-04-241-0/+48
| | | | | | | | | | | DTS properties are used instead of fixed data because PHY settings can be different for different chips/boards. Add description of new DLL PHY delays. Signed-off-by: Piotr Sroka <piotrs@cadence.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-cadence: Fix writing PHY delayPiotr Sroka2017-04-241-2/+9
| | | | | | | | | Add polling for ACK to be sure that data are written to PHY register. Signed-off-by: Piotr Sroka <piotrs@cadence.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-16 03:51:40 +0100