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* iio: gyro: bmg160: fix buffer read valuesIrina Tirdea2016-04-031-1/+1
| | | | | | | | | | | | | | When reading gyroscope axes using iio buffers, the values returned are always 0. In the interrupt handler, the return value of the read operation is returned to the user instead of the value read. Return the value read to the user. This is also fixed in commit 82d8e5da1a33 ("iio: accel: bmg160: optimize transfers in trigger handler"). Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
* iio: gyro: bmg160: fix endianness when reading axesIrina Tirdea2016-04-031-3/+4
| | | | | | | | | | | | | | | | | | | | | | For big endian platforms, reading the axes will return invalid values. The device stores each axis value in a 16 bit little endian register. The driver uses regmap_read_bulk to get the axis value, resulting in a 16 bit little endian value. This needs to be converted to cpu endianness to work on big endian platforms. Fix endianness for big endian platforms by converting the values for the axes read from little endian to cpu. This is also partially fixed in commit 82d8e5da1a33 ("iio: accel: bmg160: optimize transfers in trigger handler"). Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
* iio: accel: bmc150: fix endianness when reading axesIrina Tirdea2016-04-031-3/+4
| | | | | | | | | | | | | | | | | | | | | | For big endian platforms, reading the axes will return invalid values. The device stores each axis value in a 16 bit little endian register. The driver uses regmap_read_bulk to get the axis value, resulting in a 16 bit little endian value. This needs to be converted to cpu endianness to work on big endian platforms. Fix endianness for big endian platforms by converting the values for the axes read from little endian to cpu. This is also partially fixed in commit b6fb9b6d6552 ("iio: accel: bmc150: optimize transfers in trigger handler"). Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
* iio: st_magn: always define ST_MAGN_TRIGGER_SET_STATEArnd Bergmann2016-04-031-0/+1
| | | | | | | | | | | | | | | | | | | | When CONFIG_IIO_TRIGGER is enabled but CONFIG_IIO_BUFFER is not, we get a build error in the st_magn driver: drivers/iio/magnetometer/st_magn_core.c:573:23: error: 'ST_MAGN_TRIGGER_SET_STATE' undeclared here (not in a function) .set_trigger_state = ST_MAGN_TRIGGER_SET_STATE, ^~~~~~~~~~~~~~~~~~~~~~~~~ Apparently, this ST_MAGN_TRIGGER_SET_STATE macro was meant to be set to NULL when the definition is not available because st_magn_buffer.c is not compiled, but the alternative definition was not included in the original patch. This adds it. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 74f5683f35fe ("iio: st_magn: Add irq trigger handling") Acked-by: Denis Ciocca <denis.ciocca@st.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
* iio: fix config watermark initial valueIrina Tirdea2016-03-281-0/+1
| | | | | | | | | | | | | | | | | | config structure is set to 0 when updating the buffers, so by default config->watermark will be 0. When computing the minimum between config->watermark and the buffer->watermark or insert_buffer-watermark, this will always be 0 regardless of the value set by the user for the buffer. Set as initial value for config->watermark the maximum allowed value so that the minimum value will always be set from one of the buffers. Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Fixes: f0566c0c405d ("iio: Set device watermark based on watermark of all attached buffers") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
* iio: health: max30100: correct FIFO check conditionMatt Ranostay2016-03-281-1/+2
| | | | | | | | | Correct issue that the last entry in FIFO was being read twice due to an incorrect decrement of entry count variable before condition check. Signed-off-by: Matt Ranostay <mranostay@gmail.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
* iio: imu: Fix inv_mpu6050 dependenciesRichard Weinberger2016-03-281-2/+1
| | | | | | | | | | | | | | | | | | | Not all archs have io memory. Instead of selecting I2C_MUX (and bypassing the HAS_IOMEM dependency) depend directly on it. Fixes the following kconfig warning: warning: (MEDIA_SUBDRV_AUTOSELECT && VIDEO_CX231XX && INV_MPU6050_I2C) selects I2C_MUX which has unmet direct dependencies (I2C && HAS_IOMEM) And this build error: ERROR: "devm_ioremap_resource" [drivers/i2c/muxes/i2c-mux-reg.ko] undefined! ERROR: "of_address_to_resource" [drivers/i2c/muxes/i2c-mux-reg.ko] undefined! Cc: Jonathan Cameron <jic23@kernel.org> Cc: Hartmut Knaack <knaack.h@gmx.de> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Peter Meerwald <pmeerw@pmeerw.net> Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
* iio: adc: Fix build error of missing devm_ioremap_resource on UMKrzysztof Kozlowski2016-03-281-0/+1
| | | | | | | | | | | The devres.o gets linked if HAS_IOMEM is present so on ARCH=um allyesconfig (COMPILE_TEST) failed with: drivers/built-in.o: In function `at91_adc_probe': at91-sama5d2_adc.c:(.text+0x48f548): undefined reference to `devm_ioremap_resource' Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
* Merge branch 'for-linus' of git://git.kernel.dk/linux-blockLinus Torvalds2016-03-2514-78/+251
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull block fixes from Jens Axboe: "Final round of fixes for this merge window - some of this has come up after the initial pull request, and some of it was put in a post-merge branch before the merge window. This contains: - Fix for a bad check for an error on dma mapping in the mtip32xx driver, from Alexey Khoroshilov. - A set of fixes for lightnvm, from Javier, Matias, and Wenwei. - An NVMe completion record corruption fix from Marta, ensuring that we read things in the right order. - Two writeback fixes from Tejun, marked for stable@ as well. - A blk-mq sw queue iterator fix from Thomas, fixing an oops for sparse CPU maps. They hit this in the hot plug/unplug rework" * 'for-linus' of git://git.kernel.dk/linux-block: nvme: avoid cqe corruption when update at the same time as read writeback, cgroup: fix use of the wrong bdi_writeback which mismatches the inode writeback, cgroup: fix premature wb_put() in locked_inode_to_wb_and_lock_list() blk-mq: Use proper cpumask iterator mtip32xx: fix checks for dma mapping errors lightnvm: do not load L2P table if not supported lightnvm: do not reserve lun on l2p loading nvme: lightnvm: return ppa completion status lightnvm: add a bitmap of luns lightnvm: specify target's logical address area null_blk: add lightnvm null_blk device to the nullb_list
| * nvme: avoid cqe corruption when update at the same time as readMarta Rybczynska2016-03-221-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure the CQE phase (validity) is read before the rest of the structure. The phase bit is the highest address and the CQE read will happen on most platforms from lower to upper addresses and will be done by multiple non-atomic loads. If the structure is updated by PCI during the reads from the processor, the processor may get a corrupted copy. The addition of the new nvme_cqe_valid function that verifies the validity bit also allows refactoring of the other CQE read sequences. Signed-off-by: Marta Rybczynska <marta.rybczynska@kalray.eu> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Jens Axboe <axboe@fb.com>
| * writeback, cgroup: fix use of the wrong bdi_writeback which mismatches the inodeTejun Heo2016-03-201-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When cgroup writeback is in use, there can be multiple wb's (bdi_writeback's) per bdi and an inode may switch among them dynamically. In a couple places, the wrong wb was used leading to performing operations on the wrong list under the wrong lock corrupting the io lists. * writeback_single_inode() was taking @wb parameter and used it to remove the inode from io lists if it becomes clean after writeback. The callers of this function were always passing in the root wb regardless of the actual wb that the inode was associated with, which could also change while writeback is in progress. Fix it by dropping the @wb parameter and using inode_to_wb_and_lock_list() to determine and lock the associated wb. * After writeback_sb_inodes() writes out an inode, it re-locks @wb and inode to remove it from or move it to the right io list. It assumes that the inode is still associated with @wb; however, the inode may have switched to another wb while writeback was in progress. Fix it by using inode_to_wb_and_lock_list() to determine and lock the associated wb after writeback is complete. As the function requires the original @wb->list_lock locked for the next iteration, in the unlikely case where the inode has changed association, switch the locks. Kudos to Tahsin for pinpointing these subtle breakages. Signed-off-by: Tejun Heo <tj@kernel.org> Fixes: d10c80955265 ("writeback: implement foreign cgroup inode bdi_writeback switching") Link: http://lkml.kernel.org/g/CAAeU0aMYeM_39Y2+PaRvyB1nqAPYZSNngJ1eBRmrxn7gKAt2Mg@mail.gmail.com Reported-and-diagnosed-by: Tahsin Erdogan <tahsin@google.com> Tested-by: Tahsin Erdogan <tahsin@google.com> Cc: stable@vger.kernel.org # v4.2+ Signed-off-by: Jens Axboe <axboe@fb.com>
| * writeback, cgroup: fix premature wb_put() in locked_inode_to_wb_and_lock_list()Tejun Heo2016-03-201-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | locked_inode_to_wb_and_lock_list() wb_get()'s the wb associated with the target inode, unlocks inode, locks the wb's list_lock and verifies that the inode is still associated with the wb. To prevent the wb going away between dropping inode lock and acquiring list_lock, the wb is pinned while inode lock is held. The wb reference is put right after acquiring list_lock citing that the wb won't be dereferenced anymore. This isn't true. If the inode is still associated with the wb, the inode has reference and it's safe to return the wb; however, if inode has been switched, the wb still needs to be unlocked which is a dereference and can lead to use-after-free if it it races with wb destruction. Fix it by putting the reference after releasing list_lock. Signed-off-by: Tejun Heo <tj@kernel.org> Fixes: 87e1d789bf55 ("writeback: implement [locked_]inode_to_wb_and_lock_list()") Cc: stable@vger.kernel.org # v4.2+ Tested-by: Tahsin Erdogan <tahsin@google.com> Signed-off-by: Jens Axboe <axboe@fb.com>
| * blk-mq: Use proper cpumask iteratorThomas Gleixner2016-03-203-17/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | queue_for_each_ctx() iterates over per_cpu variables under the assumption that the possible cpu mask cannot have holes. That's wrong as all cpumasks can have holes. In case there are holes the iteration ends up accessing uninitialized memory and crashing as a result. Replace the macro by a proper for_each_possible_cpu() loop and drop the unused macro blk_ctx_sum() which references queue_for_each_ctx(). Reported-by: Xiong Zhou <jencce.kernel@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jens Axboe <axboe@fb.com>
| * mtip32xx: fix checks for dma mapping errorsAlexey Khoroshilov2016-03-191-2/+2
| | | | | | | | | | | | | | | | | | | | exec_drive_taskfile() checks for dma mapping errors by comparison returned address with zero, while pci_dma_mapping_error() should be used. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: Jens Axboe <axboe@fb.com>
| * lightnvm: do not load L2P table if not supportedJavier González2016-03-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An Open-Channel SSD can work on two modes: (i) hybrid mode, where the L2P table is maintained both by the host and by the device; and (ii) full host-based, where the L2P table is uniquely maintained by the host. In the advent of a new target implementing the full host-based mode, do not assume that the L2P table must be loaded on the generic media manager; check device properties loaded on the identify command instead. Signed-off-by: Javier González <javier@cnexlabs.com> Moved into the following statement. Signed-off-by: Matias Bjørling <m@bjorling.me> Signed-off-by: Jens Axboe <axboe@fb.com>
| * lightnvm: do not reserve lun on l2p loadingJavier González2016-03-191-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the l2p table is loaded, addresses are checked for the lun they belong to and luns are reserved accordingly. This assumes that metadata is being stored in the backend device to recover the previous target configuration. Since this is not yet implemented, this check collides with some of the core initialization (e.g., sysblock initialization when a page is formed by several sectors). We take this check out and for now rely on that the right target will be created instead. When metadata is stored to recover a target, this check will come natural as part of the recovery strategy. Signed-off-by: Javier González <javier@cnexlabs.com> Signed-off-by: Matias Bjørling <m@bjorling.me> Signed-off-by: Jens Axboe <axboe@fb.com>
| * nvme: lightnvm: return ppa completion statusMatias Bjorling2016-03-192-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | PPAs sent to device is separately acknowledge in a 64bit status variable. The status is stored in DW0 and DW1 of the completion queue entry. Store this status inside the nvm_rq for further processing. This can later be used to implement retry techniques for failed writes and reads. Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Matias Bjørling <m@bjorling.me> Signed-off-by: Jens Axboe <axboe@fb.com>
| * lightnvm: add a bitmap of lunsWenwei Tao2016-03-194-29/+74
| | | | | | | | | | | | | | | | | | | | | | | | Add a bitmap of luns to indicate the status of luns: inuse/available. When create targets do the necessary check to avoid allocating luns that are already allocated. Signed-off-by: Wenwei Tao <ww.tao0320@gmail.com> Freed dev->lun_map if nvm_core_init later failed in the init process. Signed-off-by: Matias Bjørling <m@bjorling.me> Signed-off-by: Jens Axboe <axboe@fb.com>
| * lightnvm: specify target's logical address areaWenwei Tao2016-03-196-2/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can create more than one target on a lightnvm device by specifying its begin lun and end lun. But only specify the physical address area is not enough, we need to get the corresponding non- intersection logical address area division from the backend device's logcial address space. Otherwise the targets on the device might use the same logical addresses cause incorrect information in the device's l2p table. Signed-off-by: Wenwei Tao <ww.tao0320@gmail.com> Signed-off-by: Matias Bjørling <m@bjorling.me> Signed-off-by: Jens Axboe <axboe@fb.com>
| * null_blk: add lightnvm null_blk device to the nullb_listWenwei Tao2016-03-191-1/+2
| | | | | | | | | | | | | | | | | | | | After register null_blk devices into lightnvm, we forget to add these devices to the the nullb_list, makes them invisible to the null_blk driver. Signed-off-by: Wenwei Tao <ww.tao0320@gmail.com> Fixes: a514379b0c77 ("null_blk: oops when initializing without lightnvm") Signed-off-by: Jens Axboe <axboe@fb.com>
* | Merge tag 'for-linus-20160324' of git://git.infradead.org/linux-mtdLinus Torvalds2016-03-2561-592/+3524
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MTD updates from Brian Norris: "NAND: - Add sunxi_nand randomizer support - begin refactoring NAND ecclayout structs - fix pxa3xx_nand dmaengine usage - brcmnand: fix support for v7.1 controller - add Qualcomm NAND controller driver SPI NOR: - add new ls1021a, ls2080a support to Freescale QuadSPI - add new flash ID entries - support bottom-block protection for Winbond flash - support Status Register Write Protect - remove broken QPI support for Micron SPI flash JFFS2: - improve post-mount CRC scan efficiency General: - refactor bcm63xxpart parser, to later extend for NAND - add writebuf size parameter to mtdram Other minor code quality improvements" * tag 'for-linus-20160324' of git://git.infradead.org/linux-mtd: (72 commits) mtd: nand: remove kerneldoc for removed function parameter mtd: nand: Qualcomm NAND controller driver dt/bindings: qcom_nandc: Add DT bindings mtd: nand: don't select chip in nand_chip's block_bad op mtd: spi-nor: support lock/unlock for a few Winbond chips mtd: spi-nor: add TB (Top/Bottom) protect support mtd: spi-nor: add SPI_NOR_HAS_LOCK flag mtd: spi-nor: use BIT() for flash_info flags mtd: spi-nor: disallow further writes to SR if WP# is low mtd: spi-nor: make lock/unlock bounds checks more obvious and robust mtd: spi-nor: silently drop lock/unlock for already locked/unlocked region mtd: spi-nor: wait for SR_WIP to clear on initial unlock mtd: nand: simplify nand_bch_init() usage mtd: mtdswap: remove useless if (!mtd->ecclayout) test mtd: create an mtd_oobavail() helper and make use of it mtd: kill the ecclayout->oobavail field mtd: nand: check status before reporting timeout mtd: bcm63xxpart: give width specifier an 'int', not 'size_t' mtd: mtdram: Add parameter for setting writebuf size mtd: nand: pxa3xx_nand: kill unused field 'drcmr_cmd' ...
| * | mtd: nand: remove kerneldoc for removed function parameterBrian Norris2016-03-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'getchip' parameter is gone as of commit 9f3e04297b08 ("mtd: nand: don't select chip in nand_chip's block_bad op"), so kill the doc with it. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * | mtd: nand: Qualcomm NAND controller driverArchit Taneja2016-03-103-0/+2231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, MDM9x15 series. It exists as a sub block inside the IPs EBI2 (External Bus Interface 2) and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a broader interface for external slow peripheral devices such as LCD and NAND/NOR flash memory or SRAM like interfaces. We add support for the NAND controller found within EBI2. For the SoCs of our interest, we only use the NAND controller within EBI2. Therefore, it's safe for us to assume that the NAND controller is a standalone block within the SoC. The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and 16 bit correction/step) and RS ECC(4 bit correction/step) that covers main and spare data. The controller contains an internal 512 byte page buffer to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA for register read/write and data transfers. The controller performs page reads and writes at a codeword/step level of 512 bytes. It can support up to 2 external chips of different configurations. The driver prepares register read and write configuration descriptors for each codeword, followed by data descriptors to read or write data from the controller's internal buffer. It uses a single ADM DMA channel that we get via dmaengine API. The controller requires 2 ADM CRCIs for command and data flow control. These are passed via DT. The ecc layout used by the controller is syndrome like, but we can't use the standard syndrome ecc ops because of several reasons. First, the amount of data bytes covered by ecc isn't same in each step. Second, writing to free oob space requires us writing to the entire step in which the oob lies. This forces us to create our own ecc ops. One more difference is how the controller accesses the bad block marker. The controller ignores reading the marker when ECC is enabled. ECC needs to be explicity disabled to read or write to the bad block marker. The nand_bbt helpers library hence can't access BBMs for the controller. For now, we skip the creation of BBT and populate chip->block_bad and chip->block_markbad helpers instead. Reviewed-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | dt/bindings: qcom_nandc: Add DT bindingsArchit Taneja2016-03-101-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings document for the Qualcomm NAND controller driver. Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: nand: don't select chip in nand_chip's block_bad opArchit Taneja2016-03-105-26/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the arguments passed to struct nand_chip's block_bad op is 'getchip', which, if true, is supposed to get and select the nand device, and later unselect and release the device. This op is intended to be replaceable by drivers. The drivers shouldn't be responsible for selecting/unselecting chip. Like other ops, the chip should already be selected before the block_bad op is called. Remove the getchip argument from the block_bad op and nand_block_checkbad. Move the chip selection to nand_block_isbad, since it is the only caller to nand_block_checkbad which requires chip selection. Modify nand_block_bad (the default function for the op) such that it doesn't select the chip. Remove the getchip argument from the bad_block funcs in cafe_nand, diskonchip and docg4 drivers. Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: spi-nor: support lock/unlock for a few Winbond chipsBrian Norris2016-03-081-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are recent Winbond models that are known to have lock/unlock support via writing the Status Register, and that also support the TB (Top/Bottom) protection bit. Tested on w25q32dw. [Note on style: these entries are getting pretty long lines, so I picked a style that seems reasonable for splitting up the flags separate from the other mostly-similar fields.] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
| * | mtd: spi-nor: add TB (Top/Bottom) protect supportBrian Norris2016-03-082-7/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some flash support a bit in the status register that inverts protection so that it applies to the bottom of the flash, not the top. This yields additions to the protection range table, as noted in the comments. Because this feature is not universal to all flash that support lock/unlock, control it via a new flag. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
| * | mtd: spi-nor: add SPI_NOR_HAS_LOCK flagBrian Norris2016-03-081-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can't determine this purely by manufacturer type (see commit 67b9bcd36906 ("mtd: spi-nor: fix Spansion regressions (aliased with Winbond)")), and it's not autodetectable by anything like SFDP. So make a new flag for it. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
| * | mtd: spi-nor: use BIT() for flash_info flagsBrian Norris2016-03-081-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's a little easier to read and make sure there are no collisions (IMO). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
| * | mtd: spi-nor: disallow further writes to SR if WP# is lowBrian Norris2016-03-081-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Locking the flash is most useful if it provides real hardware security. Otherwise, it's little more than a software permission bit. A reasonable use case that provides real HW security might be like follows: (1) hardware WP# is deasserted (2) program flash (3) flash range is protected via status register (4) hardware WP# is asserted (5) flash protection range can no longer be changed, until WP# is deasserted In this way, flash protection is co-owned by hardware and software. Now, one would expect to be able to perform step (3) with ioctl(MEMLOCK), except that the spi-nor driver does not set the Status Register Protect bit (a.k.a. Status Register Write Disable (SRWD)), so even though the range is now locked, it does not satisfy step (5) -- it can still be changed by a call to ioctl(MEMUNLOCK). So, let's enable status register protection after the first lock command, and disable protection only when the flash is fully unlocked. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
| * | mtd: spi-nor: make lock/unlock bounds checks more obvious and robustBrian Norris2016-03-081-18/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a few different corner cases to the current logic that seem undesirable: * mtd_lock() with offs==0 trips a bounds issue on ofs - mtd->erasesize < 0 * mtd_unlock() on the middle of a flash that is already unlocked will return -EINVAL * probably other corner cases So, let's stop doing "smart" checks like "check the block below us", let's just do the following: (a) pass only non-negative offsets/lengths to stm_is_locked_sr() (b) add a similar stm_is_unlocked_sr() function, so we can check if the *entire* range is unlocked (and not just whether some part of it is unlocked) Then armed with (b), we can make lock() and unlock() much more symmetric: (c) short-circuit the procedure if there is no work to be done, and (d) check the entire range above/below This also aligns well with the structure needed for proper TB (Top/Bottom) support. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
| * | mtd: spi-nor: silently drop lock/unlock for already locked/unlocked regionBrian Norris2016-03-081-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If, for instance, the entire flash is already unlocked and I try to mtd_unlock() the entire device, I don't expect to see an EINVAL error. It should just silently succeed. Ditto for mtd_lock(). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
| * | mtd: spi-nor: wait for SR_WIP to clear on initial unlockBrian Norris2016-03-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixup a piece leftover by commit 32321e950d8a ("mtd: spi-nor: wait until lock/unlock operations are ready"). That commit made us wait for the WIP bit to settle after lock/unlock operations, but it missed the open-coded "unlock" that happens at probe() time. We should probably have this code utilize the unlock() routines in the future, to avoid duplication, but unfortunately, flash which need to be unlocked don't all have a proper ->flash_unlock() callback. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Stas Sergeev <stsp@users.sourceforge.net> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
| * | mtd: nand: simplify nand_bch_init() usageBoris BREZILLON2016-03-084-36/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_bch_init() requires several arguments which could directly be deduced from the mtd device. Get rid of those useless parameters. nand_bch_init() is also requiring the caller to provide a proper eccbytes value, while this value could be deduced from the ecc.size and ecc.strength value. Fallback to eccbytes calculation when it is set to 0. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: mtdswap: remove useless if (!mtd->ecclayout) testBoris BREZILLON2016-03-081-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the MTD device does not have OOB, the mtd->oobsize and mtd->oobavail fields are set to zero, and we are testing those values in the following test. Remove the useless if (!mtd->ecclayout) test. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: create an mtd_oobavail() helper and make use of itBoris BREZILLON2016-03-084-32/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, all MTD drivers/sublayers exposing an OOB area are doing the same kind of test to extract the available OOB size based on the mtd_info and mtd_oob_ops structures. Move this common logic into an inline function and make use of it. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Suggested-by: Priit Laes <plaes@plaes.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: kill the ecclayout->oobavail fieldBoris BREZILLON2016-03-0811-65/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ecclayout->oobavail is just redundant with the mtd->oobavail field. Moreover, it prevents static const definition of ecc layouts since the NAND framework is calculating this value based on the ecclayout->oobfree field. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: nand: check status before reporting timeoutBrian Norris2016-03-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit b70af9bef49b ("mtd: nand: increase ready wait timeout and report timeouts"), we increased the likelihood of scheduling during nand_wait(). This makes us more likely to hit the time_before(...) condition, since a lot of time may pass before we get scheduled again. Now, the loop was already buggy, since we don't check if the NAND is ready after exiting the loop; we simply print out a timeout warning. Fix this by doing a final status check before printing a timeout message. This isn't actually a critical bug, since the only effect is a false warning print. But too many prints never hurt anyone, did they? :) Side note: perhaps I'm not smart enough, but I'm not sure what the best policy is for this kind of loop; do we busy loop (i.e., no cond_resched()) to keep the lowest I/O latency (it's not great if the resched is delaying Richard's system ~400ms)? Or do we allow rescheduling, to play nice with the rest of the system (since some operations can take quite a while)? Reported-by: Richard Weinberger <richard@nod.at> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Richard Weinberger <richard@nod.at> Reviewed-by: Harvey Hunt <harvey.hunt@imgtec.com>
| * | mtd: bcm63xxpart: give width specifier an 'int', not 'size_t'Brian Norris2016-03-071-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes this warning: >> drivers/mtd/bcm63xxpart.c:175:4: note: in expansion of macro 'pr_err' pr_err("invalid rootfs address: %*ph\n", ^ >> include/linux/kern_levels.h:4:18: warning: field width specifier '*' expects argument of type 'int', but argument 2 has type 'long unsigned int' [-Wformat=] Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: mtdram: Add parameter for setting writebuf sizeAlexander Stein2016-03-071-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ubifs uses the write buffer size in recovery algorithm. When inspecting an unclean ubifs recovery fails with writebuf size 64 in mtdram while recovery on actual mtd device with writebuf size of 1024 succeeds. So add a parameter for setting this property. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: Richard Weinberger <richard@nod.at> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: nand: pxa3xx_nand: kill unused field 'drcmr_cmd'Brian Norris2016-03-071-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | With this removal, we don't need to 'get' the second DMA resource either, as it's also unused. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | Documentation: fsl-quadspi: Add optional propertiesYao Yuan2016-03-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add optional properties for QSPI: big-endian if the register is big endian on this platform. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | Documentation: fsl-quadspi: Add fsl, ls2080a-qspi compatible stringYao Yuan2016-03-071-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | new compatible string: "fsl,ls2080a-qspi". Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: spi-nor: fsl-quadspi: add support for layerscapeYao Yuan2016-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043a and LS2080A in the Layerscape family also support Freescale Quad SPI, make Quad SPI selectable for these hardwares. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: spi-nor: fsl-quadspi: add support for ls1021aYao Yuan2016-03-072-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021a also support Freescale Quad SPI controller. Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI selectable for LS1021A SOC hardwares. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Acked-by: Han xu <han.xu@freescale.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: spi-nor: fsl-quadspi: add big-endian supportYao Yuan2016-03-071-60/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add R/W functions for big- or little-endian registers: The qSPI controller's endian is independent of the CPU core's endian. So far, the qSPI have two versions for big-endian and little-endian. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Acked-by: Han xu <han.xu@freescale.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: spi-nor: add subsector flag to n25q128aEzequiel García2016-03-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Micron n25q128axx support subsector (4K) erase so let's update the flags. Tested on n25q128a13. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: nand: pxa3xx_nand: fix dmaengine initializationRobert Jarzmik2016-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the driver is initialized in a pure device-tree platform, the driver's probe fails allocating the dma channel : [ 525.624435] pxa3xx-nand 43100000.nand: no resource defined for data DMA [ 525.632088] pxa3xx-nand 43100000.nand: alloc nand resource failed The reason is that the DMA IO resource is not acquired through platform resources but by OF bindings. Fix this by ensuring that DMA IO resources are only queried in the non device-tree case. Fixes: 8f5ba31aa565 ("mtd: nand: pxa3xx-nand: switch to dmaengine") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: nand: sunxi: remove direct mtd->priv accessesBoris BREZILLON2016-03-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | mtd->priv is no longer pointing to the struct nand_chip it is attached to. Replace those accesses by mtd_to_nand() calls. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Fixes: 4be4e03efc7f ("mtd: nand: sunxi: add randomizer support") Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | jffs2: Improve post-mount CRC scan efficiencyDavid Woodhouse2016-02-293-25/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to finish doing the CRC checks before we can allow writes to happen, and we currently process the inodes in order. This means a call to jffs2_get_ino_cache() for each possible inode# up to c->highest_ino. There may be a lot of lookups which fail, if the inode# space is used sparsely. And the inode# space is *often* used sparsely, if a file system contains a lot of stuff that was put there in the original image, followed by lots of creation and deletion of new files. Instead of processing them numerically with a lookup each time, just walk the hash buckets instead. [fix locking typo reported by Dan Carpenter] Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-30 17:07:25 +0100