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* mm: frontswap: lazy initialization to allow tmem backends to build/run as ↵Dan Magenheimer2013-05-011-10/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | modules With the goal of allowing tmem backends (zcache, ramster, Xen tmem) to be built/loaded as modules rather than built-in and enabled by a boot parameter, this patch provides "lazy initialization", allowing backends to register to frontswap even after swapon was run. Before a backend registers all calls to init are recorded and the creation of tmem_pools delayed until a backend registers or until a frontswap store is attempted. Signed-off-by: Stefan Hengelein <ilendir@googlemail.com> Signed-off-by: Florian Schmaus <fschmaus@gmail.com> Signed-off-by: Andor Daam <andor.daam@googlemail.com> Signed-off-by: Dan Magenheimer <dan.magenheimer@oracle.com> [v1: Fixes per Seth Jennings suggestions] [v2: Removed FRONTSWAP_HAS_.. ] [v3: Fix up per Bob Liu <lliubbo@gmail.com> recommendations] [v4: Fix up per Andrew's comments] Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Bob Liu <lliubbo@gmail.com> Cc: Wanpeng Li <liwanp@linux.vnet.ibm.com> Cc: Dan Magenheimer <dan.magenheimer@oracle.com> Cc: Minchan Kim <minchan@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* fs/dcache.c: add cond_resched() to shrink_dcache_parent()Greg Thelen2013-05-011-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call cond_resched() in shrink_dcache_parent() to maintain interactivity. Before this patch: void shrink_dcache_parent(struct dentry * parent) { while ((found = select_parent(parent, &dispose)) != 0) shrink_dentry_list(&dispose); } select_parent() populates the dispose list with dentries which shrink_dentry_list() then deletes. select_parent() carefully uses need_resched() to avoid doing too much work at once. But neither shrink_dcache_parent() nor its called functions call cond_resched(). So once need_resched() is set select_parent() will return single dentry dispose list which is then deleted by shrink_dentry_list(). This is inefficient when there are a lot of dentry to process. This can cause softlockup and hurts interactivity on non preemptable kernels. This change adds cond_resched() in shrink_dcache_parent(). The benefit of this is that need_resched() is quickly cleared so that future calls to select_parent() are able to efficiently return a big batch of dentry. These additional cond_resched() do not seem to impact performance, at least for the workload below. Here is a program which can cause soft lockup if other system activity sets need_resched(). int main() { struct rlimit rlim; int i; int f[100000]; char buf[20]; struct timeval t1, t2; double diff; /* cleanup past run */ system("rm -rf x"); /* boost nfile rlimit */ rlim.rlim_cur = 200000; rlim.rlim_max = 200000; if (setrlimit(RLIMIT_NOFILE, &rlim)) err(1, "setrlimit"); /* make directory for files */ if (mkdir("x", 0700)) err(1, "mkdir"); if (gettimeofday(&t1, NULL)) err(1, "gettimeofday"); /* populate directory with open files */ for (i = 0; i < 100000; i++) { snprintf(buf, sizeof(buf), "x/%d", i); f[i] = open(buf, O_CREAT); if (f[i] == -1) err(1, "open"); } /* close some of the files */ for (i = 0; i < 85000; i++) close(f[i]); /* unlink all files, even open ones */ system("rm -rf x"); if (gettimeofday(&t2, NULL)) err(1, "gettimeofday"); diff = (((double)t2.tv_sec * 1000000 + t2.tv_usec) - ((double)t1.tv_sec * 1000000 + t1.tv_usec)); printf("done: %g elapsed\n", diff/1e6); return 0; } Signed-off-by: Greg Thelen <gthelen@google.com> Signed-off-by: Dave Chinner <david@fromorbit.com> Cc: <stable@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* fs/block_dev.c: no need to check inode->i_bdev in bd_forget()Yan Hong2013-05-011-5/+3
| | | | | | | | | Its only caller evict() has promised a non-NULL inode->i_bdev. Signed-off-by: Yan Hong <clouds.yan@gmail.com> Cc: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* inotify: invalid mask should return a error number but not set itZhao Hongjiang2013-05-011-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | When we run the crackerjack testsuite, the inotify_add_watch test is stalled. This is caused by the invalid mask 0 - the task is waiting for the event but it never comes. inotify_add_watch() should return -EINVAL as it did before commit 676a0675cf92 ("inotify: remove broken mask checks causing unmount to be EINVAL"). That commit removes the invalid mask check, but that check is needed. Check the mask's ALL_INOTIFY_BITS before the inotify_arg_to_mask() call. If none are set, just return -EINVAL. Because IN_UNMOUNT is in ALL_INOTIFY_BITS, this change will not trigger the problem that above commit fixed. [akpm@linux-foundation.org: fix build] Signed-off-by: Zhao Hongjiang <zhaohongjiang@huawei.com> Acked-by: Jim Somerville <Jim.Somerville@windriver.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Jerome Marchand <jmarchan@redhat.com> Cc: Eric Paris <eparis@parisplace.org> Cc: <stable@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* memory hotplug: fix warningsVincent Stehlé2013-05-011-1/+1
| | | | | | | | | | | | | | | Fix the following compilation warnings: mm/slab.c: In function `kmem_cache_init_late': mm/slab.c:1778:2: warning: statement with no effect [-Wunused-value] mm/page_cgroup.c: In function `page_cgroup_init': mm/page_cgroup.c:305:2: warning: statement with no effect [-Wunused-value] Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net> Cc: David Rientjes <rientjes@google.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* drivers/usb/storage/realtek_cr.c: fix buildAndrew Morton2013-05-011-4/+1
| | | | | | | | | | | | | | Remove unused local `us', which broke the build. Also nuke an unneeded cast. Repairs commit 191648d03d20 ("usb: storage: Convert US_DEBUGP to usb_stor_dbg"). Cc: Joe Perches <joe@perches.com> Acked-by: David Rientjes <rientjes@google.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge tag 'arm64-for-linus' of ↵Linus Torvalds2013-04-3038-90/+1410
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 Pull arm64 update from Catalin Marinas: "Main features: - Versatile Express SoC (model) support - DT files and Kconfig entries (there are no arch/arm64/mach-* directories). The bulk of the code has already been moved to drivers/ as part of the ARM SoC clean-up. - Basic multi-cluster support (CPU logical map initialised from the DT) - Simple earlyprintk support for UART 8250/16550 and FastModel console output - Optimised kernel library bitops and string functions. - Automatic initialisation of the irqchip and clocks via DT" * tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: (26 commits) arm64: Use acquire/release semantics instead of explicit DMB arm64: klib: bitops: fix unpredictable stxr usage arm64: vexpress: Enable ARMv8 RTSM model (SoC) support arm64: vexpress: Add dts files for the ARMv8 RTSM models arm64: Survive invalid cpu enable-methods arm64: mm: Correct show_pte behaviour arm64: Fix compat types affecting struct compat_stat arm64: Execute DSB during thread switching for TLB/cache maintenance arm64: compiling issue, need add include/asm/vga.h file arm64: smp: honour #address-size when parsing CPU reg property arm64: Define cmpxchg64 and cmpxchg64_local for outside use arm64: Define readq and writeq for driver module using arm64: Fix task tracing arm64: add explicit symbols to ESR_EL1 decoding arm64: Use irqchip_init() for interrupt controller initialisation arm64: psci: Use the MPIDR values from cpu_logical_map for cpu ids. arm64: klib: Optimised atomic bitops arm64: klib: Optimised string functions arm64: klib: Optimised memory functions arm64: head: match all affinity levels in the pen of the secondaries ...
| * arm64: Use acquire/release semantics instead of explicit DMBCatalin Marinas2013-04-301-4/+2
| | | | | | | | | | | | | | This patch changes the test_and_*_bit functions to use the load-acquire/store-release instructions instead of explicit DMB. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: klib: bitops: fix unpredictable stxr usageMark Rutland2013-04-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | We're currently relying on unpredictable behaviour in our testops (test_and_*_bit), as stxr is unpredictable when the status register and the source register are the same This patch changes reallocates the status register so as to bring us back into the realm of predictable behaviour. Boot tested on an AEMv8 model. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: vexpress: Enable ARMv8 RTSM model (SoC) supportCatalin Marinas2013-04-263-3/+16
| | | | | | | | | | | | | | | | | | This patch adds the necessary Kconfig entries to enable support for the ARMv8 software model (Versatile Express platform) together with the defconfig update. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
| * arm64: vexpress: Add dts files for the ARMv8 RTSM modelsPawel Moll2013-04-265-0/+638
| | | | | | | | | | | | | | | | This patch adds the DTS files for the ARMv8 RTSM and Foundation models. Signed-off-by: Pawel Moll <Pawel.Moll@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
| * arm64: Survive invalid cpu enable-methodsMark Rutland2013-04-251-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, if you pass the kernel a dtb where a cpu node has an unsupported enable-method property (e.g. "not-psci"), it'll explode horribly, as it iterates over the enable_ops array incorrectly. It increments the pointer *at* the current element, rather than incrementing the pointer *to* the current element. As the first two elements pointed to structures that were contiguous in memory, this happened to be equivalent. However the third element is NULL, so when the list is exhausted, smp_get_enable_ops generates the wrong pointer, and dereferences an arbitrary portion of memory, which currently happens to contain zero. This patch fixes this by indirecting the pointer one level, so we iterate over the array elements correctly, avoiding the below panic: Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: mm: Correct show_pte behaviourSteve Capper2013-04-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | show_pte makes use of the *_none_or_clear_bad style functions. If a pgd, pud or pmd is identified as being bad, it will then be cleared. As show_pte appears to be called from either the user or kernel fault handlers this side effect can lead to unpredictable behaviour; especially as TLB entries are not invalidated. This patch removes the page table sanitisation from show_pte. If a bad pgd, pud or pmd is encountered it is left unmodified. Signed-off-by: Steve Capper <steve.capper@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: Fix compat types affecting struct compat_statCatalin Marinas2013-04-251-9/+13
| | | | | | | | | | | | | | | | | | The compat_stat structure doesn't match the arch/arm/ struct stat definition. This patch fixes the compat types and struct compat_stat definition accordingly. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Will Deacon <will.deacon@arm.com>
| * arm64: Execute DSB during thread switching for TLB/cache maintenanceCatalin Marinas2013-04-251-0/+6
| | | | | | | | | | | | | | | | | | The DSB following TLB or cache maintenance ops must be run on the same CPU. With kernel preemption enabled or for user-space cache maintenance this may not be the case. This patch adds an explicit DSB in the __switch_to() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: compiling issue, need add include/asm/vga.h fileChen Gang2013-04-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | For compiling with allmodconfig, need vga.h file, so generate it which just only include the asm-generic one. It is firstly used by drivers/gpu/drm/drm_irq.c. The related error: include/video/vga.h:22:21: fatal error: asm/vga.h: No such file or directory Signed-off-by: Chen Gang <gang.chen@asianux.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: smp: honour #address-size when parsing CPU reg propertyWill Deacon2013-04-251-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For systems where the top 32-bits of the MPIDR are all zero, we should allow the device-tree to specify an #address-size of 0x1 for the CPU reg property and then zero extend the value there. Without this patch, kvmtool breaks with the recent mpidr parsing code introduced in 4c7aa0021356 ("arm64: kernel: initialise cpu_logical_map from the DT"). Acked-by: Javi Merino <javi.merino@arm.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: Define cmpxchg64 and cmpxchg64_local for outside useChen Gang2013-04-231-0/+3
| | | | | | | | | | | | | | | | Drivers use cmpxchg64, cmpxchg64_local to perform 64-bit operation, so they can cross 32-bit and 64-bit platforms (it is a standard way). Signed-off-by: Chen Gang <gang.chen@asianux.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: Define readq and writeq for driver module usingChen Gang2013-04-191-0/+4
| | | | | | | | | | | | | | | | | | | | when compiling with allmodconfig, CONFIG_64BIT=y the file drivers/base/regmap/regmap-mmio.c will use readq and writeq so we need implement these functions. Signed-off-by: Chen Gang <gang.chen@asianux.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: Fix task tracingChristopher Covington2013-04-171-1/+1
| | | | | | | | | | | | | | | | | | For accurate accounting call contextidr_thread_switch before a task is scheduled, rather than after, when the 'next' variable has a different meaning since we switched the stacks. Signed-off-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: add explicit symbols to ESR_EL1 decodingMarc Zyngier2013-04-172-26/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | The ESR_EL1 decoding process is a bit cryptic, and KVM has also a need for the same constants. Add a new esr.h file containing the appropriate exception classes constants, and change entry.S to use it. Fix a small bug in the EL1 breakpoint check while we're at it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * Merge branch 'arm64-klib' into upstreamCatalin Marinas2013-03-2812-18/+418
| |\ | | | | | | | | | | | | | | | | | | * arm64-klib: arm64: klib: Optimised atomic bitops arm64: klib: Optimised string functions arm64: klib: Optimised memory functions
| | * arm64: klib: Optimised atomic bitopsCatalin Marinas2013-03-214-32/+94
| | | | | | | | | | | | | | | | | | | | | This patch implements the AArch64-specific atomic bitops functions using exclusive memory accesses to avoid locking. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| | * arm64: klib: Optimised string functionsCatalin Marinas2013-03-215-1/+95
| | | | | | | | | | | | | | | | | | | | | This patch introduces AArch64-specific string functions (strchr, strrchr). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| | * arm64: klib: Optimised memory functionsCatalin Marinas2013-03-218-2/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces AArch64-specific memory functions (memcpy, memmove, memchr, memset). These functions are not optimised for any CPU implementation but can be used as a starting point once hardware is available. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | arm64: Use irqchip_init() for interrupt controller initialisationCatalin Marinas2013-03-264-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch uses the generic irqchip_init() function for initialising the interrupt controller on arm64. It also adds several definitions required by the ARM GIC irqchip driver but does not enable ARM_GIC yet. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | arm64: psci: Use the MPIDR values from cpu_logical_map for cpu ids.Liviu Dudau2013-03-261-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | With the (re)introduction of cpu_logical_map in arm64 we switch to the use of MPIDR values to identify CPUs. Update the psci code to do that. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | arm64: head: match all affinity levels in the pen of the secondariesJavi Merino2013-03-202-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reg property of the cpu nodes in the DT now contains all the affinity levels in (MPIDR[39:32] and MPIDR[23:0]) and that's what boot_secondary() writes in the pen, so increase the mask in secondary_holding_pen accordingly. Signed-off-by: Javi Merino <javi.merino@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | arm64: kernel: initialise cpu_logical_map from the DTJavi Merino2013-03-204-7/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting the kernel, the cpu logical id map must be initialised using device tree data passed by FW or through an embedded blob. This patch parses the reg property in device tree "cpu" nodes, retrieves the corresponding CPUs hardware identifiers (MPIDR) and initialises the cpu logical map accordingly. The device tree HW identifiers are considered valid if all CPU nodes contain a "reg" property, there are no duplicate "reg" entries and the DT defines a CPU node whose "reg" property defines affinity levels that matches those of the boot CPU. The primary CPU is assigned cpu logical number 0 to keep the current convention valid. Based on a0ae02405076ac32bd17ece976e914b5b6075bb0 (ARM: kernel: add device tree init map function). Signed-off-by: Javi Merino <javi.merino@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | arm64: kernel: make the pen of the secondary a 64-bit unsigned valueJavi Merino2013-03-202-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Change the prototype of write_pen_release() accordingly and clarify that's holding the hardware id of the secondary that's going to boot. This is in preparation of getting HWIDs parsed from the DT. Signed-off-by: Javi Merino <javi.merino@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | arm64: Initialise the clocks described via DTCatalin Marinas2013-03-201-0/+8
| | | | | | | | | | | | | | | | | | | | | This patch adds an arch_initcall() for the of_clk_init() clock initialisation. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | arm64: add support for 8250/16550 earlyprintkAnup Patel2013-03-201-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for using earlyprintk with 8250/16550 UART ports. The 8250/16550 UART can either have 8-bit or 32-bit aligned registers which is HW vendor dependent. Kernel args for 8-bit aligned regs: earlyprintk=uart8250-8bit,<phys_address> Kernel args for 32-bit aligned regs: earlyprintk=uart8250-32bit,<phys_address> Signed-off-by: Anup Patel <anup.patel@linaro.org> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | arm64: early_printk: add support for FastModel console outputMarc Zyngier2013-03-201-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable early_printk to use the FastModel semihosting to output the early kernel messages. Works both for host and guest kernels. To use this feature, pass "early_printk=smh" to the kernel. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | arm64: add read_cpuid_{implementor,part_number,mpidr}Marc Zyngier2013-03-201-0/+22
| |/ | | | | | | | | | | | | | | | | In order to preserve some kind of source compatibility between arm and arm64, introduce read_cpuid_{implementor,part_number,mpidr} which are used on KVM to find out which CPU we're running on. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | Merge tag 'metag-for-v3.10-rc1' of ↵Linus Torvalds2013-04-3023-40/+407
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag Pull arch/metag update from James Hogan: - Various fixes for the interrupting perf counter handling in metag's perf backend. - Add OProfile support based on perf. - Sets up cache partitions for SMP so bootloader doesn't have to. - Patch from Paul Bolle to remove ARCH_POPULATES_NODE_MAP again (touches microblaze too). - Add TLS pointer regset to metag ptrace api. - Add exported metag DSP extended context handling header <asm/ech.h>. - Increase defconfig log buffer size to 128KiB. - Various fixes, typos, missing exports. * tag 'metag-for-v3.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag: metag: defconfigs: increase log buffer 8KiB => 128KiB metag: avoid unnecessary builtin dtb rebuilds metag: add exported <asm/ech.h> for extended context handling metag: export _metag_da_present and cpu_2_hwthread_id metag: ptrace: Implement NT_METAG_TLS memblock: Kill ARCH_POPULATES_NODE_MAP once more metag: cachepart: fix get_global_dcache_size() typo metag: cachepart: take into account small cache bits metag: smp: copy cache partition and enable GCOn metag: OProfile support metag: perf: prepare for use by oprofile metag: perf: don't reset TXTACTCYC metag: perf: use hard_processor_id() to get thread metag: perf: fix frequency sampling (dynamic period) metag: perf: add missing prev_count updates metag: perf: fixes for interrupting perf counters metag: perf: fix wrap handling in delta calculation metag: perf: fix core internal / perf channel mux
| * | metag: defconfigs: increase log buffer 8KiB => 128KiBJames Hogan2013-04-253-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Meta defconfigs set the log buffer size to just 8KiB, but with the fairly recent conversion of the kernel log buffer into a structured binary format, log messages appear to consume more space in the buffer, and in some cases it's not big enough to store the entire boot log. Therefore switch all the defconfigs to use the default size of 128KiB. Signed-off-by: James Hogan <james.hogan@imgtec.com>
| * | metag: avoid unnecessary builtin dtb rebuildsJames Hogan2013-04-221-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The builtin .dtb.S intermediate file needs to be marked with .SECONDARY so that it isn't automatically deleted (which causes it to be regenerated on every build). Also add *.dtb.S to clean-files so it gets cleaned up by make clean. Similarly, if the specified builtin dtb isn't already in dtb-y (e.g. imported into the tree and specified in CONFIG_METAG_BUILTIN_DTB_NAME) it too will be treated as an intermediate and deleted automatically (again causing it to be regenerated on every build), so add it to dtb-y so it gets added to targets and the dtbs target. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Vineet Gupta <Vineet.Gupta1@synopsys.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Michal Marek <mmarek@suse.cz> Cc: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | metag: add exported <asm/ech.h> for extended context handlingJames Hogan2013-03-272-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an exported header file <asm/ech.h> containing the definitions of some bits which can be set in D0.8 to indicate to the kernel that certain DSP state should be preserved. The definitions have the same names and values as the ones in the kernel-internal <asm/tbx.h>, to make it easier for DSP assembly code to be compatible between Linux and non-Linux operating systems. Signed-off-by: James Hogan <james.hogan@imgtec.com>
| * | metag: export _metag_da_present and cpu_2_hwthread_idJames Hogan2013-03-272-0/+3
| | | | | | | | | | | | | | | | | | | | | Export the symbols _metag_da_present and cpu_2_hwthread_id to modules (GPL only) to allow the imgdafs file system to be built as a module. Signed-off-by: James Hogan <james.hogan@imgtec.com>
| * | metag: ptrace: Implement NT_METAG_TLSPaul Clothier2013-03-272-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement functionality to get the TLS pointer for the metag architecture using regsets. This provides multi-threaded debug support for GDB. Signed-off-by: Paul Clothier <Paul.Clothier@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com>
| * | memblock: Kill ARCH_POPULATES_NODE_MAP once morePaul Bolle2013-03-202-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig symbol ARCH_POPULATES_NODE_MAP was killed in v3.3. After that it popped up again in microblaze and metag. Nobody noticed, probably because these Kconfig symbols are entirely unused and these architectures both select HAVE_MEMBLOCK_NODE_MAP. Anyhow, these two entries can also be killed. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Acked-by: Michal Simek <monstr@monstr.eu> Signed-off-by: James Hogan <james.hogan@imgtec.com>
| * | metag: cachepart: fix get_global_dcache_size() typoJames Hogan2013-03-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compilation is broken when the kernel is destined to live in the global part of the virtual address space: arch/metag/kernel/cachepart.c In function 'get_thread_cache_size': arch/metag/kernel/cachepart.c +71 : error: implicit declaration of function 'get_global_dache_size' Fix the typo. Signed-off-by: James Hogan <james.hogan@imgtec.com>
| * | metag: cachepart: take into account small cache bitsJames Hogan2013-03-151-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | The CORE_CONFIG2 register has bits to indicate that the data or code cache is small, i.e. that the size described in the field should be divided by 64. Take this into account in get_icache_size() and get_dcache_size(). Signed-off-by: James Hogan <james.hogan@imgtec.com>
| * | metag: smp: copy cache partition and enable GCOnJames Hogan2013-03-153-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When starting an SMP hardware thread, copy the cache partition configuration so that the threads share the same cache partitions. Also enable the GCOn bit if running in the local half of the virtual address space to enable coherency of shared local cache partitions. An atomic unlock system event is executed by the new cpu before any memory is read to ensure that any writes made by the boot cpu prior to full coherency taking effect are visible to the new cpu. This is to allow SMP to work even when the bootloader hasn't configured the caches for coherency. A log message is printed to describe the cache partition changes so that the user is aware of potential unintentional cache wastage if they've configured the cache partitions in the wrong way. Signed-off-by: James Hogan <james.hogan@imgtec.com>
| * | metag: OProfile supportJames Hogan2013-03-156-0/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add OProfile support for metag, using the perf backend, and falling back to generic timer based sampling if perf counter interrupt support is disabled. The oprofile code prepends "metag/" to the perf pmu name to give "metag/meta2" which is more consistent with other oprofile arch names. The backtrace code makes use of <asm/stacktrace.h> for kernel backtracing, and a simple frame pointer walk for userland backtracing. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Robert Richter <rric@kernel.org> Cc: oprofile-list@lists.sf.net
| * | metag: perf: prepare for use by oprofileJames Hogan2013-03-151-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow our perf_events code to work with oprofile the PERF_TYPE_RAW event type attribute is implemented, which allows the internal encoding of events to be used externally (this requires some tweaks so that it handles invalid event types more gracefully), and perf_pmu_name() is adjusted to return metag_pmu->name instead of metag_pmu->pmu.name (which is changed to "meta2"). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: Robert Richter <rric@kernel.org> Cc: oprofile-list@lists.sf.net
| * | metag: perf: don't reset TXTACTCYCJames Hogan2013-03-151-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The thread active cycle counter TXTACTCYC is used in __delay so it shouldn't really be reset to zero by perf. Fix perf to just read the value, and instead of clearing it, record the prev_count value in enable_counter so that the delta calculations know about the previous value. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
| * | metag: perf: use hard_processor_id() to get threadJames Hogan2013-03-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use hard_processor_id() to get the current thread number rather than get_cpu() and the hardware thread mapping. There was no matching put_cpu(), and in any case this should be slightly more efficient. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
| * | metag: perf: fix frequency sampling (dynamic period)James Hogan2013-03-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Frequency sampling mode dynamically adjusts the sample period so as to hit a particular frequency of samples. The sample period starts at just 1 and then gets increased if the interrupt rate is too high. This changed sample period needs handling in metag_pmu_event_set_period to update period_left (as the ARM equivalent does). The calculated delta also needs subtracting from period_left in metag_pmu_event_update in order to hit the conditional blocks in metag_pmu_event_set_period which update last_period (which is used in the dynamic sampling period calculation). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
| * | metag: perf: add missing prev_count updatesJames Hogan2013-03-151-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prev_count needs setting when changing the counter value, otherwise the calculated delta will be wrong, which for frequency sampling (dynamic period sampling) results in sampling at too high a frequency. For non-interrupting performance counters it should also be cleared when enabling the counter since the write to the PERF_COUNT register will clear the perf counter. This also includes a minor change to remove the u64 cast from the metag_pmu->write() call as metag_pmu->write() takes a u32 anyway, and in any case GCC is smart enough to optimise away the cast. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-17 21:29:41 +0100