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* Merge branch 'reset/for_v3.10' of git://git.pengutronix.de/git/pza/linux ↵Olof Johansson2013-04-138-0/+459
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/drivers From Philipp Zabel, this is a series that adds a simple API for devices to request being reset by a separate reset controller hardware, and it implements reset signal device tree bindings. * 'reset/for_v3.10' of git://git.pengutronix.de/git/pza/linux: reset: NULL deref on allocation failure reset: Add reset controller API dt: describe base reset signal binding Signed-off-by: Olof Johansson <olof@lixom.net>
| * reset: NULL deref on allocation failureDan Carpenter2013-04-121-1/+1
| | | | | | | | | | | | | | "rstc" is NULL here and we should use "rcdev" instead of "rstc->rcdev". Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| * reset: Add reset controller APIPhilipp Zabel2013-04-127-0/+384
| | | | | | | | | | | | | | | | | | | | | | | | This adds a simple API for devices to request being reset by separate reset controller hardware and implements the reset signal device tree binding. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz>
| * dt: describe base reset signal bindingStephen Warren2013-04-121-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This binding is intended to represent the hardware reset signals present internally in most IC (SoC, FPGA, ...) designs. It consists of a binding for a reset controller device (provider), and a pair of properties, "resets" and "reset-names", to link a device node (consumer) to its reset controller via phandle, similarly to the clock and interrupt bindings. The reset controller has all information necessary to reset the consumer device. That could be provided via device tree, or it could be implemented in hardware. The aim is to enable device drivers to request a framework API to issue a reset simply by providing their struct device pointer as the most common case. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Acked-by: Rob Herring <rob.herring@calxeda.com>
* | irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructureTony Prisk2013-04-135-19/+10
| | | | | | | | | | | | | | | | | | This patch moves the arch-vt8500 irq code to drivers/irqchip and converts it to use the new IRQCHIP_DECLARE and irqchip_init. This allows the removal of some more functions from common.h Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Olof Johansson <olof@lixom.net>
* | Merge tag 'timer-samsung-for-v3.10' of ↵Arnd Bergmann2013-04-091-2/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers From Kukjin Kim <kgene.kim@samsung.com>: including fix for GENERIC_GPIO based on previous pull-request for timer-samsung * tag 'timer-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: SAMSUNG: change GENERIC_GPIO to ARCH_REQUIRE_GPIOLIB Signed-off-by: Arnd Bergmann <arnd@anrdb.de>
| * | ARM: SAMSUNG: change GENERIC_GPIO to ARCH_REQUIRE_GPIOLIBKukjin Kim2013-04-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When I applied regarding samsung-time patches, the "select GENERIC_GPIO" has been added wrong, so this patch fixes that. And since the GENERIC_GPIO in arch/arm/ will be gone away, this adds ARCH_REQUIRE_GPIOLIB for S3C24XX and S5PC100 instead. Reported-by: Alexandre Courbot <gnurou@gmail.com> Cc: Romain Naour <romain.naour@openwide.fr> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | Merge tag 'pmu-exynos-for-v3.10' of ↵Arnd Bergmann2013-04-096-22/+113
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers From Kukjin Kim <kgene.kim@samsung.com>: add support arm-pmu for exynos4 and exynos5250 * tag 'pmu-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Add arm-pmu DT binding for exynos421x ARM: EXYNOS: Add arm-pmu DT binding for exynos5250 ARM: EXYNOS: Enable PMUs for exynos4 irqchip: exynos-combiner: Correct combined IRQs for exynos4 irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | ARM: EXYNOS: Add arm-pmu DT binding for exynos421xChanho Park2013-04-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a arm-pmu node to bind device tree for exynos4210. The exynos4210 and 4212 have two cpus which includes a pmu. In contrast, the exynos4412 has 4 cpus and pmus. We need to define two more pmus for this type board. However, supporting arm-pmu for the exynos4412 will handle it later because there is no dts support for 4412 based board. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: EXYNOS: Add arm-pmu DT binding for exynos5250Chanho Park2013-04-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables arm-pmu to bind device tree for exynos5250. The exynos5250 has two pmus which have combiner irq type. Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: EXYNOS: Enable PMUs for exynos4Chanho Park2013-04-083-3/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch defines irq numbers of ARM performance monitoring unit for exynos4. Firs of all, we need to fix IRQ_PMU correctly and to split pmu initialization of exynos from plat-samsung for easily defining it. The number of CPU cores and PMU irq numbers are vary according to soc types. So, we need to identify each soc type using soc_is_xxx function and to define the pmu irqs dynamically. For example, the exynos4412 has 4 cpu cores and pmus. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | irqchip: exynos-combiner: Correct combined IRQs for exynos4Chanho Park2013-04-082-14/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch corrects combined IRQs for exynos4 series platform. The exynos4412 has four extra combined irq group and the exynos4212 has two more combined irqs than exynos4210. Each irq is mapped to IRQ_SPI(xx). Unfortunately, extra 4 combined IRQs isn't sequential. So, we need to map the irqs manually. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: changes moved into drivers/irqchip/] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irqChanho Park2013-04-081-5/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds set_irq_affinity function for combiner_irq. We need this function to enable a arm-pmu because the pmu of exynos has combined type irqs. Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: changes moved into drivers/irqchip/] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | | Merge tag 'clk-exynos-for-v3.10' of ↵Arnd Bergmann2013-04-0953-4117/+4655
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers From Kukjin Kim <kgene.kim@samsung.com>: add suppport common clock framework for exynos * tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (73 commits) ARM: EXYNOS: fix compilation error introduced due to common clock migration clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} clk: exynos4: export clocks required for fimc-is clk: samsung: Fix compilation error clk: exynos5250: register display block gate clocks to common clock framework clk: exynos4: Add support for SoC-specific register save list clk: exynos4: Add missing registers to suspend save list clk: exynos4: Remove E4X12 prefix from SRC_DMC register clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register clk: exynos4: Add E4210 prefix to LCD1 clock registers clk: exynos4: Remove SoC-specific registers from save list clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions clk: exynos4: Define {E,V}PLL registers clk: exynos4: Add missing mout_sata on Exynos4210 clk: exynos4: Add missing CMU_TOP and ISP clocks clk: exynos4: Add G3D clocks clk: exynos4: Add camera related clock definitions clk: exynos4: Export mout_core clock of Exynos4210 clk: samsung: Remove unimplemented ops for pll clk: exynos4: Export clocks used by exynos cpufreq drivers ... [arnd: add missing #address-cells property in mshc DT node] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | Merge commit 'v3.9-rc5' into next/clk-exynosKukjin Kim2013-04-081122-6045/+12783
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/boot/dts/exynos4.dtsi arch/arm/boot/dts/exynos5440.dtsi
| * | | | ARM: EXYNOS: fix compilation error introduced due to common clock migrationThomas Abraham2013-04-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The functions exynos4_clk_init and exynos4_clk_register_fixed_ext are applicable only on Exynos4 non-dt platforms. But when building Exynos5 platforms without including Exynos4 platforms, the following errors show up. arch/arm/mach-exynos/built-in.o: In function `exynos_init_time': arch/arm/mach-exynos/common.c:446: undefined reference to `exynos4_clk_init' arch/arm/mach-exynos/common.c:447: undefined reference to `exynos4_clk_register_fixed_ext' Fix this compilation errors by marking these calls as Exynos4 specific. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}Tushar Behera2013-04-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide) instead of RATIO bit-field (4-bit wide) for dividing clock rate. With current common clock setup, we are using RATIO bit-field which is creating FIFO read errors while accessing eMMC. Changing over to use PRE_RATIO bit-field fixes this issue. dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020) mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 end_request: I/O error, dev mmcblk0, sector 1 Signed-off-by: Tushar Behera <tushar.behera@linaro.org> CC: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: export clocks required for fimc-isSylwester Nawrocki2013-04-082-21/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1, ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1, DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are available to the consumers (Exynos4x12 FIMC-IS subsystem). While at it, indentation of the mux clocks table is corrected. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: samsung: Fix compilation errorSachin Kamat2013-04-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes the below compilation error during non-dt build. drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext': drivers/clk/samsung/clk.c:252:2: error: implicit declaration of function 'for_each_matching_node_and_match' [-Werror=implicit-function-declaration] drivers/clk/samsung/clk.c:252:60: error: expected ';' before '{' token Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos5250: register display block gate clocks to common clock frameworkLeela Krishna Amudala2013-04-042-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi. Register it to common clock framework. Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Add support for SoC-specific register save listTomasz Figa2013-04-045-8/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Add missing registers to suspend save listTomasz Figa2013-04-041-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Remove E4X12 prefix from SRC_DMC registerTomasz Figa2013-04-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This register is present on all Exynos4 SoCs and so the prefix is misleading. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Add E4210 prefix to GATE_IP_PERIR registerTomasz Figa2013-04-041-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This definition is specific for Exynos4210 (which has another location than the same register on Exynos4x12 SoCs) and so needs appropriate prefix. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Add E4210 prefix to LCD1 clock registersTomasz Figa2013-04-041-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds E4210 prefix to all registers related to LCD1 clock domain, because they are present only on Exynos4210. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Remove SoC-specific registers from save listTomasz Figa2013-04-041-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current clock save list is shared for all Exynos4 SoCs, so it must contain only registers present in all supported SoCs, because accessing unavailable registers might have undefined effect. This patch removes registers specific for particular SoCs from shared save list, as they should be supported by separate SoC-specific lists. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Use SRC_MASK_PERIL{0,1} definitionsTomasz Figa2013-04-041-11/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are definitions of SRC_MASK_PERIL0 and SRC_MASK_PERIL1 registers, but they are not used for clock definitions. This patch modifies related clock definitions to use defined macros instead of numeric offsets. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Define {E,V}PLL registersTomasz Figa2013-04-041-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds preprocessor definitions of EPLL and VPLL registers and replaces all occurences of offsets of related registers with new definitions. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Add missing mout_sata on Exynos4210Tomasz Figa2013-04-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing mout_sata that is a parent of div_sata clock. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Add missing CMU_TOP and ISP clocksAndrzej Hajda2013-04-042-3/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Add G3D clocksTomasz Figa2013-04-042-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clocks needed for G3D block present on Exynos 4 SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Add camera related clock definitionsSylwester Nawrocki2013-04-042-17/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds several gate and mux clocks related to camera and ISP blocks. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Export mout_core clock of Exynos4210Tomasz Figa2013-04-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables clock lookup registration for mout_core clock used in Exynos4210 cpufreq driver. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: samsung: Remove unimplemented ops for pllTomasz Figa2013-04-041-80/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unimplemented clock operations should be simply omitted instead of returning error values. This patch removes unimplemented PLL operations to fix problems caused by returning error code in round_rate callback. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Export clocks used by exynos cpufreq driversLukasz Majewski2013-04-042-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch exports clocks used by Exynos cpufreq drivers to allow lookup using device tree. (Support to cpufreq drivers will be added in further patches.) Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Move dac and mixer to Exynos4210-specific clocksTomasz Figa2013-04-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sclk_dac and sclk_mixer clocks are not present on Exynos4x12. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Export sclk_pcm0Tomasz Figa2013-04-042-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock is used by PCM interface 0. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Add missing sclk_audio0 clockTomasz Figa2013-04-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock is a parent of mout_spdif and sclk_pcm0. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Add missing mout_mipihsi clockTomasz Figa2013-04-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing output of mux MIPIHSI which is needed for div_mipihsi clock. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Use mout_mpll_user_* on Exynos4x12Tomasz Figa2013-04-042-61/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of sclk_mpll as one of their parents. This patch moves such clocks from common array into SoC-specific arrays and adjusts their parent lists respectively. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: exynos4: Correct sclk_mfc clock definitionSylwester Nawrocki2013-04-042-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock must be exported to allow lookup using device tree. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: samsung: add infrastructure to add separate aliasesHeiko Stuebner2013-03-282-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code adds aliases, if necessary, directly when adding the clock, limiting the number of possible aliases to one. Some platforms need more than one alias, like the hsmmc pclocks on s3c2416 which need a "hsmmc" and "mmc_busclk.0" alias for the s3c- sdhci driver. Therefore add the possibility to separately add clock aliases for previously created clocks. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: samsung: always allocate the clk_tableHeiko Stuebner2013-03-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed to allow looking up previous created clocks when adding separate aliases to them. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: samsung: fix pm init on non-dt platformsHeiko Stueber2013-03-281-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock_init function checked for a dt node, returning immediately for non-dt machines. This let to the suspend init never being reached on those non-DT machines. So fix this by moving the pm init code above the check. Signed-off-by: Heiko Stueber <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | clk: samsung: register clk_div_tables for divider clocksHeiko Stuebner2013-03-282-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some Samsung platforms divider clocks only use specific divider combinations like the armdiv on s3c2443 and s3c2416. For these usecases the generic divider clock already provides the option of providing a lookup table mapping register values to divider values. Therefore add a new field to samsung_div_clock and if filled with a table, use clk_register_divider_table instead of clk_register_divider to register a divider clock Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | ARM: dts: add board specific fixed rate clock nodes for Exynos based platformsThomas Abraham2013-03-2510-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock frequency of xxti and xusbxti clocks is dependent on the frequency of the on-board oscillator that is used to generate these clocks. So allow the frequency of these clocks to be specfied from device tree. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | ARM: dts: add clock provider information for all controllers in Exynos5440 SoCThomas Abraham2013-03-251-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For all supported peripheral controllers on Exynos5440, add clock lookup information. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | ARM: dts: add clock provider information for all controllers in Exynos5250 SoCThomas Abraham2013-03-251-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For all supported peripheral controllers on Exynos5250, add clock lookup information. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | ARM: dts: add clock provider information for all controllers in Exynos4 SoCsThomas Abraham2013-03-253-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For all supported peripheral controllers on Exynos4 SoCs, add clock lookup information. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | | ARM: dts: add Exynos4 and Exynos5 clock controller nodesThomas Abraham2013-03-254-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock controller nodes for EXYNOS4210, EXYNOS4x12, EXYNOS5250 and EXYNOS5440 SoCs. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-10 13:46:06 +0100