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* ARM: clk-imx6sl: refine clock tree for SSIShengjiu Wang2014-09-162-4/+14
| | | | | | | Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driverShawn Guo2014-09-161-37/+0
| | | | | | | | Since ENABLE and BYPASS bits of PLLs are now implemented as separate gate and mux clocks by clock drivers, the code handling these two bits can be removed from clk-pllv3 driver. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6sx: add BYPASS support for PLL clocksShawn Guo2014-09-162-10/+78
| | | | | | | | This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sx. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6sl: add BYPASS support for PLL clocksShawn Guo2014-09-162-9/+87
| | | | | | | | This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sl. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: add BYPASS support for PLL clocksShawn Guo2014-09-162-11/+83
| | | | | | | | | | | | The imx6q clock driver currently hard-codes all PLL clocks to source from OSC24M without BYPASS support. The patch adds the missing lvds_in clock which is mutually exclusive with lvds_gate, and implements BYPASS and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits are implemented as mux clocks, and ENABLE bit of PLL clocks is implemented as a gate clock after BYPASS mux. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: add an exclusive gate clock typeShawn Guo2014-09-163-1/+99
| | | | | | | | | | | | | | | | There are a couple of gate clocks are mutually exclusive on i.MX6, i.e. LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously. This patches adds an exclusive gate clock type specifically for such case. The clock driver will need to call imx_clk_gate_exclusive() to register a gate clock with parameter exclusive_mask indicating the mask of gate bits which are mutually exclusive to this gate clock. Right now, it only handles the exclusive gate clocks which are defined in a single hardware register, which is the case we're running into today. But it can be extended to handle exclusive gate clocks defined in different registers later if needed. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: clk-imx6q: refine clock tree for SSIShengjiu Wang2014-09-161-3/+9
| | | | | | | Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: clk-imx6q: refine clock tree for ASRCShengjiu Wang2014-09-162-2/+7
| | | | | | | | ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share the same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: clk-imx6sl: correct the pxp and epdc axi clock selectionsFancy Fang2014-09-161-3/+4
| | | | | | | | | | The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL clocks are not the same. So split the epdc_pxp_sels into two different clock selections 'pxp_axi_sels' and 'epdc_axi_sels'. Signed-off-by: Fancy Fang <chen.fang@freescale.com> Signed-off-by: Robby Cai <R63905@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: clk-imx6q: refine clock tree for ESAIShengjiu Wang2014-09-162-6/+8
| | | | | | | | | There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename 'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'. Make the clock for ESAI more clear and align them with imx6sx. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: clk-imx6sl: Select appropriate parents for LCDIF clocksFabio Estevam2014-09-161-0/+7
| | | | | | | | PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: clk-imx6sl: Remove csi_lcdif_sels[]Fabio Estevam2014-09-161-3/+4
| | | | | | | | | | | | | Currently csi_lcdif_sels[] is a shared array for the providing the possible clock parents for csi and lcdif blocks. This is not correct, as csi and lcdif do not share the same clock parents. Introduce csi_sels[] for the csi and lcdif_axi_sels[] for the lcdif clocks in order to describe the parents correctly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: clk-vf610: Add USBPHY clocksStefan Agner2014-09-162-3/+14
| | | | | | | | | This commit adds PLL7 which is required for USBPHY1. It also adds the USB PHY and USB Controller clocks and the gates to enable them. Acked-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: add cpufreq support for i.mx6sxAnson Huang2014-09-161-0/+3
| | | | | | | | Add cpufreq support for i.MX6SX, using common i.MX6Q cpufreq driver. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: clk-vf610: introduce clks_init_onStefan Agner2014-09-161-0/+9
| | | | | | | | | | | | | | | | | | | At the end of the boot process, the clock framework might disable required main PLL's. So far, this was no issue since drivers requested clocks, which are descended of the main PLL's (e.g. pll1_pfd1, which provides the system clock). To archive the full 500MHz system clock, DDR clock need to be a descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The bootloader sets up the clocks accordingly before making use of DDR at all. However, in Linux, there is no driver using PLL2, which lead to PLL2 being disabled by the clock framework. With this patch, we make sure that the main system clock and the DDR clock are initially enabled and are kept enabled. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX1: Add devicetree supportAlexander Shiyan2014-09-163-0/+35
| | | | | | | This patch adds basic devicetree support for i.MX1 based SoCs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX6: add more chip revision supportJason Liu2014-09-162-0/+15
| | | | | | | | | | Add more revision support for the new i.MX6DQ tape-out (TO1.5). This TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed. Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx: Remove mach-mxt_td60 board fileFabio Estevam2014-09-103-286/+0
| | | | | | | | | | All the current support of mach-mxt_td60 board can be converted to devicetree. Remove the board file. Cc: Alan Carvalho de Assis <acassis@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX: Remove i.MX1 ADS board supportAlexander Shiyan2014-09-014-167/+0
| | | | | | | | mx1ads.c can be replaced with devicetree equivalent: imx1-ads.dts, so remove the board file. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: vf610-twr: remove useless property for sound card.Xiubo Li2014-09-011-1/+0
| | | | | | | | | | This was added by: Commit 8128c4f36 ("ARM: dts: vf610-twr: Add simple-card support.") This useless property may cause some confusions for users. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: remove imx_scu_standby_enable()Shawn Guo2014-09-013-16/+0
| | | | | | | | With commit c716483c3db1 ("ARM: 8122/1: smp_scu: enable SCU standby support"), the STANDBY bit of SCU is handled by core function scu_enable(). So imx_scu_standby_enable() can be removed now. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX: Remove Phytec i.MX27 PCM038/PCM970 board filesAlexander Shiyan2014-09-016-658/+0
| | | | | | | | | pcm970-baseboard.c and mach-pcm038.c can be replaced with their devicetree equivalents: imx27-phytec-phycore-rdk.dts and imx27-phytec-phycore-som.dtsi respectively, so remove the board files. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX: Remove mach-cpuimx27sd board fileAlexander Shiyan2014-09-016-736/+1
| | | | | | | | | | eukrea_mbimx27-baseboard.c and mach-cpuimx27.c can be replaced with their devicetree equivalents: imx27-eukrea-mbimxsd27-baseboard.dts and imx27-eukrea-cpuimx27.dtsi respectively, so remove the board files. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: iomux: Do not export symbol without public declarationAlexander Stein2014-09-013-11/+0
| | | | | | | | | | The iomux function declarations are in headers only accessible in this directory. Thus those can't be used in any module. None of the objects in this directory is tristate. Neither can the header be included in out-of-tree modules. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* Linux 3.17-rc3v3.17-rc3Linus Torvalds2014-09-011-1/+1
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* Merge tag 'xtensa-20140830' of git://github.com/czankel/xtensa-linuxLinus Torvalds2014-09-0124-217/+497
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull Xtensa updates from Chris Zankel: "Xtensa improvements for 3.17: - support highmem on cores with aliasing data cache. Enable highmem on kc705 by default - simplify addition of new core variants (no need to modify Kconfig / Makefiles) - improve robustness of unaligned access handler and its interaction with window overflow/underflow exception handlers - deprecate atomic and spill registers syscalls - clean up Kconfig: remove orphan MATH_EMULATION, sort 'select' statements - wire up renameat2 syscall. Various fixes: - fix address checks in dma_{alloc,free}_coherent (runtime BUG) - fix access to THREAD_RA/THREAD_SP/THREAD_DS (debug build breakage) - fix TLBTEMP_BASE_2 region handling in fast_second_level_miss (runtime unrecoverable exception) - fix a6 and a7 handling in fast_syscall_xtensa (runtime userspace register clobbering) - fix kernel/user jump out of fast_unaligned (potential runtime unrecoverabl exception) - replace termios IOCTL code definitions with constants (userspace build breakage)" * tag 'xtensa-20140830' of git://github.com/czankel/xtensa-linux: (25 commits) xtensa: deprecate fast_xtensa and fast_spill_registers syscalls xtensa: don't allow overflow/underflow on unaligned stack xtensa: fix a6 and a7 handling in fast_syscall_xtensa xtensa: allow single-stepping through unaligned load/store xtensa: move invalid unaligned instruction handler closer to its users xtensa: make fast_unaligned store restartable xtensa: add double exception fixup handler for fast_unaligned xtensa: fix kernel/user jump out of fast_unaligned xtensa: configure kc705 for highmem xtensa: support highmem in aliasing cache flushing code xtensa: support aliasing cache in kmap xtensa: support aliasing cache in k[un]map_atomic xtensa: implement clear_user_highpage and copy_user_highpage xtensa: fix TLBTEMP_BASE_2 region handling in fast_second_level_miss xtensa: allow fixmap and kmap span more than one page table xtensa: make fixmap region addressing grow with index xtensa: fix access to THREAD_RA/THREAD_SP/THREAD_DS xtensa: add renameat2 syscall xtensa: fix address checks in dma_{alloc,free}_coherent xtensa: replace IOCTL code definitions with constants ...
| * Merge tag 'xtensa-for-next-20140815' into for_nextChris Zankel2014-08-1924-217/+497
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xtensa improvements for 3.17: - support highmem on cores with aliasing data cache. Enable highmem on kc705 by default; - simplify addition of new core variants (no need to modify Kconfig / Makefiles); - improve robustness of unaligned access handler and its interaction with window overflow/underflow exception handlers; - deprecate atomic and spill registers syscalls; - clean up Kconfig: remove orphan MATH_EMULATION, sort 'select' statements; - wire up renameat2 syscall. Various fixes: - fix address checks in dma_{alloc,free}_coherent (runtime BUG); - fix access to THREAD_RA/THREAD_SP/THREAD_DS (debug build breakage); - fix TLBTEMP_BASE_2 region handling in fast_second_level_miss (runtime unrecoverable exception); - fix a6 and a7 handling in fast_syscall_xtensa (runtime userspace register clobbering); - fix kernel/user jump out of fast_unaligned (potential runtime unrecoverable exception); - replace termios IOCTL code definitions with constants (userspace build breakage). Signed-off-by: Chris Zankel <chris@zankel.net>
| | * xtensa: deprecate fast_xtensa and fast_spill_registers syscallsMax Filippov2014-08-142-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These syscalls are not used by userspace tools for some time now, and they have issues when called with invalid arguments. It's not worth changing signal delivery mechanism as we don't expect any new users for these syscalls. Let's keep them for backwards compatibility under #ifdef, disabled by default. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: don't allow overflow/underflow on unaligned stackMax Filippov2014-08-143-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Double exceptions that happen during register window overflow/underflow are handled in the topmost stack frame, as if it was the only exception that occured. However unaligned access exception handler is special because it needs to analyze instruction that caused the exception, but the userspace instruction that triggered window exception is completely irrelevant. Unaligned data access is rather normal in the generic userspace code, but stack pointer manipulation must always be done by architecture-aware code and thus unaligned stack means a serious problem anyway. Use the default unaligned access handler that raises SIGBUS in case of unaligned access in window overflow/underflow handler. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: fix a6 and a7 handling in fast_syscall_xtensaMax Filippov2014-08-141-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove restoring a6 on some return paths and instead modify and restore it in a single place, using symbolic name. Correctly restore a7 from PT_AREG7 in case of illegal a6 value. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: allow single-stepping through unaligned load/storeMax Filippov2014-08-141-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Update icount when icountlevel is non-zero but not greater than EXCM level when load/store instruction is successfully emulated. This allows single-stepping over such instruction in userspace debugger. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: move invalid unaligned instruction handler closer to its usersMax Filippov2014-08-141-33/+29
| | | | | | | | | | | | | | | | | | | | | | | | With this change a threaded jump from .Linvalid_instruction_load to .Linvalid_instruction can be removed and more code may be added to common load/store exit path. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: make fast_unaligned store restartableMax Filippov2014-08-141-32/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fast_unaligned may encounter DTLB miss or SEGFAULT during the store emulation. Don't update epc1 and lcount until after the store emulation is complete, so that the faulting store instruction could be replayed. Remove duplicate code handling zero overhead loops and calculate new epc1 and lcount in one place. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: add double exception fixup handler for fast_unalignedMax Filippov2014-08-141-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | fast_unaligned_fixup restores user registers and runs normal exception handler in the current stack frame. Unaligned load/store is retried after that. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: fix kernel/user jump out of fast_unalignedMax Filippov2014-08-141-1/+1
| | | | | | | | | | | | | | | | | | Use correct register (a0, just read from the PS) to check user mode bit. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: configure kc705 for highmemMax Filippov2014-08-141-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Enable all memory available on KC705 (1G - 128M) by default. Update memory node in DTS and also limit usable memory in bootargs in case memmap is passed from the bootloader. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: support highmem in aliasing cache flushing codeMax Filippov2014-08-141-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use __flush_invalidate_dcache_page_alias with alias set to color of the page physical address instead of __flush_invalidate_dcache_page: this works for high memory pages and mapping/unmapping to the TLBTEMP area is virtually free. Allow building configurations with aliasing cache and highmem enabled. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: support aliasing cache in kmapMax Filippov2014-08-142-2/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define ARCH_PKMAP_COLORING and provide corresponding macro definitions on cores with aliasing data cache. Instead of single last_pkmap_nr maintain an array last_pkmap_nr_arr of pkmap counters for each page color. Make sure that kmap maps physical page at virtual address with color matching its physical address. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: support aliasing cache in k[un]map_atomicMax Filippov2014-08-143-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | Map high memory pages at virtual addresses with color that match color of their physical address. Existing cache alias management mechanisms may be used with such pages. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: implement clear_user_highpage and copy_user_highpageMax Filippov2014-08-144-66/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing clear_user_page and copy_user_page cannot be used with highmem because they calculate physical page address from its virtual address and do it incorrectly in case of high memory page mapped with kmap_atomic. Also kmap is not needed, as most likely userspace mapping color would be different from the kmapped color. Provide clear_user_highpage and copy_user_highpage functions that determine if temporary mapping is needed for the pages. Move most of the logic of the former clear_user_page and copy_user_page to xtensa/mm/cache.c only leaving temporary mapping setup, invalidation and clearing/copying in the xtensa/mm/misc.S. Rename these functions to clear_page_alias and copy_page_alias. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: fix TLBTEMP_BASE_2 region handling in fast_second_level_missMax Filippov2014-08-142-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current definition of TLBTEMP_BASE_2 is always 32K above the TLBTEMP_BASE_1, whereas fast_second_level_miss handler for the TLBTEMP region analyzes virtual address bit (PAGE_SHIFT + DCACHE_ALIAS_ORDER) to determine TLBTEMP region where the fault happened. The size of the TLBTEMP region is also checked incorrectly: not 64K, but twice data cache way size (whicht may as well be less than the instruction cache way size). Fix TLBTEMP_BASE_2 to be TLBTEMP_BASE_1 + data cache way size. Provide TLBTEMP_SIZE that is a greater of doubled data cache way size or the instruction cache way size, and use it to determine if the second level TLB miss occured in the TLBTEMP region. Practical occurence of page faults in the TLBTEMP area is extremely rare, this code can be tested by deletion of all w[di]tlb instructions in the tlbtemp_mapping region. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: allow fixmap and kmap span more than one page tableMax Filippov2014-08-141-16/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | To support aliasing cache both kmap region sizes are multiplied by the number of data cache colors. After that expansion page tables that cover kmap regions may become larger than one page. Correctly allocate and initialize page tables in this case. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: make fixmap region addressing grow with indexMax Filippov2014-08-142-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's much easier to reason about alignment and coloring of regions located in the fixmap when fixmap index is just a PFN within the fixmap region. Change fixmap addressing so that index 0 corresponds to FIXADDR_START instead of the FIXADDR_TOP. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: fix access to THREAD_RA/THREAD_SP/THREAD_DSMax Filippov2014-08-142-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With SMP and a lot of debug options enabled task_struct::thread gets out of reach of s32i/l32i instructions with base pointing at task_struct, breaking build with the following messages: arch/xtensa/kernel/entry.S: Assembler messages: arch/xtensa/kernel/entry.S:1002: Error: operand 3 of 'l32i.n' has invalid value '1048' arch/xtensa/kernel/entry.S:1831: Error: operand 3 of 's32i.n' has invalid value '1040' arch/xtensa/kernel/entry.S:1832: Error: operand 3 of 's32i.n' has invalid value '1044' Change base to point to task_struct::thread in such cases. Don't use a10 in _switch_to to save/restore prev pointer as a2 is not clobbered. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: add renameat2 syscallMiklos Szeredi2014-08-141-1/+4
| | | | | | | | | | | | | | | | | | Signed-off-by: Miklos Szeredi <mszeredi@suse.cz> Cc: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: fix address checks in dma_{alloc,free}_coherentAlan Douglas2014-08-141-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Virtual address is translated to the XCHAL_KSEG_CACHED region in the dma_free_coherent, but is checked to be in the 0...XCHAL_KSEG_SIZE range. Change check for end of the range from 'addr >= X' to 'addr > X - 1' to handle the case of X == 0. Replace 'if (C) BUG();' construct with 'BUG_ON(C);'. Cc: stable@vger.kernel.org Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: replace IOCTL code definitions with constantsMax Filippov2014-08-141-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes userspace code that builds on other architectures but fails on xtensa due to references to structures that other architectures don't refer to. E.g. this fixes the following issue with python-2.7.8: python-2.7.8/Modules/termios.c:861:25: error: invalid application of 'sizeof' to incomplete type 'struct serial_multiport_struct' {"TIOCSERGETMULTI", TIOCSERGETMULTI}, python-2.7.8/Modules/termios.c:870:25: error: invalid application of 'sizeof' to incomplete type 'struct serial_multiport_struct' {"TIOCSERSETMULTI", TIOCSERSETMULTI}, python-2.7.8/Modules/termios.c:900:24: error: invalid application of 'sizeof' to incomplete type 'struct tty_struct' {"TIOCTTYGSTRUCT", TIOCTTYGSTRUCT}, Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: remove orphan MATH_EMULATION symbolMax Filippov2014-08-144-8/+0
| | | | | | | | | | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: select HAVE_IDE only on platforms that may have itMax Filippov2014-08-142-2/+3
| | | | | | | | | | | | | | | | | | | | | HAVE_IDE is not a property of architecture but of a platform, and neither ISS or XTFPGA support it. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: sort 'select' statements in KconfigMax Filippov2014-08-141-11/+11
| | | | | | | | | | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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