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* Merge tag 'integrator-armsoc-1' of ↵Arnd Bergmann2016-09-144-158/+126
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/late Pull "This is a bunch of Integrator changes for v4.9" Linus Walleij: - Add and fix a bunch of clocks in the DTS corresponding to the new clock support merged into the clk tree. - Move the CLCD display configuration from boardfile to device tree using the new CLCD support merged into the fbdev tree. - Cut some auxdata. - Cut some static remappings. - Move the sched_clock() counter to use syscon+regmap. * tag 'integrator-armsoc-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: integrator: read counter using syscon/regmap ARM: integrator: cut down on static maps ARM: integrator: delete some auxdata ARM: integrator: move CP CLCD display to DTS ARM: dts: add the core module clocks to Integrator/CP ARM: dts: Add the core module clocks to Integrator/AP ARM: dts: add the Integrator/AP baseboard clocks ARM: dts: set the 24MHz xtal as parent of the UART clock
| * ARM: integrator: read counter using syscon/regmapLinus Walleij2016-08-311-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | Look up the core module base address from the device tree and register a sched_clock() using the regmap to the core module on the Integrator/CP. MFD_SYSCON is selected by the arch so it is always available. This further makes it possible to remove one more static map. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: integrator: cut down on static mapsLinus Walleij2016-08-312-63/+0
| | | | | | | | | | | | | | | | This removes all the unused static maps on the Integrator/AP and Integrator/CP and also take this opportunity to strip down a big list of unused #includes from each boardfile. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: integrator: delete some auxdataLinus Walleij2016-08-312-18/+0
| | | | | | | | | | | | | | | | | | | | | | There is just a few auxdata entries still needed on the Integrators: - UART RTS/CTS callbacks for Integrator/AP - MMC/SD special card detect quirk for Integrator/CP Delete the rest. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: integrator: move CP CLCD display to DTSLinus Walleij2016-08-312-58/+36
| | | | | | | | | | | | | | | | The Integrator/CP CLCD VGA display can now be registered fully from the device tree. Delete the board file code and add the display definition to the DTS. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: dts: add the core module clocks to Integrator/CPLinus Walleij2016-08-311-10/+27
| | | | | | | | | | | | | | This adds the core and memory clocks to the Integrator/CP device tree. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: dts: Add the core module clocks to Integrator/APLinus Walleij2016-08-311-1/+28
| | | | | | | | | | | | | | | | | | This adds the clocks on the core module to the Integrator/AP board: a 24MHz chrystal, and two special-purpose ICST525 dividers, one used to clock the CPU core and another auxilary oscillator. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: dts: add the Integrator/AP baseboard clocksLinus Walleij2016-08-311-0/+21
| | | | | | | | | | | | | | | | | | The two clocks present on the Integrator/AP baseboard and accessible through its system controller is the PCIv3 bridge clock and the PCI bus clock. Define the proper device tree nodes for these. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: dts: set the 24MHz xtal as parent of the UART clockLinus Walleij2016-08-311-0/+1
| | | | | | | | | | | | | | This has no practical effect but reflects the actual clock hierarchy of the system. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'renesas-arm64-dt-for-v4.9' of ↵Arnd Bergmann2016-09-1415-58/+6532
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late Pull "Renesas ARM64 Based SoC DT Updates for v4.9" from Simon Horman: Clean up: * Remove unnecessary cap-mmc-highspeed property from SDHI nodes on r8a7795 SoC * Add SoC-specific compatible property to audio-dmac nodes on r8a7795 SoC New Board: * Add r8a7794/h3ulcb board Enablement: * Add PFC and GPIO to r8a7796 SoC * Enable DU and USB 2.0 on r8a7795/salvator-x board * Add VTP, FCPV, FCPF and FDP1 to r8a7795 SoC * Set maximum frequency for SDHI clocks on r8a7795 SoC * tag 'renesas-arm64-dt-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits) arm64: dts: r8a7796: Add GPIO device nodes arm64: dts: r8a7796: salvator-x: add serial console pins arm64: dts: r8a7796: Add pinctrl device node arm64: dts: r8a7795: salvator-x: Configure pins for the DU RGB output arm64: dts: h3ulcb: enable GPIO leds arm64: dts: h3ulcb: Sound SSI support arm64: dts: h3ulcb: enable SDHI0 arm64: dts: h3ulcb: enable GPIO keys arm64: dts: r8a7795: remove unnecessary cap-mmc-highspeed property arm64: dts: h3ulcb: enable USB2.0 Host channel 1 arm64: dts: h3ulcb: enable USB2 PHY of channel 1 arm64: dts: h3ulcb: enable WDT arm64: dts: h3ulcb: enable EXTALR clk arm64: dts: h3ulcb: enable I2C2 arm64: dts: h3ulcb: enable EthernetAVB arm64: dts: h3ulcb: enable SCIF clk and pins arm64: dts: h3ulcb: initial device tree arm64: dts: h3ulcb: add H3ULCB board DT bindings arm64: dts: r8a7795: Add SoC-specific compatible property to audio-dmac nodes arm64: dts: r8a7795: renesas: salvator-x: Enable DU ...
| * | arm64: dts: r8a7796: Add GPIO device nodesTakeshi Kihara2016-09-081-0/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add GPIO device nodes to the DT of the r8a7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * | arm64: dts: r8a7796: salvator-x: add serial console pinsUlrich Hecht2016-09-081-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | Adds pin control for SCIF2. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7796: Add pinctrl device nodeTakeshi Kihara2016-09-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds pinctrl device node for R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7795: salvator-x: Configure pins for the DU RGB outputLaurent Pinchart2016-09-081-0/+7
| | | | | | | | | | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: enable GPIO ledsVladimir Barinov2016-09-081-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | This supports GPIO leds on H3ULCB board Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: Sound SSI supportVladimir Barinov2016-09-081-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | This supports SSI sound for H3ULCB board. SSI DMA mode used. CS2000 used as AUDIO_CLK_B. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: enable SDHI0Vladimir Barinov2016-09-081-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | This supports SDHI0 on H3ULCB board SD card slot Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: enable GPIO keysVladimir Barinov2016-09-081-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | This supports GPIO keys on H3ULCB board Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7795: remove unnecessary cap-mmc-highspeed propertySimon Horman2016-09-081-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove cap-mmc-highspeed property from SDHI2 and SDHI3. This property is unnecessary as the driver automatically sets the highspeed capability. Furthermore its use is inconsistent with SDHI0 and SDHI1 which are also highspeed capable but do not have this property present. Found by inspection. Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: enable USB2.0 Host channel 1Vladimir Barinov2016-09-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | This supports USB2.0 Host channel 1 on H3ULCB board Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: enable USB2 PHY of channel 1Vladimir Barinov2016-09-061-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | This supports USB2 PHY channel #1 on H3ULCB board Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: enable WDTVladimir Barinov2016-09-061-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | This supports watchdog timer for H3ULCB board Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: enable EXTALR clkVladimir Barinov2016-09-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This enables EXTALR clock that can be used for the watchdog. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: enable I2C2Vladimir Barinov2016-09-061-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | This supports I2C2 bus on H3ULCB board Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: enable EthernetAVBVladimir Barinov2016-09-061-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | This supports Ethernet AVB on H3ULCB board Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: enable SCIF clk and pinsVladimir Barinov2016-09-061-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | This enables the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: initial device treeVladimir Barinov2016-09-062-1/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the initial device tree for the R8A7795 SoC based H3ULCB low cost board. This commit supports the following peripherals: - SCIF (console) Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: h3ulcb: add H3ULCB board DT bindingsVladimir Barinov2016-09-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add H3ULCB Device tree bindings Documentation, listing it as a supported board. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7795: Add SoC-specific compatible property to audio-dmac nodesGeert Uytterhoeven2016-09-061-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | The audio-dmac nodes used the generic compatible property only. Add the SoC-specific one, to make it future proof. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7795: renesas: salvator-x: Enable DULaurent Pinchart2016-09-061-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | Only the VGA output is supported for now. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a7795: Add DU device to DTLaurent Pinchart2016-09-061-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | Add the DU device to r8a7795.dtsi in a disabled state. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a7795: Add VSP instancesLaurent Pinchart2016-09-061-0/+90
| | | | | | | | | | | | | | | | | | | | | The r8a7795 has 9 VSP instances. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a7795: Add FCPV nodesLaurent Pinchart2016-09-061-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | The FCPs handle the interface between various IP cores and memory. Add the instances related to the VSP2s. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7795: salvator-x: enable HSUSBYoshihiro Shimoda2016-09-061-0/+4
| | | | | | | | | | | | | | | Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7795: salvator-x: enable USB 2.0 Host channel 0Yoshihiro Shimoda2016-09-061-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | We have to set SW15 to pin 2-3 side on the board before we use CN9 as USB host or peripheral. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7795: salvator-x: enable usb2_phy of channel 0Yoshihiro Shimoda2016-09-061-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | This patch also adds a regulator node for USB2.0 to handle VBUS on/off by the phy-rcar-gen3-usb2 driver. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7795: Add HSUSB device nodeYoshihiro Shimoda2016-09-061-0/+17
| | | | | | | | | | | | | | | Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7795: set maximum frequency for SDHI clocksWolfram Sang2016-09-061-0/+4
| | | | | | | | | | | | | | | | | | | | | Define the upper limit otherwise the driver cannot utilize max speeds. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7795: add FDP1 device nodesKieran Bingham2016-09-061-0/+27
| | | | | | | | | | | | | | | | | | | | | Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kieran Bingham <kieran@bingham.xyz> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: r8a7795: add FCPF device nodesKieran Bingham2016-09-061-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | Provide nodes for the FCP devices dedicated to the FDP device channels. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Kieran Bingham <kieran@bingham.xyz> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a7796: Add SDHI pins, groups and functionsTakeshi Kihara2016-08-191-0/+275
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds SDHI pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7796: Add SCIF pins, groups and functionsTakeshi Kihara2016-08-191-0/+300
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Initial R8A7796 PFC supportTakeshi Kihara2016-08-196-0/+2086
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds initial pinctrl driver to support for the R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: rebased on top of renesas-drivers] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7795: Add DU supportLaurent Pinchart2016-08-161-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add DU pin groupsSergei Shtylyov2016-08-081-0/+144
| | | | | | | | | | | | | | | | | | | | | Add DU pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add VIN pin groupsSergei Shtylyov2016-08-081-0/+577
| | | | | | | | | | | | | | | | | | | | | | | | Add VIN[0-5] pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> [geert: Fix VI1_D14_G6_Y6 and VI1_D15_G7_Y7 pins] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7795: Correct header from R-Car Gen3 to R8A7795Geert Uytterhoeven2016-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This source file handles r8a7795 only, which is not the sole member of the R-Car Gen3 family. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sh-pfc: r8a7792: Add CAN pin groupsSergei Shtylyov2016-08-081-0/+37
| | | | | | | | | | | | | | | | | | | | | Add CAN0/1 data/clock pin groups to R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add SDHI pin groupsSergei Shtylyov2016-08-081-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | Add SDHI0 pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add EtherAVB pin groupsSergei Shtylyov2016-08-081-0/+99
| | | | | | | | | | | | | | | | | | | | | Add the EtherAVB pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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