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* dmaengine: sh: don't use dynamic static allocationVinod Koul2014-06-031-1/+9
| | | | | | | | | | | | | | | | dynamic stack allocation in kernel is considered bad as kernel stack is low and we get warns on few archs as reported by kbuild test robot >> drivers/dma/sh/shdma-base.c:671:32: sparse: Variable length array is used. >> drivers/dma/sh/shdma-base.c:701:1: warning: 'shdma_prep_dma_cyclic' uses >> dynamic stack allocation [enabled by default] Fix this by making a static array of 32 which should be sufficient for shdma_prep_dma_cyclic which only user in kernel is audio and 32 periods for audio seems quite sufficient atm Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sh: fix print specifier warningsVinod Koul2014-06-031-1/+1
| | | | | | | | | | | | | | | | | | As documented in Documentation/printk-formats.txt we should use %zu/%zx specifiers for size_t type variables for the code to compile on different architectures. This is uncovered as COMPILE_TEST has been enabled recently for this driver drivers/dma/sh/shdma-base.c: In function 'shdma_prep_dma_cyclic': >> drivers/dma/sh/shdma-base.c:683:4: warning: format '%d' expects argument of >> type 'int', but argument 4 has type 'size_t' [-Wformat=] __func__, buf_len, period_len, slave_id); >> drivers/dma/sh/shdma-base.c:683:4: warning: format '%d' expects argument of >> type 'int', but argument 5 has type 'size_t' [-Wformat=] Reported-by: kbuild test robot <fengguang.wu@intel.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sh: make shdma_prep_dma_cyclic staticVinod Koul2014-06-031-1/+1
| | | | | | | | | | | | kbuild test robot reports that shdma_prep_dma_cyclic should be static, since symbol is not declared, quick check revails that is the case >> drivers/dma/sh/shdma-base.c:660:32: sparse: symbol 'shdma_prep_dma_cyclic' >> was not declared. Should it be static? Reported-by: kbuild test robot <fengguang.wu@intel.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: Kconfig: Update MXS_DMA help text to include MX6Q/MX6DLFabio Estevam2014-06-011-1/+1
| | | | | | | | | The APBX-DMA block is also found on MX6Q/MX6DL chips. Update the help text accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* of: dma: Grammar s/requests/request/, s/used required/required/Geert Uytterhoeven2014-06-011-2/+2
| | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: shdma: Enable driver compilation with COMPILE_TESTLaurent Pinchart2014-06-011-1/+1
| | | | | | | | This helps increasing build testing coverage. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Simon Horman <horms@verge.net.au> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-hpbdma: Include linux/err.hLaurent Pinchart2014-06-011-0/+1
| | | | | | | | | linux/err.h isn't implicitly included by the current headers on all platforms, resulting in compilation failures due to implicit declarations of IS_ERR and PTR_ERR. Fix this by including linux/err.h. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sudmac: Include linux/err.hLaurent Pinchart2014-06-011-0/+1
| | | | | | | | | linux/err.h isn't implicitly included by the current headers on all platforms, resulting in compilation failures due to implicit declarations of IS_ERR and PTR_ERR. Fix this by including linux/err.h. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sudmac: Keep #include sorted alphabeticallyLaurent Pinchart2014-06-011-3/+3
| | | | | | | This helps detecting duplicate includes. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: shdmac: Include linux/err.hLaurent Pinchart2014-06-011-0/+1
| | | | | | | | | linux/err.h isn't implicitly included by the current headers on all platforms, resulting in compilation failures due to implicit declarations of IS_ERR and PTR_ERR. Fix this by including linux/err.h. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: shdmac: Keep #include sorted alphabeticallyLaurent Pinchart2014-06-011-7/+7
| | | | | | | This helps detecting duplicate includes. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: s3c24xx-dma: Add cyclic transfer supportVasily Khoruzhick2014-06-011-1/+111
| | | | | | | | | | Many audio interface drivers require support of cyclic transfers to work correctly, for example Samsung ASoC DMA driver. This patch adds support for cyclic transfers to the s3c24xx-dma driver Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: s3c24xx-dma: Process whole SG chainVasily Khoruzhick2014-06-011-1/+0
| | | | | | | | Due to redundant 'break' in loop driver processed only first chunk. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: imx: correct sdmac->status for cyclic dma txJiada Wang2014-06-011-2/+0
| | | | | | | | | | | | | | | | | | | | | | In cyclic dma tx's handler sdma_handle_channel_loop(), SDMA channel statue is set to either DMA_ERROR or DMA_IN_PROGRESS based on each period's status. This has the following issues: 1) If one period's status is BD_RROR, then channel status will be set to DMA_ERROR, but it will be overwritten to DMA_IN_PROGRESS if the following periods are OK. 2) DMA client may call sdma_control(DMA_TERMINATE_ALL) to stop the cyclic dma operation, sdma channel status will be set to DMA_ERROR, but if after this handler is called, then again the channel status will be overwritten to DMA_IN_PROGRESS. Then the following dmaengine_prep_dma_cyclic() will always fail, as channel status is DMA_IN_PROGRESS. As in cyclic dma tx, channel status will be initially set to DMA_IN_PROGRESS, driver only needs to change it to DMA_ERROR, when something wrong happens (one period status is wrong, or stoped by client explicitly). Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: pch: fix compilation for alpha targetVinod Koul2014-05-221-0/+1
| | | | | | | | | commit 4828b493 introduced COMPILE_TEST for this driver and this cause compile failure on alpha as kzalloc wasnt availble for this arch in included header, so explictly add slab.h Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: pch_dma: Fix Kconfig dependenciesJean Delvare2014-05-221-1/+1
| | | | | | | | | | | The pch_dma driver is for a companion chip to the Intel Atom E600 series processors. These are 32-bit x86 processors so the driver is only needed on X86_32. Add COMPILE_TEST as an alternative, so that the driver can still be build-tested elsewhere. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mpc512x: add support for peripheral transfersAlexander Popov2014-05-221-5/+239
| | | | | | | | | | | Introduce support for slave s/g transfer preparation and the associated device control callback in the MPC512x DMA controller driver, which adds support for data transfers between memory and peripheral I/O to the previously supported mem-to-mem transfers. Signed-off-by: Alexander Popov <a13xp0p0v88@gmail.com> [fixed subsytem name] Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: fix comment typoAlexander Popov2014-05-221-1/+1
| | | | | | | Fix comment typo. Signed-off-by: Alexander Popov <a13xp0p0v88@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: remove DEFINE_PCI_DEVICE_TABLE macroJingoo Han2014-05-212-2/+2
| | | | | | | | | Don't use DEFINE_PCI_DEVICE_TABLE macro, because this macro is deprecated. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: ste_dma40: Convert to the late system PM callbacksUlf Hansson2014-05-071-1/+1
| | | | | | | | Clients may still be active in the early phase of system PM, thus we need to move the suspend operations to the late system PM phase. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mmp_pdma: add support for residue reportingDaniel Mack2014-05-071-3/+84
| | | | | | | | | | | | | | | A channel can accommodate more than one transaction, each consisting of multiple descriptors, the last of which has the DCMD_ENDIRQEN bit set. In order to report the channel's residue, we hence have to walk the list of running descriptors, look for those which match the cookie, and then try to find the descriptor which defines upper and lower boundaries that embrace the current transport pointer. Once it is found, walk forward until we find the descriptor that tells us about the end of a transaction via a set DCMD_ENDIRQEN bit. Signed-off-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: ste_dma40: Fixup system suspend/resumeUlf Hansson2014-05-071-3/+10
| | | | | | | | | | | | | Make sure to handle register context save/restore when needed from system PM callbacks. Previously we solely trusted the device to reside in in-active state while the system suspend callback were invoked, which is just too optimistic. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: ste_dma40: Convert to PM macros while providing the PM callbacksUlf Hansson2014-05-071-79/+71
| | | | | | | | Converting to the PM macros makes us simplify and remove some code. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: ste_dma40: Don't require CONFIG_PM_RUNTIMEUlf Hansson2014-05-071-11/+10
| | | | | | | | | | While probing, don't rely on CONFIG_PM_RUNTIME to be configured. Instead, let's power up the device and make it fully operational. Update the runtime PM status to reflect the active state. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: ste_dma40: Maintain spinlock order while handling pauseUlf Hansson2014-05-071-1/+1
| | | | | | | | | The runtime PM resume callback needs to be executed while holding the spinlock, make sure to maintain this for the pause operation as well. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: dw: convert to use SET_LATE_SYSTEM_SLEEP_PM_OPSAndy Shevchenko2014-05-071-8/+2
| | | | | | | | | | | The commit 4501fe61 "dma: dw: Add suspend and resume handling for PCI mode DW_DMAC." introduces system power management callbacks. Regarding to commit f78c4cff "PM / Sleep: Add macro to define common late/early system PM callbacks" we have nice macro to setup dev_pm_ops structure. This patch converts a driver to use the macro. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: dw: move PM to suspend_late / resume_early stagesAndy Shevchenko2014-05-071-14/+4
| | | | | | | | | | | There is no need to use *_noirq version of suspend and resume PM callbacks. The suspend_late / resume_early suit better (it was discussed in [1]) and in future could be used for runtime PM support. [1] http://www.spinics.net/lists/kernel/msg1650974.html Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mpc512x: fix freeing resources in mpc_dma_probe() and mpc_dma_remove()Alexander Popov2014-05-021-17/+38
| | | | | | | | | | | Fix mpc_dma_probe() error path and mpc_dma_remove(): manually free IRQs and dispose IRQ mappings before devm_* takes care of other resources. Moreover replace devm_request_irq() with request_irq() since there is no need to use it because the original code always frees IRQ manually with devm_free_irq(). Replace devm_free_irq() with free_irq() accordingly. Signed-off-by: Alexander Popov <a13xp0p0v88@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mpc512x: separate 'compatible' values for MPC512x and MPC8308Alexander Popov2014-05-023-2/+3
| | | | | | | | MPC512x and MPC8308 have similar DMA controllers, but are independent SoCs. DMA controller driver should have separate 'compatible' values for these SoCs. Signed-off-by: Alexander Popov <a13xp0p0v88@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mpc512x: reorder mpc8308 specific instructionsAlexander Popov2014-05-021-17/+25
| | | | | | | | | | Concentrate the specific code for MPC8308 in the 'if' branch and handle MPC512x in the 'else' branch. This modification only reorders instructions but doesn't change behaviour. Signed-off-by: Alexander Popov <a13xp0p0v88@gmail.com> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* DMA: Freescale: move functions to avoid forward declarationsHongbo Zhang2014-05-021-95/+95
| | | | | | | | | These functions will be modified in the next patch in the series. By moving the function in a patch separate from the changes, it will make review easier. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Signed-off-by: Qiang Liu <qiang.liu@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* DMA: Freescale: add fsl_dma_free_descriptor() to reduce code duplicationHongbo Zhang2014-05-021-10/+17
| | | | | | | | | There are several places where descriptors are freed using identical code. This patch puts this code into a function to reduce code duplication. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Signed-off-by: Qiang Liu <qiang.liu@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* DMA: Freescale: remove attribute DMA_INTERRUPT of dmaengineHongbo Zhang2014-05-021-31/+0
| | | | | | | | | Delete attribute DMA_INTERRUPT because fsldma doesn't support this function, exception will be thrown if talitos is used to offload xor at the same time. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Signed-off-by: Qiang Liu <qiang.liu@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* DMA: Freescale: unify register access methodsHongbo Zhang2014-05-021-19/+33
| | | | | | | | | | | | Methods of accessing DMA controller registers are inconsistent, some registers are accessed by DMA_IN/OUT directly, while others are accessed by functions get/set_* which are wrappers of DMA_IN/OUT, and even for the BCR register, it is read by get_bcr but written by DMA_OUT. This patch unifies the inconsistent methods, all registers are accessed by get/set_* now. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* DMA: Freescale: remove the unnecessary FSL_DMA_LD_DEBUGHongbo Zhang2014-05-021-10/+0
| | | | | | | | | | Some codes are calling chan_dbg with FSL_DMA_LD_DEBUG surrounded, it is really unnecessary to use such a macro because chan_dbg is a wrapper of dev_dbg, we do have corresponding DEBUG macro to switch on/off dev_dbg, and most of the other codes are also calling chan_dbg directly without using FSL_DMA_LD_DEBUG. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* DMA: shdma: add cyclic transfer supportKuninori Morimoto2014-05-022-7/+66
| | | | | | | | This patch add cyclic transfer support and enables dmaengine_prep_dma_cyclic() Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [reflown changelog for readablity] Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* DMA: shdma: tidyup callback chunk finderKuninori Morimoto2014-05-021-9/+9
| | | | | | | | | Current shdma is using "last" which indicates last desc which needs to have callback function. But that desc's chunks is always 1, we can use it as finder Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [reflown changelog for readablity] Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mmp_pdma: Fix physical channel memory allocation sizeLaurent Pinchart2014-05-021-4/+2
| | | | | | | | | Use sizeof(*var) instead of sizeof(type) when calling devm_k*alloc(). This avoids using the wrong type as was done to allocate the physical channels array. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mmp_pdma: Simplify access to channel drcmr valueLaurent Pinchart2014-05-021-1/+1
| | | | | | | | | As the physical channel and virtual channel point to each other, pchan->phy->vchan is always equal to pchan. Simplify the code accordingly. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mmp_pdma: Fix the #dma-channels DT property documentationLaurent Pinchart2014-05-021-4/+7
| | | | | | | | The property is optional and defaults to 32. Document it as such. Cc: devicetree@vger.kernel.org Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: edma: update DMA memcpy to use new param elementJoel Fernandes2014-04-301-2/+2
| | | | | | | | | edma param struct is now within an edma_pset struct introduced in Thomas Gleixner's edma tx status series. Update memcpy function for the same. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: edma: Document variables used for residue accountingJoel Fernandes2014-04-301-2/+24
| | | | | | | | | | The granular residue accounting code uses certain variables specifically for residue accounting. Document these in the structure declaration. Also move around some elements and group them together. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: edma: Provide granular accountingThomas Gleixner2014-04-301-2/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first slot in the ParamRAM of EDMA holds the current active subtransfer. Depending on the direction we read either the source or the destination address from there. In the internal psets we have the address of the buffer(s). In the cyclic case we only use the internal pset[0] which holds the start address of the circular buffer and calculate the remaining room to the end of the buffer. In the SG case we read the current address and compare it to the internal psets address and length. - If the current address is outside of this range, the pset has been processed already and we mark it done, update the residue_stat value and process the next set. That avoids that we need to walk all processed psets for every invocation of tx_status. - If its inside the range we know that we look at the current active set and stop the walk. - In case of intermediate transfers we update the stats in the interrupt callback function before starting the next batch of transfers. The tx_status callback and the interrupt callback are serialized via vchan.lock. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> [joelf@ti.com: Hunk #2 in original patch manually applied] Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: edma: Make reading the position of active channels workThomas Gleixner2014-04-302-16/+10
| | | | | | | | | | | | | | | | | | | | | | | As Joel pointed out, edma_read_position() uses memcpy_fromio() to read the parameter ram. That's not synchronized with the internal update as it does a byte by byte copy. We need to do a 32bit read to get a consistent value. Further reading destination and source is pointless. In DEV_TO_MEM transfers we are only interested in the destination, in MEM_TO_DEV we care about the source. In MEM_TO_MEM it really does not matter which one you read. Simple solution: Remove the pointers, select dest/source via a bool and return the read value. Remove the export of this function while at it. The only potential user is the dmaengine and that's always builtin. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: edma: Store transfer data in edma_desc and edma_psetThomas Gleixner2014-04-301-0/+9
| | | | | | | | | | | | For granular accounting we need to store the direction and the information for the individual psets: - source or destination address, depending on direction - length Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: edma: Create private pset structThomas Gleixner2014-04-301-31/+36
| | | | | | | | | | | | Preparatory patch to support finer grained accounting. Move the edma_params array out of edma_desc so we can add further per pset data to it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> [joelf@ti.com: Fixed up hunk #3 in original patch to apply] Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: edma: Check the current decriptor first in tx_status()Thomas Gleixner2014-04-301-4/+3
| | | | | | | | | | It's likely that the caller investigates the status of a currently active descriptor. Make that simple check first and only rumage in the vchan list if that fails. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: edma: Sanitize residue reportingThomas Gleixner2014-04-301-25/+9
| | | | | | | | | | | | | | | | | The residue reporting in edma_tx_status() is just broken. It blindly walks the psets and recalculates the lenght of the transfer from the hardware parameters. For cyclic transfers it adds the link pset, which results in interestingly large residues. For non-cyclic it adds the dummy pset, which is stupid as well. Aside of that it's silly to walk through the pset params when the per descriptor residue is known at the point of creating it. Store the information in edma_desc and use it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: edma: Add channel number to debug printsPeter Ujfalusi2014-04-291-3/+4
| | | | | | | | | It helps to identify issues if we have some information regarding to the channel which the event is associated. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: edma: No need save/restore interrupt flags during spin_lock in IRQJoel Fernandes2014-04-231-5/+4
| | | | | | | | | | | The vchan lock in edma_callback is acquired in hard interrupt context. As interrupts are already disabled, there's no point in save/restoring interrupt mask bit or cpsr flags. Get rid of flags local variable and use spin_lock instead of spin_lock_irqsave. Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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