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* i2c: designware: Add Intel Baytrail PMIC I2C bus supportDavid Box2015-01-265-5/+193
| | | | | | | | | | | | | | This patch implements an I2C bus sharing mechanism between the host and platform hardware on select Intel BayTrail SoC platforms using the X-Powers AXP288 PMIC. On these platforms access to the PMIC must be shared with platform hardware. The hardware unit assumes full control of the I2C bus and the host must request access through a special semaphore. Hardware control of the bus also makes it necessary to disable runtime pm to avoid interfering with hardware transactions. Signed-off-by: David E. Box <david.e.box@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: designware: Add i2c bus locking supportDavid Box2015-01-262-0/+32
| | | | | | | | | | Adds support for acquiring and releasing a hardware bus lock in the i2c designware core transfer function. This is needed for i2c bus controllers that are shared with but not controlled by the kernel. Signed-off-by: David E. Box <david.e.box@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* of: i2c: Add i2c-mux-idle-disconnect DT property to PCA954x mux driverAlexander Sverdlin2015-01-232-1/+13
| | | | | | | | | | | Add i2c-mux-idle-disconnect device tree property to PCA954x mux driver. The new property forces the multiplexer to disconnect child buses in idle state. This is used, for example, when there are several multiplexers on the same bus and the devices on the underlying buses might have same I2C addresses. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nsn.com> [wsa: added a newline] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: designware: use {readl|writel}_relaxed instead of readl/writelJisheng Zhang2015-01-231-6/+6
| | | | | | | | | | | | | | readl/writel is too expensive especially on Cortex A9 w/ outer L2 cache. This introduces i2c read/write delays on Marvell BG2/BG2Q SoCs when there are heavy L2 cache maintenance operations at the same time. The driver does not perform DMA, so it's safe to use the relaxed version. From another side, the relaxed io accessor macros are available on all architectures now, so we can use the relaxed versions instead. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: designware-pci: no need to provide clk_khzAndy Shevchenko2015-01-231-2/+0
| | | | | | | | | | The clk_khz field makes sense only if SS counters are not provided. Since we provide them for Haswell and Baytrail explicitly we may omit the clk_khz parameter. Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: designware-pci: remove Moorestown supportAndy Shevchenko2015-01-231-29/+0
| | | | | | | | | The Moorestown support bits were removed few years ago. This is a follow up to that changes. Suggested-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: imx: whitespace and checkpatch cleanupPhilipp Zabel2015-01-221-10/+13
| | | | | | | | | This patch fixes up some whitespace issues and addresses a few checkpatch warnings. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: simplify boilerplate code for attribute groupsWolfram Sang2015-01-221-24/+6
| | | | | | | | Declaring attribute groups can be done with macros these days, let's use them for consistency and readability reasons. Also, put the ATTR macros directly below the referenced functions while we are here. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: imx: remove unused return value assignmentsPhilipp Zabel2015-01-141-2/+0
| | | | | | | | The ret variable is set and never used in the error path of i2c_imx_dma_request. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: ACPI: Pick the first address if device has multipleMika Westerberg2015-01-141-1/+1
| | | | | | | | | | | | ACPI specification allows I2C devices with multiple addresses. The current implementation goes over all addresses and assigns the last one to the device. This is typically not the primary address of the device. Instead of doing that we assign the first address to the device and then let the driver handle rest of the addresses as it wishes. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: cadence: Check for errata condition involving master receiveHarini Katakam2015-01-141-0/+14
| | | | | | | | | | | | | | | | | | Cadence I2C controller has the following bugs: - completion indication is not given to the driver at the end of a read/receive transfer with HOLD bit set. - Invalid read transaction are generated on the bus when HW timeout condition occurs with HOLD bit set. As a result of the above, if a set of messages to be transferred with repeated start includes any message following a read message, completion is never indicated and timeout occurs. Hence a check is implemented to return -EOPNOTSUPP for such sequences. Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Vishnu Motghare <vishnum@xilinx.com> [wsa: fixed some whitespaces] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* dt-bindings: use isil prefix for Intersil in I2C trivial-devices.txtArnaud Ebalard2015-01-131-3/+2
| | | | | | | | | | | | This patch fixes I2C trivial-devices.txt DT documentation file to reference isil (NASDAQ symbol and the most used prefix inside the kernel) for Intersil. It reverts 7c75c1d5e72b ("dt-bindings: Document deprecated device vendor name to fix related warning"). Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: imx: fix handling of wait_for_completion_timeout resultNicholas Mc Guire2015-01-131-4/+4
| | | | | | | | | wait_for_completion_timeout does not return negative values so "result" handling here should be simplified to cover the actually possible cases only. Signed-off-by: Nicholas Mc Guire <der.herr@hofr.at> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: rk3x: Account for repeated start time requirementDoug Anderson2015-01-132-20/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Rockchip I2C the controller drops SDA low slightly too soon to meet the "repeated start" requirements. >From my own experimentation over a number of rates: - controller appears to drop SDA at .875x (7/8) programmed clk high. - controller appears to keep SCL high for 2x programmed clk high. The first rule isn't enough to meet tSU;STA requirements in Standard-mode on the system I tested on. The second rule is probably enough to meet tHD;STA requirements in nearly all cases (especially after accounting for the first), but it doesn't hurt to account for it anyway just in case. Even though the repeated start requirement only need to be accounted for during a small part of the transfer, we'll adjust the timings for the whole transfer to meet it. I believe that adjusting the timings in just the right place to switch things up for repeated start would require several extra interrupts and that doesn't seem terribly worth it. With this change and worst case rise/fall times, I see 100kHz i2c going to ~85kHz. With slightly optimized rise/fall (800ns / 50ns) I see i2c going to ~89kHz. Fast-mode isn't affected much because tSU;STA is shorter relative to tHD;STA there. As part of this change we needed to account for the SDA falling time. The specification indicates that this should be the same, but we'll follow Designware's lead and add a binding. Note that we deviate from Designware and assign the default SDA falling time to be the same as the SCL falling time, which is incredibly likely. Signed-off-by: Doug Anderson <dianders@chromium.org> [wsa: rebased to i2c/for-next] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: rk3x: fix bug that cause measured high_ns doesn't meet I2C specificationaddy ke2015-01-132-23/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of clock cycles to be written into the CLKDIV register that determines the I2C clk high phase includes the rise time. So to meet the timing requirements defined in the I2C specification which defines the minimal time SCL has to be high, the rise time has to taken into account. The same applies to the low phase with falling time. In my test on RK3288-Pink2 board, which is not an upstream board yet, if external pull-up resistor is 4.7K, rise_ns is about 700ns. So the measured high_ns is about 3900ns, which is less than 4000ns (the minimum high_ns in I2C specification for Standard-mode). To fix this bug min_low_ns should include fall time and min_high_ns should include rise time. This patch merged the patch from chromium project which can get the rise and fall times for signals from the device tree. This allows us to more accurately calculate timings. see: https://chromium-review.googlesource.com/#/c/232774/ Signed-off-by: Addy Ke <addy.ke@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> [wsa: fixed a typo in the docs] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: cadence: Handle > 252 byte transfersHarini Katakam2015-01-131-73/+102
| | | | | | | | | | | | | The I2C controller sends a NACK to the slave when transfer size register reaches zero, irrespective of the hold bit. So, in order to handle transfers greater than 252 bytes, the transfer size register has to be maintained at a value >= 1. This patch implements the same. The interrupt status is cleared at the beginning of the isr instead of the end, to avoid missing any interrupts. Signed-off-by: Harini Katakam <harinik@xilinx.com> [wsa: added braces around else branch] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: pmcmsp: remove dead codeWolfram Sang2015-01-131-7/+0
| | | | | | | | CPPCHECK rightfully says: drivers/i2c/busses/i2c-pmcmsp.c:151: style: The function 'pmcmsptwi_reg_to_clock' is never used. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* i2c: Remove support for legacy PMLars-Peter Clausen2014-12-222-122/+0
| | | | | | | | | | | | | | There haven't been any I2C driver that use the legacy suspend/resume callbacks for a while now and new drivers are supposed to use PM ops. So remove support for legacy suspend/resume for I2C drivers. Since there aren't any special bus specific things to do during suspend/resume and since the PM core will automatically fallback directly to using the device's PM ops if no bus PM ops are specified there is no need to have any I2C bus PM ops. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* Linux 3.19-rc1v3.19-rc1Linus Torvalds2014-12-211-2/+2
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* Merge tag 'for-linus' of ↵Linus Torvalds2014-12-2110-25/+103
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger/linux Pull ACCESS_ONCE cleanup preparation from Christian Borntraeger: "kernel: Provide READ_ONCE and ASSIGN_ONCE As discussed on LKML http://marc.info/?i=54611D86.4040306%40de.ibm.com ACCESS_ONCE might fail with specific compilers for non-scalar accesses. Here is a set of patches to tackle that problem. The first patch introduce READ_ONCE and ASSIGN_ONCE. If the data structure is larger than the machine word size memcpy is used and a warning is emitted. The next patches fix up several in-tree users of ACCESS_ONCE on non-scalar types. This does not yet contain a patch that forces ACCESS_ONCE to work only on scalar types. This is targetted for the next merge window as Linux next already contains new offenders regarding ACCESS_ONCE vs. non-scalar types" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger/linux: s390/kvm: REPLACE barrier fixup with READ_ONCE arm/spinlock: Replace ACCESS_ONCE with READ_ONCE arm64/spinlock: Replace ACCESS_ONCE READ_ONCE mips/gup: Replace ACCESS_ONCE with READ_ONCE x86/gup: Replace ACCESS_ONCE with READ_ONCE x86/spinlock: Replace ACCESS_ONCE with READ_ONCE mm: replace ACCESS_ONCE with READ_ONCE or barriers kernel: Provide READ_ONCE and ASSIGN_ONCE
| * s390/kvm: REPLACE barrier fixup with READ_ONCEChristian Borntraeger2014-12-181-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Commit 1365039d0cb3 ("KVM: s390: Fix ipte locking") replace ACCESS_ONCE with barriers. Lets use READ_ONCE instead. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * arm/spinlock: Replace ACCESS_ONCE with READ_ONCEChristian Borntraeger2014-12-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Change the spinlock code to replace ACCESS_ONCE with READ_ONCE. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * arm64/spinlock: Replace ACCESS_ONCE READ_ONCEChristian Borntraeger2014-12-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Change the spinlock code to replace ACCESS_ONCE with READ_ONCE. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * mips/gup: Replace ACCESS_ONCE with READ_ONCEChristian Borntraeger2014-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Change the gup code to replace ACCESS_ONCE with READ_ONCE. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * x86/gup: Replace ACCESS_ONCE with READ_ONCEChristian Borntraeger2014-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Change the gup code to replace ACCESS_ONCE with READ_ONCE. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * x86/spinlock: Replace ACCESS_ONCE with READ_ONCEChristian Borntraeger2014-12-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Change the spinlock code to replace ACCESS_ONCE with READ_ONCE. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * mm: replace ACCESS_ONCE with READ_ONCE or barriersChristian Borntraeger2014-12-183-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Let's change the code to access the page table elements with READ_ONCE that does implicit scalar accesses for the gup code. mm_find_pmd is tricky, because m68k and sparc(32bit) define pmd_t as array of longs. This code requires just that the pmd_present and pmd_trans_huge check are done on the same value, so a barrier is sufficent. A similar case is in handle_pte_fault. On ppc44x the word size is 32 bit, but a pte is 64 bit. A barrier is ok as well. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Cc: linux-mm@kvack.org Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * kernel: Provide READ_ONCE and ASSIGN_ONCEChristian Borntraeger2014-12-181-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Let's provide READ_ONCE/ASSIGN_ONCE that will do all accesses via scalar types as suggested by Linus Torvalds. Accesses larger than the machines word size cannot be guaranteed to be atomic. These macros will use memcpy and emit a build warning. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
* | Merge tag 'clk-for-linus-3.19' of ↵Linus Torvalds2014-12-2194-690/+6663
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
| * | clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to ↵Krzysztof Kozlowski2014-12-171-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | domain being gated Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block. This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll. The system hang on one of steps: 1. Disabling unused clocks from audss block. 2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated. Add a workaround for this by enabling the 'mau_epll' clock in probe. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | ARM: OMAP3: clock: fix boot breakage in legacy modeTero Kristo2014-12-161-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new usage of determine_rate and set_rate_and_parent calls for OMAP DPLLs assumes the DPLLs must have two parents defined, even if it is the same clock. Legacy clock data did not fullfill this requirement and caused a boot crash. Fixed by adding the missing parent information to the DPLL clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Fixes: 2e1a7b014f ("ARM: OMAP3+: DPLL: use determine_rate() and...") Cc: Paul Walmsley <paul@pwsan.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Kevin Hilman <khilman@linaro.org> Reported-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIsTero Kristo2014-12-163-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the change for determine_rate clock operation was merged, the OMAP counterpart using these calls was overlooked for some reason, and caused boot failures on at least OMAP4 platforms. Fixed by updating the DPLL API calls to use the new parameters. Signed-off-by: Tero Kristo <t-kristo@ti.com> Fixes: 646cafc6aa ("clk: Change clk_ops->determine_rate") Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Paul Walmsley <paul@pwsan.com> Tested-by: Kevin Hilman <khilman@linaro.org> Reported-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | Merge tag 'for-v3.19/omap-a' of ↵Michael Turquette2014-12-169-63/+238
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into tmp Some OMAP clock/hwmod patches for v3.19. Most of the patches are clock-related. The DPLL implementation is changed to better align to the common clock framework. There is also a patch that removes a few lines from the hwmod code - this patch should have no functional effect. Basic build, boot, and PM test logs for these patches can be found here: http://www.pwsan.com/omap/testlogs/omap-a-for-v3.19/20141113094101/
| * | | clk: Really fix deadlock with mmap_semStephen Boyd2014-12-161-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6314b6796e3c (clk: Don't hold prepare_lock across debugfs creation, 2014-09-04) forgot to update one place where we hold the prepare_lock while creating debugfs directories. This means we still have the chance of a deadlock that the commit was trying to fix. Actually fix it by moving the debugfs creation outside the prepare_lock. Cc: <stable@vger.kernel.org> # 3.18 Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Fixes: 6314b6796e3c "clk: Don't hold prepare_lock across debugfs creation" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: removed lockdep_assert]
| * | | Merge tag 'for-v3.19-exynos-clk-2' of git://linuxtv.org/snawrocki/samsung ↵Michael Turquette2014-12-115-10/+12
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into clk-next - exynos4415 and exynos audio subsystem clk driver (build with PM_SLEEP disabled, resource release) fixes - minor cleanups in drivers/clk/samsung/clk.c (spelling, includes) - modification of the exynos4 HDMI PHY clock definition to model dependency of "sclk_hdmiphy" on the "hdmi" clock
| | * | | clk: samsung: Fix double add of syscore ops after driver rebindKrzysztof Kozlowski2014-12-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During driver unbind the syscore ops were not unregistered which lead to double add on syscore list: $ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/unbind $ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/bind [ 1463.044061] ------------[ cut here ]------------ [ 1463.047255] WARNING: CPU: 0 PID: 1 at lib/list_debug.c:36 __list_add+0x8c/0xc0() [ 1463.054613] list_add double add: new=c06e52c0, prev=c06e52c0, next=c06d5f84. [ 1463.061625] Modules linked in: [ 1463.064623] CPU: 0 PID: 1 Comm: bash Tainted: G W 3.18.0-rc5-next-20141121-00005-ga8fab06eab42-dirty #1022 [ 1463.075338] [<c0014e2c>] (unwind_backtrace) from [<c0011d80>] (show_stack+0x10/0x14) [ 1463.083046] [<c0011d80>] (show_stack) from [<c048bb70>] (dump_stack+0x70/0xbc) [ 1463.090236] [<c048bb70>] (dump_stack) from [<c00233d4>] (warn_slowpath_common+0x74/0xb0) [ 1463.098295] [<c00233d4>] (warn_slowpath_common) from [<c00234a4>] (warn_slowpath_fmt+0x30/0x40) [ 1463.106962] [<c00234a4>] (warn_slowpath_fmt) from [<c020fe80>] (__list_add+0x8c/0xc0) [ 1463.114760] [<c020fe80>] (__list_add) from [<c0282094>] (register_syscore_ops+0x30/0x3c) [ 1463.122819] [<c0282094>] (register_syscore_ops) from [<c0392f20>] (exynos_audss_clk_probe+0x36c/0x460) [ 1463.132091] [<c0392f20>] (exynos_audss_clk_probe) from [<c0283084>] (platform_drv_probe+0x48/0xa4) [ 1463.141013] [<c0283084>] (platform_drv_probe) from [<c0281a14>] (driver_probe_device+0x13c/0x37c) [ 1463.149852] [<c0281a14>] (driver_probe_device) from [<c0280560>] (bind_store+0x90/0xe0) [ 1463.157822] [<c0280560>] (bind_store) from [<c027fd10>] (drv_attr_store+0x20/0x2c) [ 1463.165363] [<c027fd10>] (drv_attr_store) from [<c0143898>] (sysfs_kf_write+0x4c/0x50) [ 1463.173252] [<c0143898>] (sysfs_kf_write) from [<c0142c80>] (kernfs_fop_write+0xbc/0x198) [ 1463.181395] [<c0142c80>] (kernfs_fop_write) from [<c00e2be0>] (vfs_write+0xa0/0x1a8) [ 1463.189104] [<c00e2be0>] (vfs_write) from [<c00e2f00>] (SyS_write+0x40/0x8c) [ 1463.196122] [<c00e2f00>] (SyS_write) from [<c000f2a0>] (ret_fast_syscall+0x0/0x48) [ 1463.203655] ---[ end trace 08f6710c9bc8d8f3 ]--- [ 1463.208244] exynos-audss-clk 3810000.audss-clock-controller: setup completed Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Fixes: 1241ef94ccc3 ("clk: samsung: register audio subsystem clocks using common clock framework") Cc: <stable@vger.kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | | clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmiAndrzej Hajda2014-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sclk_hdmiphy clock is generated by HDMI-PHY and depends on hdmi gate clock. The patch models this dependency using parent/child hirerarchy. The patch fixes issue with system hangs during mixer device access, mixer uses sclk_hdmiphy descendant clock. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | | clk: samsung: exynos4415: Fix build with PM_SLEEP disabledKrzysztof Kozlowski2014-12-021-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following build errors when PM_SLEEP is disabled (e.g. by disabling SUSPEND and HIBERNATION): drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_init’: drivers/clk/samsung/clk-exynos4415.c:982:2: error: ‘exynos4415_ctx’ undeclared (first use in this function) drivers/clk/samsung/clk-exynos4415.c:982:2: note: each undeclared identifier is reported only once for each function it appears in drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_dmc_init’: drivers/clk/samsung/clk-exynos4415.c:1123:2: error: ‘exynos4415_dmc_ctx’ undeclared (first use in this function) make[3]: *** [drivers/clk/samsung/clk-exynos4415.o] Error 1 Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | | clk: samsung: remove unnecessary inclusion of header files from clk.hPankaj Dubey2014-12-022-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's remove unnecessary include of header files from clk.h and add required one in clk.c Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> [s.nawrocki@samsung.com: dropped removal of '#include <linux/syscore_ops.h>'] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | | clk: samsung: remove unnecessary CONFIG_OF from clk.cPankaj Dubey2014-12-021-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unnecessary CONFIG_OF from samsung/clk.c. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | | clk: samsung: Spelling s/bwtween/between/Pankaj Dubey2014-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a typo in comment section of "struct samsung_clk_provider". Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | | | clk: mmp: fix sparse non static symbol warningWei Yongjun2014-12-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes the following sparse warnings: drivers/clk/mmp/clk-frac.c:113:6: warning: symbol 'clk_factor_init' was not declared. Should it be static? Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | | | clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso2014-12-0414-49/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | | | clk: change clk_debugfs_add_file to take a struct clk_hwTomeu Vizoso2014-12-042-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of struct clk, as this should be only used by providers. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | | | clk: Don't expose __clk_get_accuracyTomeu Vizoso2014-12-042-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As it's only used internally, in drivers/clk/clk.c. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | | | clk: Don't try to use a struct clk* after it could have been freedTomeu Vizoso2014-12-041-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As __clk_release could call kfree on clk and then we wouldn't have a safe way of getting the module that owns the clock. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Fixes: fcb0ee6a3d33 ("clk: Implement clk_unregister") Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | | | clk: Remove unused function __clk_get_prepare_countTomeu Vizoso2014-12-042-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | | | Merge tag 'ib-mfd-regulator-clk-v3.19' of ↵Michael Turquette2014-11-298-24/+374
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into clk-next Immutable branch between MFD, Regulator and Clk, due for v3.19
| * \ \ \ \ Merge tag 'v3.19-rockchip-clk2' of ↵Michael Turquette2014-11-298-50/+315
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next - clock phase setting capability for the rk3288 mmc clocks - pll init to allow syncing to actual rate table values - some more exported clocks - fixes for some clocks (typos etc) all of them not yet used in actual drivers
| | * | | | | clk: rockchip: Add support for the mmc clock phases using the frameworkAlexandru M Stan2014-11-285-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the 2 physical clocks for the mmc (drive and sample). They're mostly there for the phase properties, but they also show the true clock (by dividing by RK3288_MMC_CLKGEN_DIV). The drive and sample phases are generated by dividing an upstream parent clock by 2, this allows us to adjust the phase by 90 deg. There's also an option to have up to 255 delay elements (40-80 picoseconds long). This driver uses those elements (under the assumption that they're 60 ps long) to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as 90 deg if the delay elements are as big as 80 ps, so a finer division (smaller than 22.5) was not picked because the phase might not be monotonic anymore. Suggested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-09 13:45:11 +0100